Memory controller and link identification method

Abstract

The present invention relates to a memory controller and link identification method, coupled to a memory device for controlling access operations of the memory device, comprising a host interface and a microprocessor. The microprocessor, coupled to the host interface, sets a predetermined parameter to a specific value after the memory controller is powered on and initiates a link establishment process to attempt to establish a transmission link through the host interface. The predetermined parameter is one of multiple capability parameters of the host interface, and the predetermined parameter is related to reception by the host interface. After the link establishment process is completed, the microprocessor further identifies a target device to establish a transmission link with the host interface based on at least one of multiple attribute parameters associated with the transmission link and the specific value.

Description

Technical Field

[0001] The invention relates to a link identification method applicable to a product testing process and a memory controller implementing the link identification method. Background Art

[0002] With the rapid advancement of data storage technology in recent years, numerous data storage devices, such as memory cards conforming to Secure Digital (SD) / Multi Media Card (MMC), Compact Flash (CF), Memory Stick (MS), and Extreme Digital (XD) specifications, solid-state drives (SSDs), embedded Multi Media Card (eMMC), and Universal Flash Storage (UFS), have been widely adopted for various applications. Consequently, the demand for data storage devices in various fields has also grown significantly.

[0003] Suppliers of data storage devices can usually provide testing services to their customers. For example, after the client packages the chip of the data storage device according to its needs, it can hand over the packaged chip to the supplier for testing. In the test process, the chip to be tested may need to be connected to different devices at different test stages / test stations, or the transmission interface of the chip to be tested may have different connection methods according to the test items. In addition, the transmission interface of the chip to be tested may also need to establish a link with the corresponding interface due to test requirements during the test process. In order to correctly identify the object to be linked to the transmission interface of the chip to be tested during the test process, so as to avoid the inability to complete the test process due to link identification errors, an effective link identification method is required. Summary of the Invention

[0004] An object of the present invention is to correctly identify the object that establishes a link with the transmission interface of the chip to be tested during the test process, so as to avoid the test process from being unable to complete due to link identification errors.

[0005] According to one embodiment of the present invention, a memory controller is coupled to a memory device for controlling access operations of the memory device, and includes a host interface and a microprocessor. The microprocessor is coupled to the host interface and, after power is supplied to the memory controller, sets a predetermined parameter to a specific value and initiates a link establishment process to attempt to establish a transmission link through the host interface. The predetermined parameter is one of multiple capability parameters of the host interface, and the predetermined parameter is related to reception by the host interface. After the link establishment process is completed, the microprocessor further identifies a target device for establishing a transmission link with the host interface based on at least one of multiple attribute parameters associated with the transmission link and the specific value.

[0006] According to one embodiment of the present invention, a link identification method is applicable to a memory controller, which is coupled to a memory device for controlling access operations of the memory device. The link identification method includes: after the memory controller is powered on, setting a predetermined parameter of the memory controller to a special value, wherein the predetermined parameter is one of multiple capability parameters of the memory controller and the predetermined parameter is related to reception of a host interface of the memory controller; executing a link establishment process to attempt to establish a transmission link through the host interface; and after the link establishment process is completed, identifying a target device for establishing a transmission link with the host interface based on at least one of multiple attribute parameters associated with the transmission link and the special value. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 FIG. 1 is a schematic diagram showing a data storage device according to an embodiment of the present invention.

[0008] Figure 2 FIG. 1 is a schematic diagram showing a testing device with a device under test installed thereon according to an embodiment of the present invention.

[0009] Figure 3 FIG. 4 is a flow chart showing a link identification method according to an embodiment of the present invention.

[0010] Figure 4 FIG. 1 is a flow chart showing a testing method of an application link identification method according to an embodiment of the present invention.

[0011]

Explanation of symbols

[0012] 100,200: Data storage device

[0013] 110:Memory controller

[0014] 112: Microprocessor

[0015] 112C: Program code

[0016] 112M: Read-only memory

[0017] 114:Memory interface

[0018] 116: Buffer memory

[0019] 118,218:Host interface

[0020] 120: Memory device

[0021] 130: Host device

[0022] 132: Encoder

[0023] 134:Decoder

[0024] 250:Testing device

[0025] 251: Connector

[0026] 31,32: Routing

[0027] P_TX0, P_TX1: Transmit pins

[0028] P_RX0, P_RX1: Receive pins DETAILED DESCRIPTION

[0029] In the following, many specific details are described to provide a thorough understanding of the embodiments of the present invention. However, those skilled in the art will still understand how to implement the present invention in the absence of one or more specific details or in the case of relying on other methods, components or materials. In other cases, well-known structures, materials or operations are not shown or described in detail to avoid obscuring the main concepts of the present invention.

[0030] References throughout this specification to "one embodiment," "an embodiment," "an example," or "an example" mean that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in at least one of the multiple embodiments of the present invention. Thus, the appearances of the phrases "in one embodiment," "in an embodiment," "in an example," or "in an example" in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable combinations and / or subcombinations in one or more embodiments or examples.

[0031] To further enhance the understanding of the objectives, features, and advantages of the present invention, specific embodiments of the present invention are described below with reference to the accompanying drawings. These embodiments are intended to illustrate the spirit of the present invention and are not intended to limit its scope. It should be understood that the following embodiments can be implemented using software, hardware, firmware, or any combination thereof.

[0032] Figure 1FIG1 is a schematic diagram illustrating a data storage device 100 according to an embodiment of the present invention. Data storage device 100 may include a memory device 120 and a memory controller 110. Memory controller 110 is used to access memory device 120 and control the operation of memory device 120. Memory device 120 may be a non-volatile (NV) memory device (e.g., a flash memory) and may include one or more memory elements (e.g., one or more flash memory dies, one or more flash memory chips, or other similar elements).

[0033] According to one embodiment of the present invention, the memory controller 110 includes a microprocessor 112, a read-only memory (ROM) 112M, a memory interface 114, a buffer memory 116, and a host interface 118. The ROM 112M is used to store a program code 112C. The program code 112C may include one or more program modules, such as boot loader code. When the host device 130 supplies power to the data storage device 100, the microprocessor 112 may execute the program code 112C to perform initialization operations and load a group of in-system programming (ISP) codes (not shown) from the memory device 120. The microprocessor 112 can execute the ISP codes to enable the data storage device 100 to have various functions. According to this embodiment, the ISP code group may include (but is not limited to) multiple program modules related to access (e.g., reading, writing, and erasing), such as a read operation module, a table lookup module, a wear leveling module, a read refresh module, a read reclaim module, a garbage collection module, a sudden power off recovery (SPOR) module, and an uncorrectable error correction code (UECC) module, for performing read, table lookup, wear leveling, read refresh, read reclaim, garbage collection, sudden power off recovery, and error handling for UECC errors, respectively. The memory interface 114 includes an encoder 132 and a decoder 134. The encoder 132 is used to encode data written to the memory device 120 to generate a corresponding check code (or error correction code, ECC). The decoder 134 is used to decode data read from the memory device 120.

[0034] The memory controller 110 can utilize its internal components to perform various control operations, such as utilizing a memory interface 114 to control access operations of the memory device 120 (particularly, access operations to at least one block or at least one data page), utilizing a buffer memory 116 to perform required buffering, and utilizing a host interface 118 to communicate with a host device 130.

[0035] The host device 130 may issue commands, such as read commands or write commands, to the data storage device 100 to access data stored in the memory device 120 , or to further control and manage the data storage device 100 .

[0036] In one embodiment, the buffer memory 116 is implemented as a random access memory (RAM). For example, the buffer memory 116 may be a static random access memory (SRAM), but the present invention is not limited thereto. In other embodiments, the buffer memory 116 may be a dynamic random access memory (DRAM).

[0037] In one embodiment, the host interface 118 may be a hardware interface with corresponding firmware / software design, used to transmit communication signals, transfer write / read data, and control task scheduling between the memory controller 110 and the host device 130. For example, the memory controller 110 / microprocessor 112 may execute corresponding firmware or software to enable the host interface 118 to perform the above operations.

[0038] In one embodiment, the memory controller 110 communicates with the host device 130 via the host interface 118 using a standard communication protocol. For example, the above-mentioned standard communication protocols include (but are not limited to): Universal Serial Bus (USB) standard, Secure Digital (SD) interface standard, Ultra High Speed-I (UHS-I) interface standard, Ultra High Speed-II (UHS-II) interface standard, CompactFlash (CF) interface standard, Multimedia Card (MMC) interface standard, Embedded Multimedia Card (eMMC) interface standard, Universal Flash Memory (UFS) interface standard, Advanced Technology Attachment (ATA) standard, Serial ATA (SATA) standard, Peripheral Component Interconnect Express (PCI-E) standard, and Parallel Advanced Technology Attachment (PATA) standard.

[0039] As described above, the manufacturer or supplier of the memory controller 110 or the data storage device 100 can test the packaged chip or device. During the testing process, the chip or device to be tested may need to be connected to different devices at different test stages / test stations, or the transmission interface of the chip or device to be tested may have different connection methods depending on the test items. In addition, the transmission interface of the chip or device to be tested may also need to establish a connection with the corresponding interface of a peer device during the testing process due to test requirements.

[0040] For example, a given test process may involve two test phases / test stations. In the first test phase, a chip or device to be tested (e.g., a chip including the memory controller 110 or the data storage device 100) (hereinafter referred to as the device to be tested for simplicity) may communicate with a host device (e.g., Figure 1The host device 130 shown is connected to the host device 130, and the host device loads the software / firmware program code required for the test process into the device under test, and sets the relevant parameters or registers required for the test process for the device under test. In the first test phase, the above operation can be used to test whether the communication between the host interface 118 and the host device 130 is operating normally. In the second test phase, the device under test is not connected to any host device, but is installed in a test device for testing. This test device can be an assembly jig or a specific fixture. Therefore, in the second test phase, the test device should ignore any instructions from the host device (if any). In the second test phase, the test device will perform a loopback test and perform a self-test under the control of the memory controller 110, for example, to test whether the read, write, clear and other operations of the memory device 120 are normal, thereby testing whether the communication between the memory controller 110 and the memory device 120 is operating normally.

[0041] It should be noted that the host device to which the device under test is connected in the first test phase and the host device to which the device under test is connected when it eventually becomes a product are usually different devices. In the test process, the host device 130 connected to the data storage device 100 may be a chip designed specifically for performing product testing. When the data storage device 100 eventually becomes a product, for example, in some embodiments, the data storage device 100 may be a portable memory device (for example, a memory card that complies with SD / MMC, CF, MS, or XD standards), and the host device 130 is an electronic device that can be connected to the data storage device, such as a mobile phone, a notebook computer, a desktop computer, etc. For another example, in other embodiments, the data storage device 100 may be a solid-state drive or an embedded storage device that complies with UFS or eMMC specifications, and may be set in an electronic device, such as a mobile phone, a notebook computer, or a desktop computer, and the host device 130 may be a processor of the electronic device.

[0042] Figure 2 FIG. 1 is a schematic diagram showing a test device with a device under test installed thereon according to an embodiment of the present invention. In this embodiment, the device under test is a data storage device 200, and the data storage device 200 can be as follows: Figure 1The data storage device 100 is shown. The test device 250 may include a slot (not shown), and the data storage device 200 can be installed in the test device 250 by being inserted into the slot. In addition, the test device 250 may include at least one or more transmission pins, such as transmission pins P_TX0 and P_TX1, one or more reception pins, such as reception pins P_RX0 and P_RX1, and a connector 251. The test device 250 can obtain power through the connector 251. For example, the connector 251 can be a USB plug, and the test device 250 can obtain power by inserting the connector 251 into another powered USB socket. In this embodiment, the host interface 218 of the data storage device 200 can be a two-lane design, that is, the host interface 218 can include two transmission terminals TX0 and TX1 and two reception terminals RX0 and RX1. The transmit pins P_TX0 and P_TX1 are used to connect to the transmit terminals TX0 and TX1 of the host interface 218, respectively. The receive pins P_RX0 and P_RX1 are used to connect to the receive terminals RX0 and RX1 of the host interface 218, respectively. Figure 2 The reference numeral 218 indicates that the transmitters TX0 and TX1 and the receivers RX0 and RX1 are included in the host interface 218, but does not limit the components included in the host interface 218. Those skilled in the art will appreciate that a host interface may include other components not shown in the figure to implement corresponding operations.

[0043] In an embodiment of the present invention, to enable the data storage device 200 to perform a loopback test, the test device 250 may have a loopback layout. As shown, the test device 250 may be arranged with traces 31 and 32. Trace 31 connects the transmit pin P_TX0 and the receive pin P_RX0, and trace 32 connects the transmit pin P_TX1 and the receive pin P_RX1. When the data storage device 200 is installed in the test device 250, the transmit pin P_TX0 is connected to the transmit terminal TX0, and the receive pin P_RX0 is connected to the receive terminal RX0, so that the transmit terminal TX0 can be connected to the receive terminal RX0 through trace 31. Similarly, when the data storage device 200 is installed in the test device 250, the transmit pin P_TX1 is connected to the transmit terminal TX1, and the receive pin P_RX1 is connected to the receive terminal RX1, so that the transmit terminal TX1 can be connected to the receive terminal RX1 through trace 32. In the second test phase, the data storage device 200 may utilize the return layout to perform a return test to test whether the transmission and reception on the two lanes of the host interface operate normally.

[0044] Generally speaking, after receiving power, the data storage device 100 / 200 will perform a link establishment process to attempt to establish a transmission link with the corresponding interface of a peer device through the host interface. For example, when the data storage device 100 / 200 is implemented as a data storage device compliant with the UFS specification, because UFS uses the physical layer M-PHY developed by the Mobile Industry Processor Interface (MIPT) Alliance, the data storage device 100 / 200 must perform a link establishment process (Link Flow) in accordance with the standardized communication protocol (Unified Protocol, commonly known as UniPro) established by the MIPI Alliance after receiving power.

[0045] However, because the device under test (e.g., a data storage device) is connected to a host device during the first test phase and connected to its own transmission interface via the return layout of the test device 250 during the second test phase, the device under test may successfully establish a transmission link during the link establishment process in both test phases. Therefore, simply determining whether a transmission link has been successfully established is insufficient to identify which device the device under test is currently connected to. If the device under test cannot correctly distinguish between the two devices during the test process, a link identification error may occur, preventing the test process from completing.

[0046] In order to correctly identify the object establishing a link with the transmission interface of the device under test (eg, the host interface 118 / 218 ) during the test process and avoid the aforementioned problem of failing to complete the test process due to link identification errors, an effective link identification method is required.

[0047] Figure 3 1 is a flow chart showing a link identification method according to an embodiment of the present invention, comprising the following steps:

[0048] Step S302: After power is supplied to the data storage device 100 / 200 and / or the memory controller 110, a predetermined parameter is set to a specific value. According to one embodiment of the present invention, the predetermined parameter is one of a plurality of capability parameters of the memory controller 110, such as a capability parameter related to reception at the host interface 118 / 218. Furthermore, according to one embodiment of the present invention, the parameter selected for setting a specific value in this step is a capability parameter that will be exchanged during the link establishment process. For example, the transmitting and receiving ends of the transmission link will each provide their capability parameters to the other end during the communication process for reference during subsequent parameter settings.

[0049] Step S304: Execute a link establishment process to attempt to establish a transmission link via the host interface. Note that, in this embodiment of the present invention, step S302 must be executed before step S304. That is, setting specific values for the predefined parameters must be completed before initiating the link establishment process. Furthermore, according to one embodiment of the present invention, the data storage device 100 / 200 may execute the link establishment process (Link Flow) in accordance with the aforementioned standardized communication protocol (UniPro).

[0050] Step S306: After the link establishment process is completed, a target device for establishing a transmission link with the host interface is identified based on at least one of the multiple attribute parameters associated with the transmission link and the aforementioned special value. As described above, during the link establishment process, the transmitting end and the receiving end of the transmission link each provide their capability parameters to the other end, and the transmitting end and the receiving end each follow the same rules to set the multiple attribute parameters associated with the transmission link based on their own and the other end's capability parameters. After the attribute parameter setting is completed, the final value of the attribute parameter associated with the aforementioned predetermined parameter among the multiple attribute parameters can be used to determine whether the target device establishing a transmission link with the data storage device 100 / 200 is another host device of the same level or the data storage device 100 / 200 itself.

[0051] According to an embodiment of the present invention, the link identification method may further include: after identifying the target device that establishes a transmission link with the host interface, determining a next operation according to an identification result of the target device.

[0052] More specifically, according to one embodiment of the present invention, after power is supplied to the memory controller 110, the microprocessor 112 sets the predetermined parameter to a specific value, for example, to a maximum value allowed, and begins executing a link establishment process to attempt to establish a transmission link through the host interface. According to one embodiment of the present invention, the predetermined parameter may be a capability parameter related to the operating time required by the host interface 118 / 218. For example, the predetermined parameter may be a receiver capability parameter RX_Hibern8Time_Capability, which specifies the minimum time the receiver must remain in hibernate mode after entering hibernate mode. Another example may be a receiver capability parameter RX_Min_ActivateTime_Capability, which specifies the time required for the receiver to initiate its first action after being awakened. According to another embodiment of the present invention, the aforementioned predetermined parameter may also be a parameter related to a synchronization pattern used by the host interface 118 / 218. For example, the aforementioned predetermined parameter may be a parameter RX_HS_G1_SYNC_LENGTH of the receiving end (where G1 represents the first speed gear Gear 1 of the high-speed (HS) mode and can be extended to other speed gears defined by MIPI). This parameter is used to specifically specify the synchronization pattern length used by the receiving end.

[0053] It should be noted that the parameters described above are merely examples of how the present invention may be implemented, and the present invention is not limited to the use of only these parameters. As described above, in embodiments of the present invention, the microprocessor may select one or more parameters associated with the receiving end of host interface 118 / 218, or parameters associated with the receiving operation of memory controller 110 and / or host interface 118 / 218, for specific value settings. Furthermore, the parameters selected for specific value settings are those that will be exchanged between the transmitter and receiver during the link establishment process.

[0054] After the parameters of the specific values are set, the microprocessor 112 can start a link establishment process. Table 1 below shows the link flow specified by the UniPro specification, where the abbreviation PA refers to the physical adapter layer.

[0055]

[0056] Table 1: Link Flow Example

[0057] For a detailed description of the linking process, please refer to UniPro Specification Version 1.61, Chapter 5.6.3.

[0058] In phase 5 of the link process, the transmitter and receiver exchange capability parameters and apply the resulting capability parameters in a degraded manner. For example, the UniPro specification defines the setting method for the attribute parameter PA_Hibern8Time as follows:

[0059] PA_Hibern8Time=max(TX_Hibern8Time_Capability, peer_RX_Hibern8Time_Capability) equation (1)

[0060] The parameter PA_Hibern8Time specifies the minimum time a device must remain in hibernate mode after entering it. max(A,B) is calculated by taking the maximum value between A and B. The parameter TX_Hibern8Time_Capability specifies the minimum time a transmitter must remain in hibernate mode after entering it. The parameter peer_RX_Hibern8Time_Capability specifies the minimum time a peer receiver must remain in hibernate mode after entering it (obtained by the transmitter through parameter exchange). Generally speaking, since a shorter return time from hibernate mode indicates a faster device, setting the parameter by taking the maximum value is equivalent to degrading the capability parameter of the faster device.

[0061] For another example, the UniPro specification defines the setting method of the attribute parameter PA_TActivate as follows:

[0062] PA_TActivate=peer_RX_Min_ActivateTime_Capability Formula (2)

[0063] The parameter PA_TActivate is used to specify the time required from being awakened to starting the first action, and the parameter peer_RX_Hibern8Time_Capability is the time required from being awakened to starting the first action of the peer receiving end (obtained by the transmitting end through parameter exchange).

[0064] As another example, the UniPro specification defines the setting method for the attribute parameter PA_TxHsG1SyncLength as follows:

[0065] PA_TxHsG1SyncLength=peer_RX_HS_G1_SYNC_LENGTH Formula (3)

[0066] The parameter PA_TxHsG1SyncLength is used to specify the synchronization pattern length used at the first speed level in the overdrive mode. The parameter peer_RX_HS_G1_SYNC_LENGTH is the synchronization pattern length used at the first speed level in the overdrive mode by the peer receiver (obtained by the transmitter through parameter exchange).

[0067] In an embodiment of the present invention, the microprocessor 112 may set a special value for at least one of the selected predetermined parameters (such as but not limited to the aforementioned parameters RX_Hibern8Time_Capability, RX_Min_ActivateTime_Capability, and / or RX_HS_G1_SYNC_LENGTH) before the link establishment process begins, for example, setting it to a very large special value (such as hexadecimal 0x7D).

[0068] During the link establishment process, the transmitter obtains the receiver's capability parameters through parameter exchange and can, as in the above example, set various attribute parameters associated with the transmission link based on the transmitter and / or receiver's capability parameters. For example, assuming that the data storage device 100 / 200 is currently connected to the host device 130 during the first testing phase, since the data storage device 100 and the host device 130 are currently exchanging parameters during the link establishment process, the values entered into the parameters peer_RX_Hibern8Time_Capability, peer_RX_Min_ActivateTime_Capability, and peer_RX_HS_G1_SYNC_LENGTH in the above example will be the parameters RX_Hibern8Time_Capability, RX_Hibern8Time_Capability, and RX_HS_G1_SYNC_LENGTH set by the host device 130. In contrast, assuming that the data storage device 100 / 200 is currently in the second test phase and is connected to its own transmission interface via the return layout of the test device 250, then because the data storage device 100 will now exchange parameters with itself during the link establishment process, the values entered into the parameters peer_RX_Hibern8Time_Capability, peer_RX_Min_ActivateTime_Capability, and peer_RX_HS_G1_SYNC_LENGTH in the above example will be the parameters RX_Hibern8Time_Capability, RX_Hibern8Time_Capability, and RX_HS_G1_SYNC_LENGTH set by the data storage device 100 / 200 itself.

[0069] In this way, the microprocessor 112 can determine whether the object establishing a transmission link with the data storage device 100 / 200 is another host device of the same level or the data storage device 100 / 200 itself based on the final value set to the attribute parameter related to the aforementioned predetermined parameter. More specifically, when the microprocessor 112 selects the capability parameter RX_Hibern8Time_Capability as the predetermined parameter to be set to a special value, if the microprocessor 112 determines that the attribute parameter PA_Hibern8Time in equation (1) is set to this special value after the link establishment process is completed, it can be determined that the object currently establishing a transmission link with the host interface 118 / 218 is the memory controller 110 itself. On the other hand, if the microprocessor 112 determines that the attribute parameter PA_Hibern8Time in equation (1) is not equal to the special value after the link establishment process is completed, it can be determined that the object currently establishing a transmission link with the host interface 118 / 218 is not the memory controller 110 itself, but a host device.

[0070] Similarly, when the microprocessor 112 selects the capability parameter RX_Min_ActivateTime_Capability and / or RX_HS_G1_SYNC_LENGTH as a predetermined parameter and sets a specific value, if the microprocessor 112 determines that the attribute parameters in formula (2) and / or formula (3) are set to the specific value, it can be determined that the object currently establishing a transmission link with the host interface 118 / 218 is the memory controller 110 itself. If the microprocessor 112 determines that the attribute parameters in formula (2) and / or formula (3) are not equal to the specific value after the link establishment process is completed, it can be determined that the object currently establishing a transmission link with the host interface 118 / 218 is not the memory controller 110 itself, but a host device.

[0071] After the microprocessor 112 identifies the target device (ie, determines that the object currently establishing a transmission link with the host interface 118 / 218 is the memory controller 110 itself or a host device), the microprocessor 112 may further determine the next operation based on the target device identification result.

[0072] Figure 4 1 is a flow chart showing a test method of an application link identification method according to an embodiment of the present invention, comprising the following steps:

[0073] Step S402: The device under test (eg, the data storage device 100 / 200) starts executing the test firmware after being powered on.

[0074] Step S404: Set at least one predetermined parameter to a corresponding special value.

[0075] Step S406: Start a link establishment process to try to establish a transmission link with another party (eg, the memory controller 110 itself or a host device) using the host interface.

[0076] Step S408: The link establishment process is completed.

[0077] Step S410: Determine whether, among the multiple attribute parameters associated with the transmission link, the attribute parameter associated with the predetermined parameter used in step S404 is set to a specific value to identify a target device establishing a transmission link with the host interface. If not, the target device is a host device, and the device under test executes step S412. If so, the target device is a non-host device, and the device under test executes step S414.

[0078] Step S412: Wait for instructions from the target device (host device).

[0079] Step S414: Execute a test process. As described above, if it is determined that the device under test is not connected to a host device, it can be determined that the test device is currently in the second test phase / test station. At this time, the test device should ignore any instructions from the host device (if any) and directly execute the test process set in the second test phase, such as the self-test and return test mentioned above.

[0080] In conventional technology, in order to allow the second test phase to simply perform a self-test, the return test is arranged in the first test phase, and the return layout is set in the first test station. Under this arrangement, the device under test cannot successfully establish a transmission link in the second test phase, so the test device can be judged in which test phase / test station it is currently in based on whether the transmission link has been successfully established. However, the return layout arranged in the first test station may cause some additional link error problems. In order to avoid the occurrence of link errors, the return layout is changed to be set in the second test station, and the return test is changed to be arranged in the second test phase. However, as mentioned above, since the device under test may successfully establish a transmission link in the link establishment process of both test phases. Therefore, it is not sufficient to identify which device the device under test is currently linking with based solely on whether the transmission link has been successfully established. If the device under test cannot correctly distinguish in the test process, the problem of the test process being unable to be completed due to link identification errors will occur. For example, in Figure 4 In the process, if step S404 is omitted and only step S410 is used to determine whether the transmission link has been successfully established, no matter which test phase the test device is currently in, only step S412 will be executed.

[0081] Different from conventional techniques, the link identification method proposed in the present invention allows the microprocessor 112 to simply and accurately identify the test stage the test device is currently in by setting special parameter values, thereby effectively solving the problems of conventional techniques.

[0082] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

Claims

1. A memory controller, coupled to a memory device, for controlling access operations of the memory device, comprising: A host interface; as well as A microprocessor is coupled to the host interface and is used to set a predetermined parameter to a specific value after the memory controller is powered on, and to start executing a link establishment process to attempt to establish a transmission link through the host interface. The predetermined parameter is one of a plurality of capability parameters of the host interface, and the predetermined parameter is related to the reception of the host interface, and After the link establishment process is completed, the microprocessor further identifies a target device that establishes the transmission link with the host interface according to at least one of a plurality of attribute parameters associated with the transmission link and the special value.

2. The memory controller according to claim 1, wherein During the link establishment process, the microprocessor further obtains a plurality of capability parameters of the target device and sets the attribute parameters associated with the transmission link according to the capability parameters of the host interface and / or the target device.

3. The memory controller according to claim 2, wherein: After the link establishment process is completed, the microprocessor determines whether the target device is the memory controller itself by determining whether at least one of the attribute parameters associated with the transmission link is set to the special value.

4. The memory controller according to claim 1, wherein After the microprocessor identifies the target device, the microprocessor further determines a next operation according to an identification result of the target device.

5. The memory controller according to claim 4, wherein: When the microprocessor determines, based on the identification result, that the target device establishing the transmission link with the host interface is the memory controller itself, the microprocessor starts to execute a test process.

6. The memory controller according to claim 4, wherein: When the microprocessor determines, based on the identification result, that the target device establishing the transmission link with the host interface is not the memory controller itself, the microprocessor waits for an instruction from the target device.

7. A testing device comprising the memory controller according to claim 1, characterized in that: The memory controller is installed in the test device, and the test device includes: A transmission pin coupled to a transmission end of the host interface; a receiving pin coupled to a receiving end of the host interface; and A trace connects the transmitting pin and the receiving pin.

8. A link identification method, applicable to a memory controller, the memory controller being coupled to a memory device for controlling access operations of the memory device, the link identification method comprising: After the memory controller is powered on, setting a predetermined parameter of the memory controller to a specific value, wherein the predetermined parameter is one of a plurality of capability parameters of the memory controller and is related to reception of a host interface of the memory controller; executing a link establishment process to attempt to establish a transmission link through the host interface; as well as After the link establishment process is completed, a target device for establishing the transmission link with the host interface is identified according to at least one of a plurality of attribute parameters associated with the transmission link and the special value.

9. The link identification method according to claim 8, wherein: The step of executing a link establishment process to attempt to establish a transmission link through the host interface also includes: obtaining a plurality of capability parameters of the target device; and The attribute parameters associated with the transmission link are set according to the capability parameters of the host interface and / or the target device.

10. The link identification method according to claim 9, wherein: After the link establishment process is completed, the step of identifying a target device for establishing the transmission link with the host interface based on at least one of a plurality of attribute parameters associated with the transmission link and the special value further includes: determining whether one of the attribute parameters associated with the transmission link is set to the special value; and When one of the attribute parameters associated with the transmission link is set to the special value, determining that the target device is the memory controller itself; and When one of the attribute parameters associated with the transmission link is not set to the special value, it is determined that the target device is not the memory controller itself.

11. The link identification method according to claim 8, wherein: After identifying the target device, the link identification method further includes: The next operation of the memory controller is determined according to an identification result of the target device.

12. The link identification method according to claim 11, wherein: When the identification result shows that the target device is the memory controller itself, the link identification method further includes: Start executing a test process.

13. The link identification method according to claim 11, wherein: When the identification result shows that the target device is not the memory controller itself, the link identification method further includes: Waiting for instructions from the target device.

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