Memory control circuit among multiple chips

Abstract

The application relates to a storage control circuit between multiple chips, which is characterized in that multiple processing chips are connected with a storage chip, and the multiple processing chips transmit indication signals to each other through general input and output interfaces between the multiple processing chips, so that the access permission control of the multiple processing chips to the storage chip is completed, the multiple processing chips can reasonably and orderly share one storage chip, one storage chip can provide data for the multiple processing chips, only one packaging substrate can be used when the chips are packaged, the number of packaged chips on the packaging substrate can be reduced due to the fact that the multiple processing chips share one storage chip, and the packaging size is reduced under the condition of ensuring the same functions.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a storage control circuit for multiple chips. Background Technology

[0002] With the development of wireless technology, more and more off-chip communication devices support Bluetooth functionality. Adding a Bluetooth chip to traditional hearing aids enables Bluetooth transmission, allowing audio data from smart devices to be transmitted to the hearing aid, ensuring the accuracy of the received audio data. However, in Bluetooth hearing aids, because neither the digital signal processing chip nor the Bluetooth chip has internal memory, they cannot directly store algorithm programs and require external storage units. Therefore, in related technologies, Bluetooth hearing aids typically have four chip dies: one for the digital signal processing chip and one for the Bluetooth chip, each with corresponding FLASH memory. During the packaging process, the digital signal processing chip die and its corresponding FLASH memory die are packaged together once, and then the entire device is packaged a third time. This results in a relatively large Bluetooth hearing aid, making it inconvenient for patients to use. Summary of the Invention

[0003] Therefore, to address the aforementioned technical problems, this application provides a small-sized and low-cost inter-chip memory control circuit, comprising:

[0004] Memory chips;

[0005] A first processing chip and a second processing chip, wherein the general-purpose input / output interface of the first processing chip is connected to the general-purpose input / output interface of the second processing chip;

[0006] A first control unit is connected between the serial peripheral output interface of the first processing chip and the serial peripheral input interface of the storage chip.

[0007] And a second control unit, which is connected between the serial peripheral output interface of the second processing chip and the serial peripheral input interface of the storage chip;

[0008] The serial peripheral output interface of the memory chip is connected to the serial peripheral input interface of the first processing chip and the second processing chip, respectively.

[0009] In one of the embodiments, the first control unit controls the connection state of the channel between the serial peripheral output interface of the first processing chip and the serial peripheral input interface of the storage chip based on the indication signal transmitted between the general input / output interface of the first processing chip and the general input / output interface of the second processing chip; and the second control unit controls the connection state of the channel between the serial peripheral output interface of the second processing chip and the serial peripheral input interface of the storage chip based on the indication signal transmitted between the general input / output interface of the first processing chip and the general input / output interface of the second processing chip.

[0010] In one of the embodiments, the first control unit comprises a first type of tri-state buffer, and the second control unit comprises a second type of tri-state buffer.

[0011] The input end of the first type of tri-state buffer is connected with the serial peripheral output interface of the first processing chip, the enable end of the first type of tri-state buffer is connected with the general input / output interface of the first processing chip, and the output end of the first type of tri-state buffer is connected with the serial peripheral input interface of the storage chip.

[0012] The input end of the second type of tri-state buffer is connected with the serial peripheral output interface of the second processing chip, the enable end of the second type of tri-state buffer is connected with the general input / output interface of the second processing chip, and the output end of the second type of tri-state buffer is connected with the serial peripheral input interface of the storage chip.

[0013] In the case that the general input / output interface of the first processing chip transmits a first type of indication signal to the general input / output interface of the second processing chip, the first type of tri-state buffer is in a conducting state, and the second type of tri-state buffer is in a blocking state.

[0014] In the case that the general input / output interface of the first processing chip transmits a second type of indication signal to the general input / output interface of the second processing chip, the first type of tri-state buffer is in a blocking state, and the second type of tri-state buffer is in a conducting state.

[0015] In one of the embodiments, the first control unit comprises a first type of tri-state buffer, and the second control unit comprises a second type of tri-state buffer.

[0016] The two NOT gates are connected in series between the enable end of the first type of tri-state buffer and the general input / output interface of the first processing chip.

[0017] In one of the embodiments, the first control unit comprises a first type of tri-state buffer, and the second control unit comprises a second type of tri-state buffer.

[0018] The input end and the enable end of the first tri-state buffer are connected with the serial peripheral output interface of the first processing chip, and the output end of the first tri-state buffer is connected with the serial peripheral input interface of the storage chip.

[0019] The input end and the enable end of the second tri-state buffer are connected with the serial peripheral output interface of the second processing chip, and the output end of the second tri-state buffer is connected with the serial peripheral input interface of the storage chip.

[0020] In a case where the general input / output interface of the first processing chip transmits a first type of indication signal to the general input / output interface of the second processing chip, the first type of indication signal indicates that the serial peripheral output interface of the second processing chip outputs a blocking signal to indicate that the second tri-state buffer is in a blocking state.

[0021] In a case where the general input / output interface of the second processing chip transmits a second type of indication signal to the general input / output interface of the first processing chip, the second type of indication signal indicates that the serial peripheral output interface of the first processing chip outputs a blocking signal to indicate that the first tri-state buffer is in a blocking state.

[0022] In one of the embodiments, a first pull-up resistor is further included.

[0023] One end of the first pull-up resistor is connected with the output end of the first tri-state buffer and the output end of the second tri-state buffer, and the other end of the first pull-up resistor is connected with the power supply interface of the storage chip.

[0024] In one of the embodiments, a second pull-up resistor is further included.

[0025] One end of the second pull-up resistor is connected with the serial peripheral output interface of the storage chip, and the second pull-up resistor is connected with the power supply interface of the first processing chip or the second processing chip.

[0026] In one of the embodiments, further comprising:

[0027] A third tri-state buffer is connected between one end of the second pull-up resistor and the serial peripheral output interface of the storage chip.

[0028] In one of the embodiments, at the initial power-on time of the first processing chip, the general input / output interface of the first processing chip transmits a first type of indication signal; the first type of indication signal is used to indicate that the connection state between the serial peripheral output interface of the second processing chip and the serial peripheral input interface of the storage chip is in a blocking state.

[0029] The application provides a hearing aid device, characterized in that comprising a hearing aid chip, the hearing aid chip is packaged based on a first processing chip, a second processing chip and a storage chip.

[0030] The first processing chip is a digital signal processing chip die; or the second processing chip is a Bluetooth chip die; or the storage chip is a flash memory chip die.

[0031] The storage control circuit between the above-mentioned multiple chips is connected with the storage chip through the multiple processing chips, transmits the indication signals between the multiple processing chips through the general input and output interfaces, controls the access permission of the multiple processing chips to the storage chip, can ensure that the multiple processing chips reasonably and orderly share one storage chip, realizes that one storage chip provides data for the multiple processing chips, can only use one packaging substrate when packaging the chips, and can reduce the number of packaged chips on the packaging substrate due to the fact that the multiple processing chips share one storage chip, and reduces the packaging size while ensuring the same functions. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 It is a schematic diagram of the storage control circuit between the multiple chips in one embodiment;

[0033] Figure 2 It is a schematic diagram of the SPI interface in one embodiment;

[0034] Figure 3 It is a schematic diagram of the storage control circuit between the multiple chips in another embodiment;

[0035] Figure 4 It is a transmission timing diagram of the clock signal of the storage control circuit between the multiple chips in another embodiment;

[0036] Figure 5 It is a schematic diagram of the storage control circuit between the multiple chips in another embodiment;

[0037] Figure 6 It is a transmission timing diagram of the clock signal of the storage control circuit between the multiple chips in another embodiment. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical scheme and advantages of the application more clear, the application is further described in detail below in combination with the drawings and embodiments. In the following description, many specific details are set forth in order to provide a thorough understanding of the present application. However, the present application can be practiced in many different ways other than those described herein, and those skilled in the art can make similar improvements without departing from the scope of the present application, so the present application is not limited to the specific implementation disclosed below.

[0039] In addition, the terms "first", "second", etc. are used only for descriptive purposes and should not be construed as indicating or implying relative importance or an indicated number of technical features. Therefore, the features defined as "first" and "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified and limited.

[0040] In the present application, unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting", "fixing" and the like should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or it can be integrated; it can be mechanically connected, or it can be electrically connected, or it can be communicated; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication or interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0041] With the development of wireless technology, more and more off-chip communication devices support Bluetooth function, for example, adding Bluetooth function in hearing aid, the audio signal in patient intelligent device can be transmitted to hearing aid directly through Bluetooth transmission technology, and then the patient can hear the sound. Specifically, the digital signal processing chip and the Bluetooth chip in the hearing aid can be packaged in one chip in the form of system in a package (SIP) or stacked Die. In the existing Bluetooth hearing aid, the digital signal processing chip has a corresponding storage chip, and the Bluetooth chip also has a corresponding storage chip. However, due to the increasing application in hearing aid and the increasing complexity of algorithm, the program to be stored is becoming larger and larger, so larger off-chip storage is needed to place the data processing program of the digital signal processing chip and the data processing program of the Bluetooth chip. Therefore, after packaging the digital processing chip and its storage chip, the Bluetooth chip and its storage chip, the volume of the hearing aid will be large, which will affect the use of the patient.

[0042] Referring to Figure 1 The embodiment of the present application provides a storage control circuit between multiple chips, which can solve the above technical problems. The circuit comprises:

[0043] a storage chip 100;

[0044] a first processing chip 200 and a second processing chip 300, a general input and output interface 210 of the first processing chip is connected with a general input and output interface 310 of the second processing chip;

[0045] A first control unit 400 is connected between the serial peripheral output interface 220 of the first processing chip and the serial peripheral input interface 110 of the storage chip;

[0046] and a second control unit 500 is connected between the serial peripheral output interface 320 of the second processing chip and the serial peripheral input interface 110 of the storage chip;

[0047] The serial peripheral output interface 120 of the storage chip is connected with the serial peripheral input interfaces 230 and 330 of the first and second processing chips respectively;

[0048] The first and second processing chips 200 and 300 are both internal without Read-Only Memory (ROM), and cannot directly store application programs and data in the chips. The first and second processing chips 200 and 300 both have general input and output interfaces, such as I / O pins, and further include serial peripheral interfaces SPI, which specifically include clock pins CLK, chip select pins CS, data output pins DO and data input pins DI in the first and second processing chips 200 and 300, and can communicate with other chips to obtain data. In the present application, for the first processing chip 200, the serial peripheral output interface 220 includes the clock pins CLK, the chip select pins CS and the data output pins DO, and the serial peripheral input interface 230 includes the data input pins DI.

[0049] The storage chip 100 is a chip that can modify internal data through a specific program, and can communicate with other chips to store data in the chip, such as a FLASH chip. The FLASH chip is connected with the first and second processing chips 200 and 300 through the SPI interface in the FLASH chip, and provides application programs for the first and second processing chips 200 and 300. Specifically, the SPI interface in the FLASH chip includes the clock pins CLK, the chip select pins CS, the data output pins DO and the data input pins DI. In the present application, the serial peripheral input interface 110 of the storage chip includes the clock pins CLK, the chip select pins CS and the data input pins DI, and the serial peripheral output interface 120 of the storage chip includes the data output pins DO.

[0050] In one embodiment, the first control unit 400 controls the connection state between the serial peripheral output interface 220 of the first processing chip and the serial peripheral input interface 110 of the memory chip based on the indication signals transmitted between the general input / output interface 210 of the first processing chip and the general input / output interface 310 of the second processing chip; and the second control unit 500 controls the connection state between the serial peripheral output interface 320 of the second processing chip and the serial peripheral input interface 110 of the memory chip based on the indication signals transmitted between the general input / output interface 210 of the first processing chip and the general input / output interface 310 of the second processing chip.

[0051] Specifically, in one embodiment, the first processing chip 200 can be a digital signal processing (DSP) chip, which needs to load an application program into the DSP chip for execution by loading operation when the DSP is working, and the DSP chip includes an SPI interface. The memory chip 100 can be a FLASH chip. The connection relationship between the DSP chip and the FLASH chip is shown in Figure 2 The second processing chip 300 can be a Bluetooth chip, and the pin connection between the Bluetooth chip and the memory chip is consistent with that between the DSP chip and the memory chip.

[0052] The first processing chip 200 and the second processing chip 300 each have a general input / output interface, such as an I / O pin. For the first processing chip 200, the access permission of the chip to the memory chip is informed to the second processing chip through the I / O pin, and the access permission requirement of the second processing chip to the memory chip is obtained. That is, by connecting the I / O pin of the first processing chip with the I / O pin of the second processing chip, the indication signals are transmitted between the I / O pins to determine the access permission of the first processing chip and the second processing chip to the memory chip.

[0053] Specifically, for example, the first processing chip 200 is a DSP chip, and the second processing chip 300 is a Bluetooth chip. The GPIO port of the DSP chip is connected with the GPIO port of the Bluetooth chip. When the DSP chip obtains the access right of the SPI interface of the storage chip, the GPIO port of the DSP chip outputs 0. At this time, the GPIO port of the Bluetooth chip inputs 0, and the Bluetooth chip does not have the access right of the SPI interface of the storage chip, and the SPI interface of the Bluetooth chip does not run. It should be noted that the SPI interface of the Bluetooth chip does not run can be realized by an external forging method, so that the output of the SPI interface of the Bluetooth chip cannot be input into the SPI interface of the storage chip, or the output of the SPI interface of the Bluetooth chip can be set to a fixed value, so that it cannot affect the data transmission between the SPI interface of the DSP chip and the SPI interface of the storage chip. When the Bluetooth chip needs to obtain the access right of the SPI interface of the storage chip, the Bluetooth chip transmits a request signal to the GPIO port of the DSP chip through the GPIO port of the Bluetooth chip. After the DSP chip obtains the request of the Bluetooth chip, the DSP chip informs the Bluetooth chip through the GPIO port of the DSP chip without accessing the SPI interface of the storage chip, that is, the output of the GPIO port of the DSP chip can be set to 1 at this time, and the Bluetooth chip obtains the access right of the SPI interface of the storage chip.

[0054] It should be noted that the general input and output interfaces of the first processing chip 200 and the second processing chip 300 are used to determine the access right of the two chips to the storage chip, so as to avoid access conflict and the storage chip cannot simultaneously respond to the access requirements of the two chips. The access right of the serial peripheral input interface 110 of the storage chip can be determined by controlling and monitoring the state of the general input and output interface through the firmware of the first processing chip 200 and the second processing chip 300.

[0055] The first control unit 400 is used to determine whether the first processing chip 200 can access the serial peripheral input interface 110 of the storage chip according to the state of the general input and output interface 210 of the first processing chip and the general input and output interface 310 of the second processing chip. Similarly, the second control unit 500 is used to determine whether the second processing chip 300 can access the serial peripheral interface 110 of the storage chip according to the state of the general input and output interface 210 of the first processing chip and the general input and output interface 310 of the second processing chip.

[0056] The indication signals transmitted between the general input / output interface 210 of the first processing chip and the general input / output interface 310 of the second processing chip can directly act on the first control unit 400 / second control unit 500, so that the first processing chip 200 / second processing chip 300 cannot access the serial peripheral interface 110 of the storage chip, or the output of the serial peripheral output interface of the first processing chip can be controlled according to the indication signals, so that the output data cannot be transmitted to the serial peripheral interface 110 of the storage chip after passing through the first control unit.

[0057] In the circuit provided by the above embodiment, the plurality of processing chips are connected with the storage chip, the indication signals are transmitted between the general input / output interfaces of the plurality of processing chips, the access permission control of the plurality of processing chips on the storage chip is completed, the plurality of processing chips can reasonably and orderly share one storage chip, one storage chip can provide data for the plurality of processing chips, only one packaging substrate can be used when packaging the chips, the number of packaged chips on the packaging substrate can be reduced due to the fact that the plurality of processing chips share one storage chip, the packaging size can be reduced and the packaging cost can be reduced under the condition of providing the same functions.

[0058] In one of the embodiments, the first control unit includes a first type of tri-state buffer, and the second control unit includes a second type of tri-state buffer.

[0059] The input end of the first type of tri-state buffer is connected with the serial peripheral output interface of the first processing chip, the enable end of the first type of tri-state buffer is connected with the general input / output interface of the first processing chip, and the output end of the first type of tri-state buffer is connected with the serial peripheral input interface of the storage chip.

[0060] The input end of the second type of tri-state buffer is connected with the serial peripheral output interface of the second processing chip, the enable end of the second type of tri-state buffer is connected with the general input / output interface of the second processing chip, and the output end of the second type of tri-state buffer is connected with the serial peripheral input interface of the storage chip.

[0061] In the case where the first type of indication signal is transmitted from the general input / output interface of the first processing chip to the general input / output interface of the second processing chip, the first type of tri-state buffer is in a conduction state, and the second type of tri-state buffer is in a blocking state.

[0062] In the case where the second type of indication signal is transmitted from the general input / output interface of the first processing chip to the general input / output interface of the second processing chip, the first type of tri-state buffer is in a blocking state, and the second type of tri-state buffer is in a conduction state.

[0063] It can be understood that the first control unit 400 and the second control unit 500 in the circuit are used to control the on-off state of the circuit according to the indication signals transmitted between the general input-output interfaces of the first processing chip and the general input-output interfaces of the second processing chip, and thus can be implemented by using tri-state buffers. The tri-state output of the tri-state buffer is controlled by the enable end. When the enable end inputs a valid signal, the device realizes normal logic state output (logic 0, logic 1). When the enable input is invalid, the output is in a high-impedance state, that is, equivalent to being disconnected from the connected circuit. The tri-state buffer can be divided into the following four types according to the relationship between the input and output of the three ports: low-active original code output, high-active original code output, low-active inverse code output, and high-active inverse code output. In the embodiment, as long as the first processing chip and the second processing chip do not store in conflict when accessing the storage chip and the transmission logic is correct, the first type of tri-state buffer and the second type of tri-state buffer can be the same type or different types.

[0064] For example, in one embodiment, referring to Figure 3 Taking the first processing chip 200 as a DSP chip and the second processing chip 300 as a Bluetooth chip as an example, the first type of tri-state buffer is a low-active original code output tri-state buffer, and the second type of tri-state buffer is a high-active tri-state buffer. The storage chip 100 can be a FLASH chip. The enable end of the low-active original code output tri-state buffer and the enable end of the high-active tri-state buffer are both controlled by the general input-output pin of the DSP chip. When the DSP accesses the SPI interface of the FLASH chip, the general input-output pin of the DSP chip outputs a low level. At this time, the output end of the low-active original code output tri-state buffer is consistent with the input end, and the high-active tri-state buffer is in a high-impedance state, that is, the input of the SPI input pin of the FLASH chip is consistent with the output of the SPI output pin of the DSP chip. When the Bluetooth chip has access permission, the general input-output pin of the DSP chip outputs a high level. At this time, the output end of the high-active original code output tri-state buffer is consistent with the input end, and the low-active tri-state buffer is in a high-impedance state, that is, the input of the SPI input pin of the FLASH chip is consistent with the output of the SPI output pin of the Bluetooth chip. For details, see Figure 4 Taking the clock signal in the SPI interface as an example, Figure 4 The timing diagram provided can clearly and clearly illustrate the access of the first processing chip and the second processing chip to the storage chip.

[0065] In the circuit provided in the above embodiment, a tri-state buffer is directly connected to the general-purpose input / output interface of the first processing chip. Since the indication signal transmitted between the general-purpose input / output interface of the first processing chip and the general-purpose input / output interface of the second processing chip can indicate the access status of the first and second processing chips to the memory chip, the working state of the tri-state buffer can be directly controlled by the indication signal. When the enable is valid, the output terminal is allowed to output terminal, and when the enable is invalid, it is in a high-impedance state, which can quickly switch the access and data reading of the SPI interface of the first and second processing chips to the memory chip.

[0066] In one embodiment, the circuit further includes:

[0067] Two NOT gates are connected in series between the enable terminal of the first type of tri-state buffer and the general-purpose input / output interface of the first processing chip.

[0068] See Figure 3 It can be seen that the first type of tri-state buffer and the second type of tri-state buffer are different categories, and their operating states differ when corresponding to the same indicator signal. Figure 3 In the circuit, the enable terminals of the first type of tri-state buffer and the second type of tri-state buffer are both directly connected to the GPIO0 pin of the first processing chip. There is no isolation device between the first type of tri-state buffer and the second type of tri-state buffer, which poses a short circuit risk. Therefore, two NOT gates can be added between the enable terminal of the first type of tri-state buffer and the general input / output interface of the first processing chip. According to logic, the output of the two serial NOT gates is consistent with the input and output and will not affect the enable terminal of the first type of tri-state buffer.

[0069] By adding redundant NOT gates, multiple devices can be isolated from each other, avoiding mutual interference and thus better protecting the circuit.

[0070] In one embodiment, the first control unit includes a first type of tri-state buffer, and the second control unit includes a second type of tri-state buffer;

[0071] The input and enable terminals of the first type of tri-state buffer are both connected to the serial peripheral output interface of the first processing chip, and the output terminal of the first type of tri-state buffer is connected to the serial peripheral input interface of the memory chip.

[0072] The input and enable terminals of the second type of tri-state buffer are both connected to the serial peripheral output interface of the second processing chip, and the output terminal of the second type of tri-state buffer is connected to the serial peripheral input interface of the memory chip.

[0073] In a case where the general input / output interface of the first processing chip transmits a first type of indication signal to the general input / output interface of the second processing chip, the first type of indication signal instructs the serial peripheral output interface of the second processing chip to output a blocking signal, so as to indicate that the second type of tri-state buffer is in a blocking state.

[0074] In a case where the general input / output interface of the second processing chip transmits a second type of indication signal to the general input / output interface of the first processing chip, the second type of indication signal instructs the serial peripheral output interface of the first processing chip to output a blocking signal, so as to indicate that the first type of tri-state buffer is in a blocking state.

[0075] According to the above explanation, in a case where the enable terminals of the first type of tri-state buffer and the second type of tri-state buffer are directly connected to the general input / output interface of the first processing chip, the tri-state buffers are directly controlled by the indication signals output between the general input / output interface of the first processing chip and the general input / output interface of the second processing chip, so as to realize whether the first processing chip or the second processing chip can normally access the SPI interface of the storage chip. In the embodiment of the present application, the enable terminals of the first type of tri-state buffer and the second type of tri-state buffer are connected to the input terminals of the respective tri-state buffers, and the output of the respective SPI interfaces is controlled by the control units in the first processing chip and the second processing chip according to the judgment of the indication signals, so as to achieve the access control of the SPI interface of the storage chip.

[0076] For example, the first type of tri-state buffer and the second type of tri-state buffer are both low-active true code output types, so in a case where the indication signal indicates that the first processing chip accesses the storage chip, the second processing chip sets the outputs of the SPI interfaces of the second processing chip to high level according to the indication signal, at this time, the second type of tri-state buffer is in a high-resistance state and cannot transmit signals to the storage chip; similarly, in a case where the second processing chip accesses the storage chip, the first processing chip sets the outputs of the SPI interfaces of the first processing chip to high level based on the indication signal.

[0077] In the circuit provided by the above embodiment, the enable terminals of the tri-state buffers are directly connected to the input terminals, so as to reduce the complexity of the connection of the external pins of the chip and facilitate the circuit assembly and packaging between multiple chips. Moreover, the output of the pins of the chip is controlled by the internal logic judgment, so as to reduce the influence of the circuit damage on the chip.

[0078] In one of the embodiments, a first pull-up resistor is further included;

[0079] One end of the first pull-up resistor is connected to the output terminal of the first type of tri-state buffer and the output terminal of the second type of tri-state buffer, and the other end of the first pull-up resistor is connected to the power supply interface of the storage chip.

[0080] It should be noted that in the circuit provided in the above embodiment, there is a case that the serial peripheral output interfaces of the first processing chip and the second processing chip output at the same time, and the first type of tri-state buffer and the second type of tri-state buffer are in high impedance state, at this time, the serial peripheral input interface of the storage chip is in open circuit, that is, the SPI pin of the storage chip is in a suspended state, therefore, a pull-up resistor needs to be set to ensure that the input of the serial peripheral input interface of the storage chip is high.

[0081] In one of the embodiments, a second pull-up resistor is further included;

[0082] One end of the second pull-up resistor is connected with the serial peripheral output interface of the storage chip, and the second pull-up resistor is connected with the power supply interface of the first processing chip or the second processing chip.

[0083] Similarly, for the first processing chip and the second processing chip, when the serial peripheral input interface is in a suspended state, a pull-up resistor is needed to make it in a high level state.

[0084] In one of the embodiments, further comprising:

[0085] A third type of tri-state buffer is connected between one end of the second pull-up resistor and the serial peripheral output interface of the storage chip.

[0086] It should be noted that in actual application scenarios, the interface levels of the first processing chip, the second processing chip and the storage chip are inconsistent, at this time, a pull-up resistor must be used to ensure that each input interface can be in a high level state.

[0087] Specifically, referring to Figure 5 In a specific embodiment, the first processing chip 200 is a DSP chip, the second processing chip 300 is a Bluetooth chip, and the storage chip 100 is an 8M bits FLASH chip, and the interface level of the FLASH chip is inconsistent with the interface level of the DSP chip and the Bluetooth chip; the first type of tri-state buffer is a low active original code output tri-state buffer, and the second type of tri-state buffer is a low active tri-state buffer.

[0088] Since the interface level of the FLASH chip is inconsistent with the interface level of the DSP chip and the Bluetooth chip, at this time, the output of the SPI interface of the DSP chip and the Bluetooth chip needs to be adjusted to an open-drain output structure, and the output of the SPI interface of the DSP chip or the Bluetooth chip can be ensured to be received by the FLASH chip "as is" through a pull-up resistor.

[0089] It should be noted that in Figure 5In the circuit, taking the access permission of the SPI interface of the DSP chip with the FLASH chip as an example, the SPI interface output of the Bluetooth chip is all high level, at this time, the second type of tri-state buffer is all in high impedance state, and cannot access the SPI interface of the FLASH chip. The output structure of the SPI interface of the DSP chip is open drain output, at this time, if the output is low level, the enable end of the first type of tri-state buffer is valid, the output is the same as the input, that is, the input of the SPI interface of the FLASH chip is also low level; if the output is high level, the enable end of the first type of tri-state buffer is invalid and is in high impedance state, at this time, the level of the pin of the SPI interface of the FLASH chip is pulled to high level through the pull-up resistor.

[0090] It can be understood that according to the design of the open drain output structure and the working principle of the pull-up resistor, if the external component is not enabled, the pull-up resistor will "weakly" pull the input voltage signal to high level. When the external component is not connected, the external component "appears" to be high impedance to the input end. At this time, the voltage at the input port can be pulled to high level through the pull-up resistor. If the external component is enabled, it will cancel the high level set by the pull-up resistor. That is, in the embodiment, although the pull-up resistor is connected, the output of the SPI interface of the DSP chip is low level, which is a certain signal, at this time, the pull-up resistor will not affect the low level.

[0091] In addition, for the input of the SPI interface of the FLASH chip, the corresponding pull-up resistor needs to be connected to the power supply of the FLASH chip, so that it can meet the high level setting of the FLASH chip. For example, the pin of the FLASH chip needs to reach 3.3V to be identified as high level, if the pull-up resistor cannot meet this requirement, the pin of the FLASH chip cannot be determined to be high level.

[0092] For the circuit in Figure 5 , the storage control process between multiple chips is realized, which can be seen in detail from Figure 6 , taking the clock signal in the SPI interface as an example, Figure 6 , the timing diagram provided can clearly and clearly illustrate the access situation of the first processing chip and the second processing chip to the storage chip.

[0093] It should be noted that in Figure 4 and Figure 6 , in Stage2 and Stage4, at this time, the high and low levels of GPIO0 and GPIO1 are inconsistent, indicating that the access permission of the first processing chip is being adjusted, at this time, the SPI interface of the storage chip has no access, that is, the storage chip does not respond.

[0094] The circuit provided in the above embodiment can solve the inconsistency of the interface level of the multi-chip and the storage chip by changing the output structure of the chip pin and adding the pull-up resistor.

[0095] In one of the embodiments, the first processing chip and the second processing chip each include a plurality of general input / output interfaces; and a data path for mutual transmission of data is formed between the two through their respective general input / output interfaces.

[0096] It should be noted that the general input / output interface belongs to a full-duplex working mode, and thus one general input / output interface can be used when transmitting the indication signal between the first processing chip and the second processing chip, and a plurality of general input / output interfaces can also be used to ensure the correctness of the indication signal and the correct processing of the indication signal by the processing chip. However, the indication signals between the plurality of general input / output interfaces have a certain correlation, and the common action thereof is to determine the access right of the plurality of processing chips to the storage chip and avoid the multi-chip access conflict, and the correlation between the indication signals of the plurality of general input / output interfaces is not specifically limited in the embodiment and can be flexibly adjusted according to the actual application scenario.

[0097] In one of the embodiments, when the first processing chip is initially powered on, the general input / output interface of the first processing chip transmits a first type of indication signal; and the first type of indication signal is used to indicate that the connection state of the path between the serial peripheral output interface of the second processing chip and the serial peripheral input interface of the storage chip is a blocking state.

[0098] For the Bluetooth hearing aid, the first processing chip is a DSP chip, and the second processing chip is a Bluetooth chip, and the DSP chip is dominant between the two, and thus the DSP chip is set to have the initial access right after the system is powered on, that is, the general input / output interface of the first processing chip transmits the first type of indication signal after the initial power-on, for example, the general input / output interface of the first processing chip outputs 0, and for the Bluetooth chip, only when 1 is received, the access right is possessed.

[0099] In one of the embodiments, a hearing aid device is provided, which includes a hearing aid chip packaged based on a first processing chip, a second processing chip and a storage chip.

[0100] The first processing chip is a digital signal processing chip die; or the second processing chip is a Bluetooth chip die; or the storage chip is a flash memory chip die.

[0101] The chip die DIE is a small unit in a silicon wafer, including a complete single chip design and a partial scribe lane area in the horizontal and vertical directions adjacent to the chip. The DIE is cut from a wafer. In this embodiment, the digital signal processing chip die DSP SOC DIE, the Bluetooth chip die Blue Tooth SOC DIE, and the flash memory chip die FLASH DIE are bare chips before packaging. The three DIEs are packaged to obtain the hearing aid chip Hearing Aid Chip.

[0102] It should be noted that in the hearing aid chip, the connection circuit between the first processing chip, the second processing chip, and the storage chip includes the above-described storage control circuit between multiple chips, so that the first processing chip and the second processing chip share the storage chip.

Claims

1. A memory control circuit between multiple chips, characterized by, The application relates to a chip system, which comprises: a storage chip; a first processing chip and a second processing chip, a general input / output interface of the first processing chip being connected with a general input / output interface of the second processing chip; a low-effective tri-state buffer, an input end and an output end of the low-effective tri-state buffer being connected with a serial peripheral output interface of the first processing chip and a serial peripheral input interface of the storage chip respectively; a high-effective tri-state buffer, an input end and an output end of the high-effective tri-state buffer being connected with a serial peripheral output interface of the second processing chip and a serial peripheral input interface of the storage chip respectively; an enable end of the low-effective tri-state buffer and an enable end of the high-effective tri-state buffer being connected with a circuit between the general input / output interface of the first processing chip and the general input / output interface of the second processing chip; a serial peripheral output interface of the storage chip being connected with serial peripheral input interfaces of the first processing chip and the second processing chip respectively; in the case that the general input / output interface of the first processing chip transmits a low level to the general input / output interface of the second processing chip, the low-effective tri-state buffer is in a conducting state and the high-effective tri-state buffer is in a blocking state, so that the first processing chip sends an access to the storage chip and receives data output by the storage chip; in the case that the general input / output interface of the first processing chip transmits a high level to the general input / output interface of the second processing chip, the low-effective tri-state buffer is in a blocking state and the high-effective tri-state buffer is in a conducting state, so that the second processing chip sends an access to the storage chip and receives data output by the storage chip.

2. The circuit of claim 1, wherein, One of the first processing chip and the second processing chip comprises a digital signal processing chip and the other comprises a Bluetooth chip.

3. The circuit of claim 1, wherein, The storage chip comprises a flash memory chip.

4. The circuit of claim 1, wherein, The first processing chip and the second processing chip are both configured not to store a data processing program in the processing chip.

5. The circuit according to any one of claims 1 to 4, characterized in that The application further comprises: two NOT gates, which are connected in series between the enable end of the low-effective tri-state buffer and the general input / output interface of the first processing chip.

6. The circuit according to any one of claims 1 to 4, characterized in that The application further comprises a first pull-up resistor; one end of the first pull-up resistor is connected with the output end of the low-effective tri-state buffer and the output end of the high-effective tri-state buffer, and the other end of the first pull-up resistor is connected with a power supply interface of the storage chip.

7. The circuit according to any one of claims 1 to 4, characterized in that The application further comprises a second pull-up resistor; one end of the second pull-up resistor is connected with a serial peripheral output interface of the storage chip, and the second pull-up resistor is connected with a power supply interface of the first processing chip or the second processing chip.

8. The circuit of claim 7, wherein, The application further comprises: a third tri-state buffer, which is connected between one end of the second pull-up resistor and a serial peripheral output interface of the storage chip.

9. The circuit according to any one of claims 1 to 4, characterized in that At the initial power-on time of the first processing chip, a general input and output interface of the first processing chip transmits a low level; the low level is used to indicate that a connection state between a serial peripheral output interface of the second processing chip and a serial peripheral input interface of the storage chip is a blocking state.

10. A hearing assistance device, characterized by The hearing aid chip includes the multi-chip inter-storage control circuit package of any one of claims 1 to 9; and the multi-chip inter-storage control circuit includes the first processing chip, the second processing chip and the storage chip. The first processing chip is a digital signal processing chip die; or the second processing chip is a Bluetooth chip die; or the storage chip is a flash memory chip die.

Images