Source driver, display device and calibration method suitable for point-to-point transmission

Abstract

The application relates to a source driver, a display device and a calibration method suitable for point-to-point transmission. The source driver comprises an internal switch tube, a link state detector, a receiver and an identification recognition circuit. The drain of the internal switch tube is used for accessing an external system LS signal, the gate of the internal switch tube is connected with an internal LS signal end and the link state detector respectively, and the source of the internal switch tube is grounded. The receiver is connected with the link state detector and the identification recognition circuit respectively, and is used for connecting a transmitter of a timing controller. The link state detector is used for detecting a lock state or an unlock state of an internal link state signal end. The identification recognition circuit is used for identifying address information sent by the timing controller and storing the address information into the receiver, and feeding back the address information and the unlock state to the timing controller through back data when the link state detector detects the unlock state, so as to instruct the timing controller to re-lock and EQ calibrate the source driver. The calibration efficiency is higher.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a source driver, display device, and calibration method suitable for point-to-point transmission. Background Technology

[0002] With the increasing demand for larger screen sizes, higher display resolutions, and higher refresh rates, the in-panel interface connecting the timing controller (TCON) and source driver IC (SDIC) in TFT-LCD display panels must support data transfer rates of up to 6Gbps or higher. To meet the ultra-high-speed data rate requirements of in-panel interfaces, point-to-point (P2P) transmission protocols have emerged. Due to the skin effect and dielectric loss in high-resolution, high-refresh-rate display panels, high-speed data experiences high-frequency loss when passing through the channel. Therefore, the transmitter (TX) uses pre-emphasis technology to enhance the lost frequency bands, and the receiver (RX) uses equalizer technology (EQ) to compensate for the lost frequency bands in the received signal. For low-speed P2P transmission protocols, signal compensation at the receiver end can be omitted or reduced to a small EQ value. However, for high-speed P2P transmission protocols, compensating for high-frequency signal attenuation is crucial for accurately recovering the high-speed signal at the RX end.

[0003] Currently, the existing high-speed signal compensation technology is AEQ (Adaptive Equalizer) compensation, which is relatively mature. However, during implementation, the inventors discovered that when an SDIC experiences an Unlock signal due to sudden noise or other factors, the int.LS (link status) signal of that SDIC pulls System.LS low, causing all SDICs to re-train (calibrate). Simultaneously, the AEQ also re-calibrates, wasting too much time on calibration. Furthermore, the SDIC may be in calibration mode upon power-on, leading to display abnormalities and still exhibiting low calibration efficiency. Summary of the Invention

[0004] Therefore, it is necessary to address the aforementioned technical problem of low calibration efficiency by providing a source driver with higher calibration efficiency suitable for point-to-point transmission, a display device, and a source driver calibration method suitable for point-to-point transmission.

[0005] To achieve the above object, in one aspect, the embodiment of the present application provides a source driver suitable for point-to-point transmission, which comprises an internal switch tube, a link state detector, a receiver and an identification recognition circuit, the drain electrode of the internal switch tube is used for connecting an external system link state signal, the gate electrode of the internal switch tube is connected with an internal link state signal end and the link state detector respectively, the source electrode of the internal switch tube is grounded, the receiver is connected with the link state detector and the identification recognition circuit respectively, and the receiver is used for connecting a transmitter of a timing controller;

[0006] The link state detector is used for detecting a signal state of the internal link state signal end; the signal state comprises a lock state or a lock loss state;

[0007] The identification recognition circuit is used for identifying address information sent by the timing controller and storing the address information in the receiver, and feeding back the address information and the lock loss state to the timing controller through back data when the link state detector detects the lock loss state; the feedback address information and the lock loss state are used for instructing the timing controller to re-lock and calibrate an equalizer of the source driver.

[0008] In another aspect, the embodiment of the present application further provides a display device, which comprises a link state pull-up circuit, a timing controller and a plurality of source drivers suitable for point-to-point transmission, the link state pull-up circuit is connected with the timing controller and each source driver suitable for point-to-point transmission respectively;

[0009] The link state pull-up circuit is used for providing pull-up for a system link state signal, and the timing controller is used for calibrating, issuing address information and re-calibrating lock loss of each source driver suitable for point-to-point transmission respectively;

[0010] Each source driver suitable for point-to-point transmission comprises an internal switch tube, a link state detector, a receiver and an identification recognition circuit, the drain electrode of the internal switch tube is used for connecting an external system link state signal, the gate electrode of the internal switch tube is connected with an internal link state signal end and the link state detector respectively, the source electrode of the internal switch tube is grounded, the receiver is connected with the link state detector, the identification recognition circuit and the timing controller respectively;

[0011] The link state detector is used for detecting a signal state of the internal link state signal end; the signal state comprises a lock state or a lock loss state;

[0012] The identification recognition circuit is used for identifying address information sent by the timing controller and storing the address information in the receiver, and feeding back the address information and the lock loss state to the timing controller through back data when the link state detector detects the link state lock loss state; the feedback address information and the lock loss state are used for instructing the timing controller to re-lock and calibrate an equalizer of the source driver suitable for point-to-point transmission.

[0013] In another aspect, the application also provides a source driver calibration method for point-to-point transmission, applied to the display device, the method comprising the steps of:

[0014] After the power-on calibration, if the link state detector of any source driver detects an unlock event, the identification recognition circuit of the source driver feeds back the address information and the unlock state to the timing controller through the feedback data;

[0015] The timing controller recalibrates the source driver until the source driver is relocked;

[0016] After the source driver is relocked, the timing controller calibrates the equalizer of the source driver until the bit error rate fed back by the source driver is zero and the equalizer value of the source driver is set;

[0017] The link state detector of the source driver detects the signal state again, and the source driver switches to the data transmission mode after the source driver is locked.

[0018] One of the above technical solutions has the following advantages and beneficial effects:

[0019] The above source driver for point-to-point transmission, display device and calibration method add a link state detector for detecting the link state signal state of each source driver and an identification recognition circuit for managing the address information of each source driver in each source driver, detect the link state signal of each source driver through the link state detector, and store the link state signal state of each source driver in the corresponding register. The link state signal state of each source driver can be fed back to the TCON through the feedback data. Meanwhile, each source driver is assigned with a unique identification address, and the address information sent by the TCON is identified by the identification recognition circuit. The identification recognition circuit can also feed back the address information of the source driver to the TCON through the feedback data, so that the TCON can accurately know the state of each source driver.

[0020] Therefore, when the source driver Unlock event occurs, the TCON can accurately know which source driver has the Unlock event through the address information and the link state fed back by the feedback data, so as to reLOCK and equalizer calibration, without recalibrating all source drivers from the beginning, which greatly improves the calibration efficiency, saves the power-on calibration time, avoids the abnormal boot screen caused by the long calibration time, and affects the use experience due to the long power-on time.

[0021] Additional aspects and advantages of the application will be in part apparent and in part pointed out hereinafter. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 Power-on calibration flowchart for a conventional source driver IC;

[0023] Figure 2 Re-calibration flowchart for a conventional source driver IC when an Unlock event occurs after power-on;

[0024] Figure 3 Circuit structure of a source driver suitable for point-to-point transmission in one embodiment;

[0025] Figure 4 Circuit structure of an identification recognition circuit in one embodiment;

[0026] Figure 5 Circuit structure of an identification recognition circuit in another embodiment;

[0027] Figure 6 Circuit structure of a display device in one embodiment;

[0028] Figure 7 Flowchart of a source driver calibration method suitable for point-to-point transmission in one embodiment;

[0029] Figure 8 Flowchart of a source driver calibration method suitable for point-to-point transmission in one embodiment;

[0030] Figure 9 Flowchart of a source driver calibration method suitable for point-to-point transmission in one embodiment; DETAILED DESCRIPTION

[0031] For the purpose of promoting an understanding of the disclosure, the present application will now be described in greater detail with reference to the figures. The preferred embodiments of the present application are illustrated in the figures. However, the present application can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. The embodiments are described so that this disclosure will be thorough and complete.

[0032] It should be noted that when an element is referred to as being "connected" to another element, it can be directly connected to the other element, or intervening elements can be present. The terms "one side," "the other side," and the like are used herein merely to facilitate the description of the embodiments.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0034] As shown in FIG. 1, a schematic diagram of a conventional power-on calibration process of a source driver IC is shown, and the specific calibration process is as follows: Figure 1

[0035] 1) After power on, the CDR (Clock Data Recovery) RESET in the receiver RX is received, at this time, the internal LS signal (SD_n int.LS) of each SDIC is in a low state, and the external system LS signal (System.LS) is pulled low (i.e. System.LS = L) through the conduction of the internal MOS tube of the inverter;

[0036] 2) After the LOCK Detector of the TCON detects that the System.LS is pulled low, the CT (Clock Calibration) signal will be sent to calibrate each SDIC;

[0037] 3) After the LOCK of each SDIC, the System.LS is pulled high (i.e. System.LS = H), at this time, the AEQ mode is entered (i.e. AEQ Mode);

[0038] 4) After entering the AEQ mode, each SDIC is calibrated in turn (i.e. SD_n EQ CT), until the feedback bit error rate is zero (i.e. BER = 0), then the EQ value at this time is set (i.e. SD_n EQ SET), until the EQ setting of all (i.e. n = M, M is the total number of SDICs) SDICs is completed;

[0039] 5) Finally, the data transmission mode (i.e. Data Mode) is entered, and the TCON sends data.

[0040] 6) If the SDIC Unlock event (i.e. SD_n Unlock) occurs after power on, the re-calibration process shown in FIG. 2 is executed. Figure 2 It can be seen that when the SDIC Unlock event occurs, the re-calibration process needs to re-calibrate all SDICs from the beginning, so the re-calibration time required will be longer, and the power-on is still in the calibration state, which will also cause the abnormal display of the boot screen and affect the user experience.

[0041] ​​

[0042] In view of the defects of the prior art, the application adds an LS detector for detecting the LS signal state of each SDIC and an ID identification circuit for managing the ID address information of each SDIC in each SDIC. The LS detector detects the LS signal of each SDIC, and the LS signal state (high level-Lock / low level-UnLock) is stored in the corresponding register. The LS signal state of each SDIC can be fed back to the TCON through the feedback data FBD. Meanwhile, each SDIC is assigned with a dedicated ID address, and the ID identification circuit identifies the ID address information sent by the TCON. The ID identification circuit can also feed back the ID address information of the SDIC to the TCON through the FBD, so that the TCON can accurately know the state of each SDIC.

[0043] Therefore, when the SDICUnlock event occurs, the TCON can accurately know which SDIC is unlocked through the ID address information and the LS state fed back by the FBD, so as to re-LOCK and AEQ calibrate the SDIC, without starting calibration from the beginning. Therefore, the power-on calibration time is saved, and the abnormal boot screen or long power-on time caused by long calibration time is avoided, thereby improving the user experience.

[0044] The scheme of the application will be described in detail below with reference to the drawings:

[0045] In one embodiment, Figure 3 As shown, a source driver 100 suitable for point-to-point transmission is improved, which comprises an internal switch tube Q, a link state detector 101, a receiver RX and an identification recognition circuit 102. The drain of the internal switch tube Q is used to access an external system link state signal, the gate of the internal switch tube Q is connected to an internal link state signal end and the link state detector 101 respectively, and the source of the internal switch tube Q is grounded. The receiver RX is connected to the link state detector 101 and the identification recognition circuit 102 respectively, and is used to connect the transmitter TX of the timing controller TCON. The link state detector 101 is used to detect the signal state of the internal link state signal end; the signal state includes a lock state or an unlock state.

[0046] The identification recognition circuit 102 is used to identify the address information sent by the timing controller TCON and store it in the receiver RX, and feed back the address information and the unlock state to the timing controller TCON through the feedback data when the link state detector 101 detects the unlock state. The feedback address information and the unlock state are used to indicate the timing controller TCON to re-lock and equalizer calibrate the source driver 100.

[0047] It can be understood that the internal switch tube Q refers to a switch tube device, such as but not limited to a MOS tube or a JFET tube, which is used to connect to the internal link state signal end through an inverter to access the link state signal (SD_n int.LS) inside the source driver 100, and the drain thereof can be used to access the external system link state signal (i.e. System.LS). The link state detector 101 refers to a level detection circuit or device capable of identifying the level state (high or low) of the link state signal inside the source driver 100, and various existing level detectors or circuit modules can be used to realize its function.

[0048] The receiver RX, i.e. the existing RX circuit inside the source driver 100, can be connected to the transmitter TX circuit of the timing controller TCON to support the data transmission function. The identification recognition circuit 102 refers to a circuit having address information recognition and transmission function, which can be built by using the switching devices and logic devices in the art, for identifying the SD_n ID (identification) signal (carrying the exclusive ID address of the nth source driver 100) sent by the timing controller TCON through the FBD, and storing the recognized address information into the address management module of the receiver RX. The identification recognition circuit 102 can also feed back the address information of the source driver 100 to the timing controller TCON through the FBD.

[0049] Specifically, after power-on, the CDR RESET in the receiver RX, at this time the link state signal (SD_n int.LS) inside the SDIC is in a low level state, and the MOS tube inside the SDIC turns on the internal MOS tube to pull down the external system link state signal (System.LS) through the inverter. After the LOCK Detector of the TCON detects that the System.LS is pulled down, the TX circuit of the TCON will send the CT signal to calibrate the SDIC. After the LOCK of each SDIC, the System.LS is pulled up. The TX circuit of the TCON sends the SD_n ID to the receiver RX of each SDIC through the FBD to set the unique SD_n ID for each SDIC, at this time the AEQ mode is entered; after entering the AEQ mode, the TCON performs equalizer calibration on each SDIC in turn, until the bit error rate fed back by all SDICs is zero, then the EQ value of each SDIC at this time is set, until the EQ setting of all SDICs is completed; thereafter, the data transmission mode Data Mode is entered, in which the TCON can send data to each SDIC.

[0050] After power on, if an SDIC has an Unlock event, the link state signal (SD_nint.LS) of the SDIC will be pulled low, and the link state signals of other SDICs without the Unlock event remain unchanged. The link state detector 101 of the SDIC with the Unlock event detects that the state of the SD_nint.LS changes to the unlock state (e.g., the internal link state signal changes from high to low), at which time the identification recognition circuit 102 feeds back the link state signal state (the unlock state) and the address information of the SDIC to the timing controller TCON through the FBD, and the timing controller TCON can accurately know the SDIC with the Unlock event according to the feedback address information and the link state signal state, and then calibrate the SDIC until the Lock is completed (i.e., the SD_nUnlock changes back to the SD_nLock), and calibrate the equalizer of the SDIC until the feedback bit error rate is zero, and then set the EQ value of the SDIC. Finally, the link state detector 101 of each SDIC can also detect the Unlock event again to ensure that all SDICs are locked, i.e., the internal link state signals of all SDICs are high.

[0051] The above source driver 100 suitable for point-to-point transmission adds a link state detector 101 for detecting the LS signal state of each SDIC and an identification recognition circuit 102 for managing the address information of each SDIC in each SDIC, detects the link state signal of each SDIC through the link state detector 101, and stores the link state signal state in the corresponding register, which can feed back the link state signal state of each SDIC to the TCON through the feedback data FBD. Meanwhile, each SDIC is assigned with a dedicated ID address, and the identification recognition circuit 102 identifies the address information sent by the TCON, and the identification recognition circuit 102 can also feed back the address information of the SDIC to the TCON through the FBD, so that the TCON can accurately know the state of each SDIC.

[0052] Therefore, when the SDIC Unlock event occurs, the TCON can accurately know which SDIC has the Unlock through the address information and the LS state fed back by the FBD, and then re-LOCK and AEQ calibrate the SDIC, without starting calibration from the beginning for all SDICs, which greatly improves the calibration efficiency, saves the power-on calibration time, avoids the abnormal boot screen caused by the long calibration time, and affects the use experience due to the long power-on time.

[0053] In one embodiment, the link status detector 101 includes a voltage comparator or an analog-to-digital converter (ADC) sampler. Optionally, in this embodiment, a voltage comparator can be used to detect the status of the SDIC's internal link status signal. For example, a reference voltage can be compared with the internal link status signal voltage to identify the level of the internal link status signal. Alternatively, various types of ADC samplers can be used to detect the status of the SDIC's internal link status signal. For example, the ADC sampler can sample the level of the internal link status signal, and then a controller with appropriate settings can identify the level of the sampled internal link status signal. By using a voltage comparator or an ADC sampler as the desired link status detector 101, the identification of the desired internal link status signal status can be achieved efficiently and reliably.

[0054] In one embodiment, such as Figure 4 As shown, the identification circuit 102 includes a logic unit 1021, a voltage comparator 1022, a first MOSFET Q1, a second MOSFET Q2, a first resistor R1, and a second resistor R2. The drain of the first MOSFET Q1 is connected to a timing controller, the source of the first MOSFET Q1 is connected to the first input terminal of the voltage comparator 1022, and the gate of the first MOSFET Q1 is connected to the first output terminal of the logic unit 1021. The drain of the second MOSFET Q2 is connected to the timing controller, the source of the second MOSFET Q2 is connected to the receiver RX, the gate of the second MOSFET Q2 is connected to the second output terminal of the logic unit 1021, and the input terminal of the logic unit 1021 is connected to the receiver RX. The first resistor R1 and the second resistor R2 are connected in series. One end of the first resistor R1 is connected to the VDD power supply, and the other end of the second resistor R2 is grounded. The second input terminal of the voltage comparator 1022 is connected between the first resistor R1 and the second resistor R2. The output terminal of the voltage comparator 1022 is connected to the receiver RX.

[0055] It is understood that the following methods were used in this embodiment: Figure 4 The illustrated preferred identification circuit 102 allows for the use of the same or different resistors for the first resistor R1 and the second resistor R2, depending on the circuit conditions of different SDIC types and the input requirements of the voltage comparator 1022. The same or different MOSFETs Q1 and Q2 can be N-type or P-type, depending on the actual signal transmission requirements. The logic controller 1021 can be any type of logic controller available in the art, selected based on the control requirements of the MOSFETs and circuit size limitations, as long as it meets the circuit size limitations of the SDIC and the required MOSFET on / off control functions. The voltage comparator 1022 can be any voltage comparator device available in the art, selected based on actual needs (functionality and specifications).

[0056] Specifically, when the TCON sends the SD_n ID to each SDIC through the FBD, the logic 1021 closes the first MOS Q1 and opens the second MOS Q2, at this time the FBD sends the SD_n ID of the SDIC to the voltage comparator 1022 for comparison, and the address management module of the receiver RX outputs the high or low level corresponding to the ID address carried in the signal in turn, and the address management module writes the ID address information of the SD_n ID into the SDIC. The voltage comparator 1022 can accurately identify the ID address to prevent possible errors (signal attenuation may occur during high-speed signal transmission), and can also buffer and provide more time margin to ensure reliable writing of the ID address information.

[0057] By using the above-mentioned identification recognition circuit 102, the ID address recognition and management of the SDIC can be efficiently, accurately and reliably realized.

[0058] In one embodiment, as shown in Figure 5 , the identification recognition circuit 102 includes a logic 1021, a first MOS Q1, a second MOS Q2, a third MOS Q3 and a first resistor R1. The drain of the first MOS Q1 is connected to the timing controller, the source of the first MOS Q1 is connected to the gate of the third MOS Q3, and the gate of the first MOS Q1 is connected to the first output of the logic 1021. The drain of the second MOS Q2 is connected to the timing controller, the source of the second MOS Q2 is connected to the receiver RX, and the gate of the second MOS Q2 is connected to the second output of the logic 1021. The input of the logic 1021 is connected to the receiver RX. One end of the first resistor R1 is connected to the VDD power supply, the other end of the first resistor R1 is connected to the drain of the third MOS Q3, the source of the third MOS Q3 is connected to the receiver RX and grounded.

[0059] It can be understood that in the present embodiment, another preferred identification recognition circuit 102 as shown in Figure 5 is used, wherein the first resistor R1 can be selected according to the circuit conditions of different types of SDICs and the input requirements of the voltage comparator 1022. The first MOS Q1, the second MOS Q2 and the third MOS Q3 can be the same or different MOS tubes, which can be N-type or P-type tubes, and can be selected according to actual signal transmission requirements. The logic 1021 can use various types of logic controllers in the art, and can be selected according to the control requirements of the MOS tubes and the circuit volume restrictions, as long as it can meet the circuit volume restrictions of the SDIC and the required MOS tube on-off control function.

[0060] Specifically, when the TCON sends the SD_n ID to each SDIC through the FBD, the logic 1021 closes the first MOS Q1 and opens the second MOS Q2, at this time the SD_n ID sent to the SDIC through the FBD reaches the third MOS Q3, when the level of the address signal SD_n ID is high, the third MOS Q3 is closed to output the VDD high level to the address management module of the receiver RX, and the address management module writes the ID address information of the SD_n ID into the SDIC. The voltage comparator 1022 plays a role in accurately identifying the ID address to prevent the possibility of false identification (in the process of high-speed signal transmission, the signal will be attenuated), and on the other hand, it plays a role in buffering and providing more time margin to ensure reliable writing of the ID address information.

[0061] By using the above-mentioned identification recognition circuit 102, the ID address recognition and management of the SDIC can be efficiently, accurately and reliably realized, and the circuit structure is more simple and the cost is lower.

[0062] In one embodiment, as shown in Figure 6 a display device 200 is also provided, comprising a link state pull-up circuit 201, a timing controller 202 and a plurality of source drivers 100 suitable for point-to-point transmission. The link state pull-up circuit 201 is connected to the timing controller 202 and each source driver 100 suitable for point-to-point transmission, respectively. The link state pull-up circuit 201 is used to provide pull-up for the system link state signal. The timing controller 202 is used to calibrate, issue address information and re-calibrate for lock loss of each source driver 100 suitable for point-to-point transmission, respectively. Each source driver 100 suitable for point-to-point transmission comprises an internal switch tube Q, a link state detector 101, a receiver RX and an identification recognition circuit 102. The drain of the internal switch tube Q is used to access an external system link state signal. The gate of the internal switch tube Q is connected to an internal link state signal end and the link state detector 101, respectively. The source of the internal switch tube Q is grounded. The receiver RX is connected to the link state detector 101, the identification recognition circuit 102 and the timing controller 202, respectively. The link state detector 101 is used to detect the signal state of the internal link state signal end; the signal state includes a locked state or a lock loss state.

[0063] The identification recognition circuit 102 is used to identify the address information sent by the timing controller 202 and store it in the receiver RX, and when the link state detector 101 detects a lock loss state, it feeds back the address information and the lock loss state to the timing controller 202 through the back data. The feedback address information and lock loss state are used to indicate the timing controller 202 to re-lock and equalizer calibrate the source driver 100 suitable for point-to-point transmission of lock loss.

[0064] It can be understood that the display device 200 can include other necessary structural components in addition to the aforementioned link state pull-up circuit 201, the timing controller 202, and the plurality of source drivers 100 suitable for point-to-point transmission, such as but not limited to display modules and TFTs, and the specific structure is determined according to the specific model of the display device 200 in actual application, which will not be described in detail in this specification. In the circuit framework structure as shown in Figure 6 In the circuit framework structure as shown in the figure, the link state pull-up circuit 201 for providing pull-up for the System.LS signal is included, which includes a pull-up resistor R connected to the VDD power supply and can be built on the PCB substrate. The timing controller 202, i.e. TCON, mainly includes a Lock Detector, an FBD module, and a transmitter TX in its internal circuit structure.

[0065] For specific explanation and description of the source driver 100 in this embodiment, reference can be made to the corresponding explanation and description in the above-mentioned embodiments of the source driver 100 suitable for point-to-point transmission, and the same understanding is applied here, which will not be described in detail.

[0066] Specifically, after power-on, the CDR RESET in the receiver RX of the source driver 100, at this time the link state signal (SD_n int.LS) in each SDIC is in a low state, and the MOS tube inside each SDIC is turned on by the inverter to pull down the external system link state signal (System.LS). After the LOCK Detector of the TCON detects that the System.LS is pulled down, the TX circuit of the TCON will send the CT signal to calibrate each SDIC. After each SDIC is locked, the link state pull-up circuit 201 pulls up the System.LS. The TX circuit of the TCON sends the SD_n ID to the receiver RX of each SDIC through the FBD to set a unique SD_n ID for each SDIC, at this time the AEQ mode is entered; after entering the AEQ mode, the TCON performs equalizer calibration on each SDIC in turn until the bit error rate fed back by all SDICs is zero, then the EQ value of each SDIC at this time is set, until all SDICs are EQ set; thereafter, the data transmission mode Data Mode is entered, in which the TCON can send data to each SDIC.

[0067] After power on, if an SDIC has an Unlock event, the link state signal (SD_nint.LS) of the SDIC will be pulled low, and the link state signals of other SDICs without an Unlock event remain unchanged. The link state detector 101 of the SDIC with an Unlock event detects that the state of the SD_nint.LS changes to a loss of lock state (e.g., the internal link state signal changes from high to low), at which time the identification recognition circuit 102 feeds back the link state signal state (loss of lock state) and address information of the SDIC to the timing controller TCON through the FBD, and the timing controller TCON can accurately know the SDIC with an Unlock event according to the feedback address information and link state signal state, and then calibrate the SDIC until the Lock is completed (i.e., the SD_nUnlock changes back to the SD_nLock), and calibrate the equalizer of the SDIC until the feedback bit error rate is zero, and then set the EQ value of the SDIC. Finally, the link state detector 101 of each SDIC can also detect the Unlock event again to ensure that all SDICs are locked, i.e., the internal link state signals of all SDICs are high.

[0068] The display device 200 described above applies the source driver 100 suitable for point-to-point transmission, adds a link state detector 101 for detecting the LS signal state of each SDIC and an identification recognition circuit 102 for managing the address information of each SDIC in each SDIC, detects the link state signal of each SDIC through the link state detector 101, and stores the link state signal state in the corresponding register, and can feed back the link state signal state of each SDIC to the TCON through the feedback data FBD. Meanwhile, each SDIC is assigned with a dedicated ID address, and the identification recognition circuit 102 recognizes the address information sent by the TCON, and can feed back the address information of the SDIC to the TCON through the FBD, so that the TCON can accurately know the state of each SDIC.

[0069] Therefore, when the SDIC Unlock event occurs, the TCON can accurately know which SDIC has an Unlock through the address information and LS state fed back by the FBD, and then reLOCK and AEQ calibrate the SDIC, without starting calibration from the beginning for all SDICs, which greatly improves the calibration efficiency, thereby saving the power-on calibration time of the display device 200, avoiding the abnormal display device 200 startup screen due to too long calibration time, and affecting the user experience due to long power-on time.

[0070] In one embodiment, the link state detector 101 comprises a voltage comparator or an analog-to-digital conversion sampler. By employing a voltage comparator or an analog-to-digital conversion sampler as the required link state detector 101, the identification of the required internal link state signal state can be efficiently and reliably achieved.

[0071] In one embodiment, the identification recognition circuit 102 comprises a logic device 1021, a voltage comparator 1022, a first MOS tube Q1, a second MOS tube Q2, a first resistor R1 and a second resistor R2. The drain of the first MOS tube Q1 is connected to the timing controller 202, the source of the first MOS tube Q1 is connected to the first input of the voltage comparator 1022, and the gate of the first MOS tube Q1 is connected to the first output of the logic device 1021. The drain of the second MOS tube Q2 is connected to the timing controller 202, the source of the second MOS tube Q2 is connected to the receiver RX, and the gate of the second MOS tube Q2 is connected to the second output of the logic device 1021. The input of the logic device 1021 is connected to the receiver RX. The first resistor R1 and the second resistor R2 are connected in series, one end of the first resistor R1 is connected to the VDD power supply, the other end of the second resistor R2 is grounded, and the second input of the voltage comparator 1022 is connected between the first resistor R1 and the second resistor R2. The output of the voltage comparator 1022 is connected to the receiver RX.

[0072] By employing the above-mentioned identification recognition circuit 102, the identification and management of the ID address of the SDIC can be efficiently, accurately and reliably achieved.

[0073] In one embodiment, the identification recognition circuit 102 comprises a logic device 1021, a first MOS tube Q1, a second MOS tube Q2, a third MOS tube Q3 and a first resistor R1. The drain of the first MOS tube Q1 is connected to the timing controller 202, the source of the first MOS tube Q1 is connected to the gate of the third MOS tube Q3, and the gate of the first MOS tube Q1 is connected to the first output of the logic device 1021. The drain of the second MOS tube Q2 is connected to the timing controller 202, the source of the second MOS tube Q2 is connected to the receiver RX, and the gate of the second MOS tube Q2 is connected to the second output of the logic device 1021. The input of the logic device 1021 is connected to the receiver RX. One end of the first resistor R1 is connected to the VDD power supply, the other end of the first resistor R1 is connected to the drain of the third MOS tube Q3, the source of the third MOS tube Q3 is connected to the receiver RX and grounded.

[0074] By employing the above-mentioned identification recognition circuit 102, the identification and management of the ID address of the SDIC can also be efficiently, accurately and reliably achieved, and the circuit structure is more simple and the cost is lower.

[0075] The specific description and limitation of the display device 200 can be understood by referring to the corresponding description and limitation of the above-mentioned source driver 100 applying point-to-point transmission. The display device 200 can be an ultra-high-definition high-refresh TV product, but is not limited to products such as 8K120 and 8K240. The above-mentioned circuit of the display device 200 can be integrated in an FPGA or a CB end.

[0076] In one embodiment, as shown in Figure 7 A source driver calibration method applying point-to-point transmission is also provided, which can be applied to the above-mentioned display device. The method can include the following calibration steps S12 to S18:

[0077] S12, after power-on calibration, if the link state detector of any source driver detects a loss of lock event, the identification recognition circuit of the source driver feeds back address information and the loss of lock state to the timing controller through the backhaul data;

[0078] S14, the timing controller re-calibrates the source driver until the source driver is re-locked;

[0079] S16, after the source driver is re-locked, the timing controller calibrates the equalizer of the source driver until the bit error rate fed back by the source driver is zero and the equalizer value of the source driver is set;

[0080] S18, the link state detector of the source driver detects the signal state again, and confirms that the source driver switches to the data transmission mode after the source driver is locked.

[0081] It can be understood that the specific description and limitation of the above-mentioned display device of the present embodiment can be understood by referring to the corresponding description and limitation of the above-mentioned display device 200 and the above-mentioned source driver 100 applying point-to-point transmission. Here, no further elaboration is given.

[0082] Specifically, as shown in Figure 8 After power-on calibration, if the link state detector of any source driver IC detects a loss of lock event, i.e. SD_nUnlock, the identification recognition circuit of the source driver IC feeds back address information and the loss of lock state to the timing controller through the backhaul data, i.e. FBD_Link(SD_n int.LS=L, the internal link state signal state is set to low; SD_n ID, feeds back the address information of the source driver IC).

[0083] The timing controller re-calibrates the source driver IC until the source driver IC is re-locked, i.e. TCONTraining SD_n (calibrates the clock of this SD to ensure Lock), SD_n Lock (this SD IC has been locked).

[0084] After the source driver IC is re-locked, the timing controller performs equalizer calibration on the source driver IC until the bit error rate fed back by the source driver IC is zero and sets the EQ value of the source driver IC, i.e. SD_n EQ CT, compensates for the lost frequency band in the received signal by using equalizer technology (EQ); determines whether BER = 0, i.e. whether the bit error rate fed back by the source driver IC is zero, if not, returns to SD_n EQ CT, and if yes, enters SD_n EQ SET, i.e. sets the corresponding EQ value after equalizer calibration.

[0085] The link state detector of the source driver IC detects the link state signal again to confirm that the source driver IC switches to the data transmission mode after the source driver IC is locked, i.e. detects again whether System.LS = H, i.e. whether the System.LS signal has been pulled high again, if not, returns to FBD_Link, and if yes, enters Data Mode, i.e. switches to the data transmission mode.

[0086] The above source driver calibration method applicable to point-to-point transmission can accurately know which SDIC has Unlock by the address information and the link state fed back by the FBD when the SDICUnlock event occurs, so as to re-LOCK and equalizer calibration, without starting calibration on all SDICs from the beginning, which greatly improves the calibration efficiency, thus saving the power-on calibration time of the display device 200 and avoiding the abnormal display device 200 startup screen or the long power-on time which affects the user experience.

[0087] In one embodiment, as shown in Figure 9 The above source driver calibration method applicable to point-to-point transmission can further include the following calibration steps:

[0088] After power-on, the timing controller detects that the level of the system link state signal is pulled down and sends a clock calibration signal to each source driver;

[0089] After each source driver completes clock calibration and is locked, the link state pull-up circuit pulls up the level of the system link state signal;

[0090] After the timing controller sends the corresponding address information to each source driver by returning the data, it enters the adaptive equalizer mode;

[0091] After entering the adaptive equalizer mode, the timing controller performs equalizer calibration on each source driver in turn;

[0092] When the bit error rate fed back by all source drivers is zero, set the equalizer value of each source driver;

[0093] After the equalizer value of each source driver is set, the timing controller switches to a data transmission mode.

[0094] It can be understood that, as shown in Figure 9 After power on, the CDR RESET in the receiver RX of the source driver 100, at this time, the link state signal (SD_n int.LS) in each SDIC is in low level state, and the MOS tube in each SDIC is turned on through the inverter to pull down the external system link state signal (System.LS=L). After the TCON LOCK Detector detects that the System.LS is pulled down, the TX circuit of the TCON will send a clock calibration signal (CT signal) to calibrate each SDIC, so that each SDIC is locked (CDR_n Lock, n=1, 2, 3…), and then the link state pull-up circuit pulls up the System.LS (System.LS=H). The TX circuit of the TCON sends the SD_n ID to the receiver RX of each SDIC through the FBD, sets the unique SD_n ID (SD_n ID Set) for each SDIC, and enters the AEQ mode (Data Mode) at this time.

[0095] After entering the AEQ mode, the TCON calibrates each SDIC in turn (SD_n EQ CT, starting from n=1) until the bit error rate fed back by all SDICs is zero (BER=0), and then sets the EQ value of each SDIC at this time (SD_n EQ SET), until the EQ of all SDICs (n=M) is set; thereafter, the data transmission mode Data Mode is entered, and the TCON can send data to each SDIC in this mode.

[0096] Through the above calibration process, the LOCK and AEQ calibration of all SDICs after initial power on can be quickly completed.

[0097] The technical features of the above embodiments can be combined in any manner. To make the description concise, not all possible combinations of the technical features in the above embodiments are described, but as long as the combinations of the technical features do not exist, they should be considered as the scope of the present application.

[0098] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the patent scope of the application. It should be noted that for those skilled in the art, without departing from the concept of the present application, some modifications and improvements can be made, which are all within the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

Claims

1. A source driver suitable for point-to-point transmission, characterized by, The internal switch tube is connected with an external system link state signal, the gate of the internal switch tube is connected with an internal link state signal terminal and the link state detector respectively, the source of the internal switch tube is grounded, the receiver is connected with the link state detector and the identification recognition circuit respectively, and the receiver is used for connecting a transmitter of a timing controller; The link state detector is used for detecting a signal state of the internal link state signal terminal; the signal state includes a lock state or a lock loss state; The identification recognition circuit is used for identifying address information sent by the timing controller and storing the address information in the receiver, and feeding back the address information and the lock loss state to the timing controller through backhaul data when the link state detector detects the lock loss state; the feedback address information and the lock loss state are used for instructing the timing controller to re-lock a source driver and calibrate an equalizer; The identification recognition circuit includes a logic device, a voltage comparator, a first MOS tube, a second MOS tube, a first resistor and a second resistor; The drain of the first MOS tube is connected with the timing controller, the source of the first MOS tube is connected with a first input terminal of the voltage comparator, and the gate of the first MOS tube is connected with a first output terminal of the logic device; The drain of the second MOS tube is connected with the timing controller, the source of the second MOS tube is connected with the receiver, the gate of the second MOS tube is connected with a second output terminal of the logic device, and an input terminal of the logic device is connected with the receiver; The first resistor and the second resistor are connected in series, one end of the first resistor is connected with a VDD power supply, the other end of the second resistor is grounded, a second input terminal of the voltage comparator is connected between the first resistor and the second resistor, and an output terminal of the voltage comparator is connected with the receiver.

2. A source driver suitable for point-to-point transmission according to claim 1, characterized in that, The link state detector includes a voltage comparator or an analog-to-digital conversion sampler.

3. A source driver suitable for point-to-point transmission, characterized in that, The internal switch tube is connected with an external system link state signal, the gate of the internal switch tube is connected with an internal link state signal terminal and the link state detector respectively, the source of the internal switch tube is grounded, the receiver is connected with the link state detector and the identification recognition circuit respectively, and the receiver is used for connecting a transmitter of a timing controller; The link state detector is used for detecting a signal state of the internal link state signal terminal; the signal state includes a lock state or a lock loss state; The identification recognition circuit is used for identifying address information sent by the timing controller and storing the address information in the receiver, and feeding back the address information and the lock loss state to the timing controller through backhaul data when the link state detector detects the lock loss state; the feedback address information and the lock loss state are used for instructing the timing controller to re-lock a source driver and calibrate an equalizer; The identification recognition circuit comprises a logic device, a first MOS transistor, a second MOS transistor, a third MOS transistor and a first resistor. The drain of the first MOS transistor is connected to the timing controller, the source of the first MOS transistor is connected to the gate of the third MOS transistor, and the gate of the first MOS transistor is connected to the first output end of the logic device. The drain of the second MOS transistor is connected to the timing controller, the source of the second MOS transistor is connected to the receiver, and the gate of the second MOS transistor is connected to the second output end of the logic device, and the input end of the logic device is connected to the receiver. One end of the first resistor is connected to a VDD power supply, the other end of the first resistor is connected to the drain of the third MOS transistor, the source of the third MOS transistor is connected to the receiver and grounded.

4. A source driver suitable for point-to-point transmission according to claim 3, characterized in that, The link state detector comprises a voltage comparator or an analog-to-digital conversion sampler.

5. A display device, characterized by The link state pull-up circuit, the timing controller and a plurality of source drivers suitable for point-to-point transmission are provided. The link state pull-up circuit is used to provide pull-up for a system link state signal, and the timing controller is used to calibrate each of the source drivers suitable for point-to-point transmission, issue address information and re-calibrate in case of lock loss. Each of the source drivers suitable for point-to-point transmission comprises an internal switch tube, a link state detector, a receiver and an identification recognition circuit. The link state detector is used to detect the signal state of the internal link state signal end. The identification recognition circuit is used to identify the address information sent by the timing controller and store the address information in the receiver, and feedback the address information and the lock loss state to the timing controller through backhaul data when the link state detector detects the lock loss state. The feedback address information and lock loss state are used to instruct the timing controller to re-lock and equalizer calibrate the source drivers suitable for point-to-point transmission in case of lock loss. The identification recognition circuit comprises a logic device, a voltage comparator, a first MOS transistor, a second MOS transistor, a first resistor and a second resistor. The drain of the first MOS transistor is connected to the timing controller, the source of the first MOS transistor is connected to the first input end of the voltage comparator, and the gate of the first MOS transistor is connected to the first output end of the logic device. The drain of the second MOS transistor is connected to the timing controller, the source of the second MOS transistor is connected to the receiver, and the gate of the second MOS transistor is connected to the second output end of the logic device, and the input end of the logic device is connected to the receiver. The first resistor and the second resistor are connected in series, one end of the first resistor is connected to a VDD power supply, the other end of the second resistor is grounded, the second input end of the voltage comparator is connected between the first resistor and the second resistor, and the output end of the voltage comparator is connected to the receiver.

6. The display device of claim 5, wherein, The link state detector comprises a voltage comparator or an analog-to-digital conversion sampler.

7. A display device, characterized by The link state pull-up circuit, the timing controller and a plurality of source drivers suitable for point-to-point transmission are included, and the link state pull-up circuit is connected to the timing controller and each of the source drivers suitable for point-to-point transmission respectively. The link state pull-up circuit is used to provide pull-up for a system link state signal, and the timing controller is used to calibrate, distribute address information and re-calibrate each of the source drivers suitable for point-to-point transmission respectively. Each of the source drivers suitable for point-to-point transmission comprises an internal switch tube, a link state detector, a receiver and an identification recognition circuit, the drain of the internal switch tube is used to access an external system link state signal, the gate of the internal switch tube is connected to an internal link state signal end and the link state detector respectively, the source of the internal switch tube is grounded, and the receiver is connected to the link state detector, the identification recognition circuit and the timing controller respectively. The link state detector is used to detect a signal state of the internal link state signal end, and the signal state comprises a locked state or an unlocked state. The identification recognition circuit is used to identify the address information sent by the timing controller and store the address information in the receiver, and feedback the address information and the unlocked state to the timing controller through backhaul data when the link state detector detects the unlocked state. The feedback address information and the unlocked state are used to instruct the timing controller to re-lock and equalizer-calibrate the source driver suitable for point-to-point transmission which is unlocked. The identification recognition circuit comprises a logic device, a first MOS tube, a second MOS tube, a third MOS tube and a first resistor. The drain of the first MOS tube is used to connect to the timing controller, the source of the first MOS tube is connected to the gate of the third MOS tube, and the gate of the first MOS tube is connected to the first output end of the logic device. The drain of the second MOS tube is used to connect to the timing controller, the source of the second MOS tube is connected to the receiver, the gate of the second MOS tube is connected to the second output end of the logic device, and the input end of the logic device is connected to the receiver. One end of the first resistor is connected to a VDD power supply, the other end of the first resistor is connected to the drain of the third MOS tube, and the source of the third MOS tube is connected to the receiver and grounded.

8. The display device of claim 7, wherein, The link state detector comprises a voltage comparator or an analog-to-digital conversion sampler.

9. A source driver calibration method for point-to-point transmission, applied to the display device of any one of claims 5 to 8, characterized in that, The method comprises the following steps: After power-on calibration, if the link state detector of any source driver detects an unlocked event, the identification recognition circuit of the source driver feeds back address information and an unlocked state to the timing controller through backhaul data. The timing controller recalibrates the source driver until the source driver is relocked; After the source driver is relocked, the timing controller performs equalizer calibration on the source driver until the error rate fed back by the source driver is zero and sets the equalizer value of the source driver; The link state detector of the source driver detects the signal state again to confirm that the source driver switches to data transmission mode after the source driver is locked.

10. The point-of-use source driver calibration method for point-to-point transmission according to claim 9, wherein, The method further comprises the steps of: After power-on, the timing controller detects that the level of the system link state signal is pulled down and sends a clock calibration signal to each source driver; After each source driver completes clock calibration and is locked, the link state pull-up circuit pulls up the level of the system link state signal; The timing controller enters the adaptive equalizer mode by sending corresponding address information to each source driver through backhaul data; After entering the adaptive equalizer mode, the timing controller performs equalizer calibration on each source driver in turn; When the error rate fed back by all the source drivers is zero, the equalizer value of each source driver is set; After the equalizer value of each source driver is set, the timing controller switches to the data transmission mode.

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