Multilayer Ceramic Capacitors

Abstract

The present invention provides a laminated ceramic capacitor capable of suppressing degradation of insulation resistance. The laminated ceramic capacitor (1) comprises: a laminate (10) having a plurality of laminated dielectric layers (20) and a plurality of internal electrode layers (30) laminated on the dielectric layers (20); and an external electrode (40) connected to the internal electrode layer (30), the laminate (10) having an inner layer portion (11), a first main surface side outer layer portion (12) and a second main surface side outer layer portion (13), and at least one of the first main surface side outer layer portion (12) and the second main surface side outer layer portion (13) is provided with a discharge path (P) formed along a plane orthogonal to the stacking direction and capable of discharging elements to the outside of the laminate (10).

Description

Technical Field

[0001] The present invention relates to a laminated ceramic capacitor. Background Art

[0002] A laminated ceramic capacitor comprises: a laminated body in which a plurality of dielectric layers and a plurality of internal electrodes are alternately laminated; and a pair of external electrodes formed on the surface of the laminated body so as to be electrically connected to the internal electrodes led out to the surface of the laminated body. Patent document 1 shows the following problem, namely, in such a laminated ceramic capacitor, when hydrogen is absorbed by the internal electrode, the hydrogen gradually reduces the surrounding dielectric layer, thereby deteriorating the insulation resistance. In addition, as a solution, the following scheme is shown, namely, when using an internal electrode mainly composed of a precious metal such as an Ag-Pd alloy, Ni is added to the internal electrode, and Ni is a metal that suppresses the absorption of hydrogen.

[0003] Prior Art Literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 1-80011

[0006] In recent years, in order to reduce material costs, base metals such as Ni are often used as materials for internal electrodes instead of precious metals such as Ag and Pd. Here, in Patent Document 1, Ni is described as a "metal that makes hydrogen absorption inert". However, according to the research of the inventors, it is known that even when Ni is used for the internal electrode, the insulation resistance will still deteriorate due to the influence of hydrogen. Therefore, in order to avoid the problem of insulation resistance degradation caused by the inclusion of hydrogen in the laminated ceramic capacitor, it is best to reduce the absolute amount of hydrogen contained in the laminated ceramic capacitor. Summary of the invention

[0007] Problem that the invention aims to solve

[0008] An object of the present invention is to provide a multilayer ceramic capacitor capable of suppressing degradation of insulation resistance.

[0009] Technical solutions to solve problems

[0010] The multilayer ceramic capacitor according to the present invention has:

[0011] A laminate having a plurality of laminated dielectric layers and a plurality of internal electrode layers laminated on the dielectric layers, and having a first main surface and a second main surface opposite to each other in a lamination direction, a first end surface and a second end surface opposite to each other in a length direction orthogonal to the lamination direction, and a first side surface and a second side surface opposite to each other in a width direction orthogonal to the lamination direction and the length direction; and

[0012] an external electrode connected to the internal electrode layer,

[0013] The laminated body has:

[0014] an inner layer portion including, in the stacking direction, from the inner electrode layer located closest to the first main surface among the plurality of inner electrode layers to the inner electrode layer located closest to the second main surface among the plurality of inner electrode layers, and the plurality of inner electrode layers are arranged to face each other with the dielectric layer interposed therebetween;

[0015] A first main surface side outer layer portion is formed of a plurality of dielectric layers located between the first main surface and an internal electrode layer located closest to the first main surface among the plurality of internal electrode layers; and

[0016] The second main surface side outer layer portion is formed by a plurality of dielectric layers located between the second main surface and the internal electrode layer located closest to the second main surface among the plurality of internal electrode layers.

[0017] At least one of the first main surface side outer layer portion and the second main surface side outer layer portion is provided with a discharge path formed along a plane perpendicular to the stacking direction and capable of discharging elements to the outside of the stacked body.

[0018] Effects of the Invention

[0019] According to the present invention, it is possible to provide a multilayer ceramic capacitor capable of suppressing degradation of insulation resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a perspective view of the appearance of the multilayer ceramic capacitor according to the first embodiment.

[0021] Figure 2 yes Figure 1 LT cross-sectional view of the multilayer ceramic capacitor taken along line II-II shown.

[0022] Figure 3 yes Figure 2 A WT cross-sectional view of the multilayer ceramic capacitor taken along line III-III is shown.

[0023] Figure 4 yes Figure 2 FIG. 1 is a LW cross-sectional view of the multilayer ceramic capacitor taken along line IV-IV shown in FIG.

[0024] Figure 5A is a LT cross-sectional view showing a laminated ceramic capacitor in which the plating layer is formed of a three-layer structure. Figure 2 The corresponding figure.

[0025] Figure 5Bis a LT cross-sectional view showing a laminated ceramic capacitor in which the plating layer is formed of a single Sn plating layer. Figure 2 The corresponding figure.

[0026] Figure 5C is a LT cross-sectional view of a multilayer ceramic capacitor showing that the plating layer is directly disposed on the first end surface and the second end surface. Figure 2 The corresponding figure.

[0027] Figure 6 yes Figure 2 The enlarged view of the VI portion in FIG. 1 is an enlarged cross-sectional view schematically showing the cross section of the discharge path.

[0028] Figure 7 yes Figure 2 The cross-sectional view taken along line VII-VII of the multilayer ceramic capacitor shown is an LW cross-sectional view taken along a plane where the discharge path is formed.

[0029] Fig. 8A yes Figure 7 The enlarged view of the VIIIA portion in is an enlarged view schematically showing a microscopic state when the surface of the first dielectric layer is viewed from above.

[0030] Figure 8B It is schematically shown Fig. 8A An enlarged cross-sectional view of a cross section near the surface of the first dielectric layer along line VIIIB-VIIIB of the surface.

[0031] Fig.9A is a diagram showing another example of a plurality of recesses provided on the surface of the first dielectric layer, and is similar to Fig. 8A The corresponding figure.

[0032] Fig. 9B is a diagram showing another example of a plurality of recesses provided on the surface of the first dielectric layer, and is similar to Figure 8B The corresponding figure.

[0033] Fig. 10A is a diagram showing another example of a plurality of recesses disposed on the surface of the first dielectric layer, and is similar to Fig. 8A The corresponding figure.

[0034] Fig. 10B is a diagram showing another example of a plurality of recesses provided on the surface of the first dielectric layer, and is similar to Figure 8B The corresponding figure.

[0035] Fig.11A is a perspective view of the appearance of a multilayer ceramic capacitor according to a first modified example of the above-mentioned embodiment, Figure 1 The corresponding figure.

[0036] Fig. 11B yes Fig.11A The LT cross-sectional view of the multilayer ceramic capacitor along the XIB-XIB line shown is similar to Figure 2 The corresponding figure.

[0037] Fig. 12A This is a perspective view of the appearance of a multilayer ceramic capacitor having openings arranged on the first main surface and the second main surface.

[0038] Fig. 12B is a LT cross-sectional view of a multilayer ceramic capacitor having openings arranged on the first and second main surfaces. Fig. 11B The corresponding figure.

[0039] Fig.13A is a perspective view of the appearance of a multilayer ceramic capacitor according to a second modified example of the above-mentioned embodiment, Figure 1 The corresponding figure.

[0040] Fig. 13B is a cross-sectional view taken along a plane where a discharge path is formed in a multilayer ceramic capacitor according to a second modified example of the above-mentioned embodiment, and is similar to Figure 7 The corresponding figure.

[0041] Fig.14 is a perspective view of the appearance of a multilayer ceramic capacitor according to a third modified example of the above-mentioned embodiment, Fig.13A The corresponding figure.

[0042] Fig.15A is a perspective view of the appearance of a multilayer ceramic capacitor according to a fourth modified example of the above-mentioned embodiment, Figure 1 The corresponding figure.

[0043] Fig. 15B is a cross-sectional view taken along a plane on which a discharge path P is formed in a multilayer ceramic capacitor according to a fourth modified example of the above-described embodiment, and is similar to FIG. Figure 7 The corresponding figure.

[0044] Fig.16 is with Fig. 11B The corresponding drawings are diagrams for explaining the division of regions of the stacked body 10 .

[0045] Fig.17 FIG. 1 is a diagram showing a two-layer structured multilayer ceramic capacitor.

[0046] Fig.18 FIG. 1 is a diagram showing a triple-structured multilayer ceramic capacitor.

[0047] Fig.19 FIG. 1 is a diagram showing a quadruple-structured multilayer ceramic capacitor.

[0048] Fig. 20It is an external perspective view of a multilayer ceramic capacitor according to a second embodiment.

[0049] Fig.21 is a LW cross-sectional view showing the first internal electrode layer of the multilayer ceramic capacitor of the above-mentioned embodiment, and is similar to Figure 4 The corresponding figure.

[0050] Fig. 22 1 is a LW cross-sectional view showing a second internal electrode layer of the multilayer ceramic capacitor according to the above embodiment.

[0051] Fig.23 is a cross-sectional view taken along a plane where a discharge path is formed in the multilayer ceramic capacitor of the above-mentioned embodiment, and is similar to Figure 7 The corresponding figure.

[0052] Fig.24 is a perspective view of the appearance of a multilayer ceramic capacitor according to a first modified example of the above-mentioned embodiment, Fig. 20 The corresponding figure.

[0053] Fig.25A It is an external perspective view of a multilayer ceramic capacitor according to a second modified example of the above-mentioned embodiment.

[0054] Fig.25B is a cross-sectional view taken along a plane where a discharge path is formed in a multilayer ceramic capacitor according to a second modified example of the above-mentioned embodiment, and is similar to Fig.23 The corresponding figure.

[0055] Fig.26 is a perspective view of the appearance of a multilayer ceramic capacitor according to a third modified example of the above-mentioned embodiment, Fig.25A The corresponding figure.

[0056] Description of Reference Numerals

[0057] 1: Multilayer ceramic capacitor;

[0058] 10: laminate;

[0059] 11: inner layer;

[0060] 12: first main surface side outer layer portion;

[0061] 13: outer layer portion on the second main surface side;

[0062] LS1: first end surface;

[0063] LS2: second end surface;

[0064] WS1: first side;

[0065] WS2: second side;

[0066] TS1: first main surface;

[0067] TS2: Second main surface;

[0068] 20: dielectric layer;

[0069] 30: internal electrode layer;

[0070] 31, 131: first internal electrode layer;

[0071] 32, 132: second internal electrode layer;

[0072] 40: external electrode;

[0073] 40A: first external electrode;

[0074] 40B: second external electrode;

[0075] 40C: third external electrode;

[0076] 40D: fourth external electrode;

[0077] 50A: first base electrode layer;

[0078] 50B: second base electrode layer;

[0079] 60A: first plating layer;

[0080] 60B: second plating layer;

[0081] 61A: first Ni plating layer;

[0082] 61B: second Ni plating layer;

[0083] 62A: first Sn plating layer;

[0084] 62B: second Sn plating layer;

[0085] 63A: first Cu plating layer;

[0086] 63B: second Cu plating layer;

[0087] 80: Cavity (concave);

[0088] P: discharge path;

[0089] H, H1, H2: opening;

[0090] L: length direction;

[0091] W: width direction;

[0092] T: stacking direction. DETAILED DESCRIPTION

[0093] <First embodiment>

[0094] Hereinafter, a multilayer ceramic capacitor 1 according to a first embodiment of the present disclosure will be described. Figure 1 It is a perspective view of the appearance of the multilayer ceramic capacitor 1 according to the present embodiment. Figure 2 yes Figure 1 FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line II-II. Figure 3 yes Figure 2 1 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line III-III. Figure 4 yes Figure 2 1 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line IV-IV.

[0095] The multilayer ceramic capacitor 1 includes a multilayer body 10 and external electrodes 40 .

[0096] exist Figure 1 to Figure 4 The XYZ orthogonal coordinate system is shown. The length direction L of the laminated ceramic capacitor 1 and the laminated body 10 corresponds to the X direction. The width direction W of the laminated ceramic capacitor 1 and the laminated body 10 corresponds to the Y direction. The stacking direction T of the laminated ceramic capacitor 1 and the laminated body 10 corresponds to the Z direction. Here, Figure 2 The section shown is also referred to as the LT section. Figure 3 The section shown is also referred to as the WT section. Figure 4 The section shown is also referred to as the LW section.

[0097] like Figure 1 to Figure 4 As shown, the stack 10 includes a first main surface TS1 and a second main surface TS2 opposite to each other in the stacking direction T, a first end surface LS1 and a second end surface LS2 opposite to each other in the length direction L orthogonal to the stacking direction T, and a first side surface WS1 and a second side surface WS2 opposite to each other in the width direction W orthogonal to the stacking direction T and the length direction L.

[0098] The laminate 10 has a substantially rectangular parallelepiped shape. In addition, the dimension in the length direction L of the laminate 10 is not necessarily longer than the dimension in the width direction W. It is preferred that the corners and ridges of the laminate 10 are rounded. The corner is the portion where three faces of the laminate intersect, and the ridge is the portion where two faces of the laminate intersect. In addition, a part or all of the surface constituting the laminate 10 may be formed with concavities and convexities.

[0099] The laminated body 10 includes an inner layer portion 11 , and a first main surface side outer layer portion 12 and a second main surface side outer layer portion 13 which are arranged in the lamination direction T so as to sandwich the inner layer portion 11 .

[0100] The inner layer portion 11 includes a plurality of dielectric layers 20 and a plurality of internal electrode layers 30. The inner layer portion 11 includes, in the stacking direction T, the internal electrode layer 30 located closest to the first main surface TS1 to the internal electrode layer 30 located closest to the second main surface TS2. In the inner layer portion 11, the plurality of internal electrode layers 30 are arranged opposite to each other with the dielectric layer 20 interposed therebetween. The inner layer portion 11 is a portion that generates electrostatic capacitance and substantially functions as a capacitor. In addition, the inner layer portion 11 is also referred to as an effective layer portion.

[0101] The plurality of dielectric layers 20 are made of dielectric materials. The dielectric material may be, for example, a dielectric ceramic containing BaTiO3, CaTiO3, SrTiO3, or CaZrO3. In addition, the dielectric material may be a material in which a secondary component such as a Mn compound, a Fe compound, a Cr compound, a Co compound, or a Ni compound is added to these main components.

[0102] The thickness of the dielectric layer 20 is preferably 0.5 μm or more and 10 μm or less. The number of the laminated dielectric layers 20 is preferably 15 or more and 700 or less. The number of the dielectric layers 20 is the sum of the number of the dielectric layers of the inner layer portion 11 and the number of the dielectric layers of the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13.

[0103] The plurality of internal electrode layers 30 include a plurality of first internal electrode layers 31 and a plurality of second internal electrode layers 32. The plurality of first internal electrode layers 31 are arranged on the plurality of dielectric layers 20. The plurality of second internal electrode layers 32 are arranged on the plurality of dielectric layers 20. The plurality of first internal electrode layers 31 and the plurality of second internal electrode layers 32 are alternately arranged across the dielectric layers 20 in the stacking direction T of the stacked body 10. The first internal electrode layers 31 and the second internal electrode layers 32 are arranged so as to sandwich the dielectric layers 20.

[0104] The first internal electrode layer 31 includes a first opposing portion 31A opposed to the second internal electrode layer 32 and a first lead portion 31B led out from the first opposing portion 31A to the first end surface LS1. The first lead portion 31B is exposed at the first end surface LS1.

[0105] The second internal electrode layer 32 includes a second opposing portion 32A opposed to the first internal electrode layer 31 and a second lead portion 32B led out from the second opposing portion 32A to the second end surface LS2. The second lead portion 32B is exposed at the second end surface LS2.

[0106] In the present embodiment, the first opposing portion 31A and the second opposing portion 32A are opposed to each other via the dielectric layer 20 , thereby forming capacitance and exhibiting capacitor characteristics.

[0107] The shapes of the first opposing portion 31A and the second opposing portion 32A are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed obliquely. The shapes of the first lead-out portion 31B and the second lead-out portion 32B are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed obliquely.

[0108] The dimension of the first opposing portion 31A in the width direction W and the dimension of the first lead portion 31B in the width direction W may be formed to be the same dimension, or one of the dimensions may be formed to be smaller. The dimension of the second opposing portion 32A in the width direction W and the dimension of the second lead portion 32B in the width direction W may be formed to be the same dimension, or one of the dimensions may be formed to be smaller.

[0109] The first internal electrode layer 31 and the second internal electrode layer 32 include, for example, a metal such as Ni, Cu, Ag, Pd, Au, or an alloy containing at least one of these metals, or other appropriate conductive material. When an alloy is used, the first internal electrode layer 31 and the second internal electrode layer 32 may include, for example, an Ag-Pd alloy.

[0110] The thickness of each of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably about 0.2 μm or more and 2.0 μm or less, for example. The total number of the first internal electrode layers 31 and the second internal electrode layers 32 is preferably 15 or more and 200 or less.

[0111] The first main surface side outer layer portion 12 is located on the first main surface TS1 side of the stack 10. The first main surface side outer layer portion 12 is a collection of multiple dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. That is, the first main surface side outer layer portion 12 is formed by multiple dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 located closest to the first main surface TS1 among the multiple internal electrode layers 30. The dielectric layer 20 used in the first main surface side outer layer portion 12 may be the same as the dielectric layer 20 used in the internal layer portion 11.

[0112] The second main surface side outer layer portion 13 is located on the second main surface TS2 side of the stack 10. The second main surface side outer layer portion 13 is a collection of multiple dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. That is, the second main surface side outer layer portion 13 is formed by multiple dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 located closest to the second main surface TS2 side among the multiple internal electrode layers 30. The dielectric layer 20 used in the second main surface side outer layer portion 13 may be the same as the dielectric layer 20 used in the internal layer portion 11.

[0113] As described above, the laminated body 10 includes the plurality of laminated dielectric layers 20 and the plurality of internal electrode layers 30 laminated on the dielectric layers 20. That is, the laminated ceramic capacitor 1 includes the laminated body 10 in which the dielectric layers 20 and the internal electrode layers 30 are alternately laminated.

[0114] The laminate 10 also includes an opposing electrode portion 11E. The opposing electrode portion 11E is a portion where the first opposing portion 31A of the first internal electrode layer 31 and the second opposing portion 32A of the second internal electrode layer 32 face each other. The opposing electrode portion 11E is configured as a part of the inner layer portion 11. Figure 4 2 shows the range of the opposing electrode portion 11E in the width direction W and the length direction L. In addition, the opposing electrode portion 11E is also referred to as a capacitor effective portion.

[0115] In addition, the stacked body 10 has an end face side outer layer portion. The end face side outer layer portion has a first end face side outer layer portion LG1 and a second end face side outer layer portion LG2. The first end face side outer layer portion LG1 is a portion including the dielectric layer 20 and the first lead portion 31B located between the opposing electrode portion 11E and the first end face LS1. The second end face side outer layer portion LG2 is a portion including the dielectric layer 20 and the second lead portion 32B located between the opposing electrode portion 11E and the second end face LS2. Figure 2 as well as Figure 4 : shows the range of the first end surface side outer layer portion LG1 and the second end surface side outer layer portion LG2 in the length direction L. In addition, the first end surface side outer layer portion LG1 and the second end surface side outer layer portion LG2 are also referred to as L intervals or end intervals.

[0116] In addition, the stacked body 10 has a side outer layer portion. The side outer layer portion has a first side outer layer portion WG1 and a second side outer layer portion WG2. The first side outer layer portion WG1 is a portion including the dielectric layer 20 located between the opposing electrode portion 11E and the first side WS1. The second side outer layer portion WG2 is a portion including the dielectric layer 20 located between the opposing electrode portion 11E and the second side WS2. Figure 3 : shows the range of the first side outer layer portion WG1 and the second side outer layer portion WG2 in the width direction W. In addition, the first side outer layer portion WG1 and the second side outer layer portion WG2 are also referred to as W intervals or side intervals.

[0117] The external electrode 40 includes a first external electrode 40A arranged on the first end surface LS1 side and a second external electrode 40B arranged on the second end surface LS2 side.

[0118] The first external electrode 40A is arranged on the first end surface LS1. The first external electrode 40A is connected to the first internal electrode layer 31. The first external electrode 40A may also be arranged on a portion of the first main surface TS1, a portion of the second main surface TS2, a portion of the first side surface WS1, and a portion of the second side surface WS2. In the present embodiment, the first external electrode 40A is formed to extend from the first end surface LS1 to a portion of the first main surface TS1, a portion of the second main surface TS2, a portion of the first side surface WS1, and a portion of the second side surface WS2.

[0119] The second external electrode 40B is arranged on the second end surface LS2. The second external electrode 40B is connected to the second internal electrode layer 32. The second external electrode 40B may also be arranged on a portion of the first main surface TS1 and a portion of the second main surface TS2 and a portion of the first side surface WS1 and a portion of the second side surface WS2. In the present embodiment, the second external electrode 40B is formed to extend from the second end surface LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2 and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0120] As described above, in the laminate 10, the first opposing portion 31A of the first internal electrode layer 31 and the second opposing portion 32A of the second internal electrode layer 32 are opposed to each other via the dielectric layer 20, thereby forming a capacitor. Therefore, the first external electrode 40A connected to the first internal electrode layer 31 and the second external electrode 40B connected to the second internal electrode layer 32 exhibit capacitor characteristics.

[0121] The first external electrode 40A includes a first base electrode layer 50A and a first plating layer 60A disposed on the first base electrode layer 50A.

[0122] The second external electrode 40B includes a second foundation electrode layer 50B and a second plating layer 60B disposed on the second foundation electrode layer 50B.

[0123] The first base electrode layer 50A is arranged on the first end surface LS1. The first base electrode layer 50A is connected to the first internal electrode layer 31. In the present embodiment, the first base electrode layer 50A is formed to extend from the first end surface LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2 and a portion of the first side surface WS1 and a portion of the second side surface WS2. In addition, the first base electrode layer 50A may be arranged only on the surface of the first end surface LS1 of the stack.

[0124] The second base electrode layer 50B is arranged on the second end surface LS2. The second base electrode layer 50B is connected to the second internal electrode layer 32. In the present embodiment, the second base electrode layer 50B is formed to extend from the second end surface LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2 and a portion of the first side surface WS1 and a portion of the second side surface WS2. In addition, the second base electrode layer 50B may be arranged only on the surface of the second end surface LS2 of the stack.

[0125] The first foundation electrode layer 50A and the second foundation electrode layer 50B (hereinafter, also collectively referred to as foundation electrode layers) include at least one selected from a sintered layer, a thin film layer, and the like.

[0126] The base electrode layer of the present embodiment is a sintered layer. The sintered layer preferably contains a metal component and a ceramic component. Thus, the adhesion between the stack 10 and the base electrode layer can be improved. As the metal component contained in the sintered layer, for example, at least one selected from Ni, Cu, Ag, Pd, Au, Ag-Pd alloy, etc. can be used. Among them, Ni is particularly preferably used. For example, in the case where the internal electrode layer 30 is formed by Ni, the metal of the base electrode layer is set to the same type of metal, that is, Ni, so that the metal bonding force is improved. Therefore, the continuity of the joint between the internal electrode layer 30 and the base electrode layer is improved. Thus, the discharge efficiency of the hydrogen absorbed in the internal electrode layer 30 described later can be improved.

[0127] The ceramic component may be the same type of ceramic material as the dielectric layer 20 or a different type of ceramic material from the dielectric layer 20. The ceramic component includes, for example, at least one selected from BaTiO3, CaTiO3, (Ba, Ca)TiO3, SrTiO3, CaZrO3, and the like.

[0128] The sintered layer is preferably a sintered layer formed by simultaneously sintering a stacked chip having an internal electrode layer and a dielectric layer and a conductive paste applied to the stacked chip. In this case, as a ceramic material, it is particularly preferred to use a ceramic material of the same type as the dielectric layer 20. As such, the base electrode layer preferably has a metal component and a dielectric material.

[0129] Alternatively, the sintered layer may be a layered body obtained by sintering the stacked small pieces having the internal electrodes and the dielectric layer, and then applying and sintering a conductive paste to the stacked body. Alternatively, the sintered layer may contain a metal component and a glass component.

[0130] Alternatively, the base electrode layer may be formed of a plurality of layers.

[0131] The thickness of the first foundation electrode layer 50A in the longitudinal direction located at the first end surface LS1 is preferably about 1 μm or more and 160 μm or less at the center portion in the height direction T and the width direction W of the first foundation electrode layer 50A, for example.

[0132] The thickness of the second foundation electrode layer 50B in the longitudinal direction located at the second end surface LS2 is preferably about 1 μm or more and 160 μm or less at the center portion in the height direction T and the width direction W of the second foundation electrode layer 50B, for example.

[0133] When the first base electrode layer 50A is also provided on a portion of at least one of the first main surface TS1 and the second main surface TS2, the thickness in the height direction of the first base electrode layer 50A provided on the portion is preferably, for example, greater than 1 μm and less than 40 μm in the central portion in the length direction L and the width direction W of the first base electrode layer 50A provided on the portion.

[0134] When the first base electrode layer 50A is also provided in a portion of at least one of the first side surface WS1 and the second side surface WS2, the thickness in the width direction of the first base electrode layer 50A provided in the portion is preferably, for example, greater than 1 μm and less than 40 μm in the central portion in the length direction L and the height direction T of the first base electrode layer 50A provided in the portion.

[0135] When a second base electrode layer 50B is also provided on a portion of at least one of the first main surface TS1 and the second main surface TS2, the thickness in the height direction of the second base electrode layer 50B provided on the portion is preferably, for example, greater than 1 μm and less than 40 μm in the central portion in the length direction L and the width direction W of the second base electrode layer 50B provided on the portion.

[0136] When the second base electrode layer 50B is also provided in a portion of at least one of the first side surface WS1 and the second side surface WS2, the thickness in the width direction of the second base electrode layer 50B provided in the portion is preferably, for example, greater than 1 μm and less than 40 μm in the central portion in the length direction L and the height direction T of the second base electrode layer 50B provided in the portion.

[0137] The first plating layer 60A is arranged to cover the first base electrode layer 50A.

[0138] The second plating layer 60B is arranged to cover the second base electrode layer 50B.

[0139] The first plating layer 60A and the second plating layer 60B (hereinafter, also collectively referred to as plating layers) include, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc. More preferably, the plating layer includes at least one of Cu, Ni, and Sn. Alternatively, the plating layer includes multiple types of Cu, Ni, and Sn.

[0140] The first plating layer 60A and the second plating layer 60B may each be formed of a plurality of layers.

[0141] For example, the plating layer may have a two-layer structure in which a Sn plating layer is formed on a Ni plating layer.

[0142] For example, Figure 2 to Figure 4 As shown, the first plating layer 60A may be formed of a first Ni plating layer 61A disposed on the first base electrode layer 50A and a first Sn plating layer 62A disposed on the first Ni plating layer 61A.

[0143] The second plating layer 60B may be formed of a second Ni plating layer 61B disposed on the second base electrode layer 50B and a second Sn plating layer 62B disposed on the second Ni plating layer 61B.

[0144] The Ni plating layer prevents the base electrode layer from being corroded by solder when mounting the multilayer ceramic capacitor 1. In addition, the Sn plating layer improves the wettability of solder when mounting the multilayer ceramic capacitor 1. Thus, the multilayer ceramic capacitor 1 can be mounted easily.

[0145] Furthermore, by not providing a Cu plating layer described later and only forming the plating layer with two layers of a Ni plating layer and a Sn plating layer, the thickness of the external electrode 40 can be formed thin. Therefore, the degree of freedom in designing the size of the stacked body 10 is increased, which can contribute to the increase of the capacitance. In addition, even if the Cu plating layer is not provided, the moisture resistance can be ensured by the base electrode layer.

[0146] The plating layer is not limited to a two-layer structure, but is preferably a three-layer structure of a Cu plating layer, a Ni plating layer, and a Sn plating layer. Figure 5A is a LT cross-sectional view showing a laminated ceramic capacitor 1 in which the plating layer is formed of a three-layer structure. Figure 2 The corresponding figure.

[0147] For example, Figure 5A As shown, the first plating layer 60A preferably includes a first Cu plating layer 63A disposed on the first base electrode layer 50A, a first Ni plating layer 61A disposed on the first Cu plating layer 63A, and a first Sn plating layer 62A disposed on the first Ni plating layer 61A.

[0148] The second plating layer 60B preferably includes a second Cu plating layer 63B disposed on the second base electrode layer 50B, a second Ni plating layer 61B disposed on the second Cu plating layer 63B, and a second Sn plating layer 62B disposed on the second Ni plating layer 61B.

[0149] The Cu plating layer has high moisture resistance. Therefore, by providing the Cu plating layer, it is possible to further suppress the intrusion of moisture from the outside into the inside of the external electrode 40 .

[0150] Alternatively, the plating layer may be formed of a single Sn plating layer. Figure 5B is a LT cross-sectional view showing a laminated ceramic capacitor 1 in which the plating layer is formed of a single Sn plating layer. Figure 2 The corresponding figure.

[0151] For example, Figure 5B As shown, the first plating layer 60A may be formed of a first Sn plating layer 62A disposed on the first base electrode layer 50A.

[0152] The second plating layer 60B may be formed of a second Sn plating layer 62B disposed on the second foundation electrode layer 50B.

[0153] By not providing a Cu plating layer and a Ni plating layer but only forming the plating layer with a Sn plating layer, the thickness of the external electrode 40 can be formed thin. Therefore, the degree of freedom in designing the size of the stacked body 10 is improved, which can contribute to the increase of the capacitance. In addition, in this case, by using Ni as the metal of the base electrode layer, the external electrode can be prevented from being corroded by the solder when the multilayer ceramic capacitor 1 is mounted only by the base electrode layer.

[0154] Alternatively, a structure in which the plating layer is directly disposed on the first end surface LS1 and the second end surface LS2 may be adopted. Figure 5C is a LT cross-sectional view of the multilayer ceramic capacitor 1 showing that the plating layer is directly disposed on the first end surface LS1 and the second end surface LS2. Figure 2 The corresponding figure.

[0155] exist Figure 5C In the example shown, the first base electrode layer 50A is not formed on the first end surface LS1 of the stack. In addition, the first base electrode layer 50A is arranged on a portion of the first main surface TS1 and a portion of the second main surface TS2 on the side of the first end surface LS1. In addition, although not shown in the figure, the first base electrode layer 50A is arranged on a portion of the first side surface WS1 and a portion of the second side surface WS2 on the side of the first end surface LS1.

[0156] The first plating layer 60A is directly arranged on the stacked body 10 on the first end surface LS1. The first plating layer 60A is arranged on the first main surface TS1, the second main surface TS2, the first side surface WS1, and the second side surface WS2 to cover the first base electrode layer 50A arranged on the first main surface TS1, the second main surface TS2, the first side surface WS1, and the second side surface WS2. In this way, the first plating layer 60A is arranged on the first end surface LS1 without passing through the base electrode layer.

[0157] exist Figure 5C In the example shown, the second base electrode layer 50B is not formed on the second end surface LS2. In addition, the second base electrode layer 50B is arranged on a portion of the first main surface TS1 and a portion of the second main surface TS2 on the second end surface LS2 side. In addition, although not shown in the figure, the second base electrode layer 50B is arranged on a portion of the first side surface WS1 and a portion of the second side surface WS2 on the second end surface LS2 side.

[0158] The second plating layer 60B is directly arranged on the stacked body 10 on the second end surface LS2. The second plating layer 60B is arranged on the first main surface TS1, the second main surface TS2, the first side surface WS1, and the second side surface WS2 to cover the second base electrode layer 50B arranged on the first main surface TS1, the second main surface TS2, the first side surface WS1, and the second side surface WS2. In this way, the second plating layer 60B is arranged on the second end surface LS2 without passing through the base electrode layer.

[0159] In this case, it is preferable that the first plating layer 60A and the second plating layer 60B are each formed of a plurality of layers.

[0160] For example, Figure 5C As shown, the first plating layer 60A preferably includes a first Ni plating layer 61A disposed on the first end surface LS1 and a first Sn plating layer 62A disposed on the first Ni plating layer 61A.

[0161] For example, Figure 5C As shown, the second plating layer 60B preferably includes a second Ni plating layer 61B disposed on the second end surface LS2 and a second Sn plating layer 62B disposed on the second Ni plating layer 61B.

[0162] More specifically, the first Ni plating layer 61A is directly arranged on the stacked body 10 on the first end surface LS1. The first Ni plating layer 61A is arranged in the first main surface TS1, the second main surface TS2, the first side surface WS1, and the second side surface WS2 to cover the first base electrode layer 50A arranged on the first main surface TS1, the second main surface TS2, the first side surface WS1, and the second side surface WS2. The first Sn plating layer 62A is arranged to cover the first Ni plating layer 61A.

[0163] The second Ni plating layer 61B is directly arranged on the stacked body 10 on the second end surface LS2. The second Ni plating layer 61B is arranged on the first main surface TS1, the second main surface TS2, the first side surface WS1, and the second side surface WS2 to cover the second base electrode layer 50B arranged on the first main surface TS1, the second main surface TS2, the first side surface WS1, and the second side surface WS2. The second Sn plating layer 62B is arranged to cover the second Ni plating layer 61B.

[0164] By using Ni as the metal of the plating layer directly disposed on the laminated body 10, it is possible to suppress the external electrodes from being corroded by the solder when mounting the laminated ceramic capacitor 1 even without providing a base electrode layer. In addition, by providing the Sn plating layer, the wettability of the solder when mounting the laminated ceramic capacitor 1 is improved. This makes it easier to mount the laminated ceramic capacitor 1.

[0165] Furthermore, since the base electrode layer is not provided on the first end surface and the second end surface, the thickness of the external electrode 40 can be formed thinner. Therefore, the degree of freedom in designing the size of the laminated body 10 is improved, which can contribute to the increase in capacitance.

[0166] Alternatively, the external electrode 40 may be formed only by a plating layer without providing a base electrode layer.

[0167] In addition, the thickness of each of the plating layers constituting the first plating layer 60A and the second plating layer 60B is preferably 1 μm or more and 15 μm or less. That is, the thickness of each of the first Cu plating layer 63A, the first Ni plating layer 61A, the first Sn plating layer 62A, the second Cu plating layer 63B, the second Ni plating layer 61B, and the second Sn plating layer 62B is preferably 1 μm or more and 15 μm or less.

[0168] In addition, as in the various examples described above, the external electrode 40 preferably includes an inner layer and an outer layer arranged on the outer surface side relative to the inner layer, the inner layer including Ni as a metal component, and the outer layer including Sn as a metal component. The inner layer including Ni as a metal component is preferably arranged on the surface of the laminate 10 where the internal electrode layer 30 is exposed. The outer layer including Sn as a metal component is preferably arranged to cover the inner layer. For example, the first external electrode 40A may include a first inner layer and a first outer layer, the first inner layer being arranged on the first end surface LS1 and including Ni as a metal component, the first outer layer being arranged on the outer surface side of the first inner layer and including Sn as a metal component, and the second external electrode 40B including a second inner layer and a second outer layer, the second inner layer being arranged on the second end surface LS2 and including Ni as a metal component, and the second outer layer being arranged on the outer surface side of the second inner layer and including Sn as a metal component. As the external electrode 40 mainly containing Ni as a metal component, for example, a sintered layer containing Ni or a Ni plating layer may be used. As the outer layer mainly containing Sn as a metal component, for example, a Sn plating layer may be used.

[0169] In addition, if the dimension in the length direction of the multilayer ceramic capacitor 1 including the stacked body 10 and the external electrode 40 is set to L dimension, the L dimension is preferably 0.02 mm or more and 2.1 mm or less. In addition, if the dimension in the height direction of the multilayer ceramic capacitor 1 is set to T dimension, the T dimension is preferably 0.01 mm or more and 1.8 mm or less. In addition, if the dimension in the width direction of the multilayer ceramic capacitor 1 is set to W dimension, the W dimension is preferably 0.01 mm or more and 1.8 mm or less.

[0170] The multilayer ceramic capacitor 1 of the present embodiment has a discharge path P that can discharge elements to the outside of the multilayer body 10 .

[0171] The discharge path P is arranged in at least one of the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13 of the stacked body 10. In the present embodiment, the discharge path P is arranged in the first main surface side outer layer portion 12. The discharge path P is formed along the LW cross section, that is, along a plane orthogonal to the stacking direction T. In other words, the discharge path P is formed along a plane extending in the length direction L and the width direction W.

[0172] Figure 6 yes Figure 2 The enlarged view of the VI portion in FIG. 1 is an enlarged cross-sectional view schematically showing the cross section of the discharge path P.

[0173] like Figure 6As shown, the discharge path P includes a plurality of cavities 80 arranged on a plane perpendicular to the stacking direction T. The cavity 80 may also have a spherical curved surface. The plurality of cavities 80 are connected to each other to form the discharge path P.

[0174] The discharge path P is disposed, for example, between the plurality of dielectric layers 20 constituting the first main surface side outer layer portion 12. Figure 6 2 shows an example in which a discharge path P is formed on a boundary surface BS between a first dielectric layer 20A included in a plurality of dielectric layers 20 constituting the first main-surface-side outer layer portion 12 and a second dielectric layer 20B arranged to overlap with the first dielectric layer 20A.

[0175] Specifically, a plurality of recesses are arranged on the surface of the first dielectric layer 20A that is opposite to the second dielectric layer 20B. A plurality of recesses are arranged on the surface of the second dielectric layer 20B that is opposite to the first dielectric layer 20A. By arranging the surfaces having the plurality of recesses to be opposite to each other, the plurality of recesses form a plurality of cavities 80. Furthermore, the plurality of recesses formed in the first dielectric layer 20A and the plurality of recesses formed in the second dielectric layer 20B are arranged at offset positions in a direction orthogonal to the stacking direction T. For example, Figure 6 2 shows an example in which the plurality of recesses formed in the first dielectric layer 20A and the plurality of recesses formed in the second dielectric layer 20B are arranged at positions shifted in the longitudinal direction L. Thus, the plurality of cavities 80 are connected to each other, and the discharge path P is formed.

[0176] Figure 7 yes Figure 2 The LW cross-sectional view along the line VII-VII of the multilayer ceramic capacitor 1 shown is a cross-sectional view along a plane along the boundary surface BS between the first dielectric layer 20A and the second dielectric layer 20B, that is, a plane where the discharge path P is formed. In other words, Figure 7 The diagram shows the surface of the first dielectric layer 20A, which is opposed to the second dielectric layer 20B, among the plurality of dielectric layers 20 constituting the first main-surface-side outer layer portion 12 .

[0177] Fig. 8A yes Figure 7 The enlarged view of the VIIIA portion in FIG. 1 schematically shows a microscopic state when the surface of the first dielectric layer 20A is viewed from above. Figure 8B It is schematically shown Fig. 8A The enlarged cross-sectional view of the cross section of the surface of the first dielectric layer 20A along the line VIIIB-VIIIB is shown. Figure 8B In FIG. 1 , only the first dielectric layer 20A is shown, and the second dielectric layer 20B is not shown.

[0178] like Fig. 8A as well as Figure 8B As shown in FIG. 1 , a plurality of concave portions having spherical curved surfaces are formed on the surface of the first dielectric layer 20A. Figure 6 Since it is a part of the cavity 80 in the cavity, it is labeled with the figure mark 80 in the same way as the cavity 80.

[0179] A plurality of recesses 80 are arranged on the surface of the first dielectric layer 20A. In the present embodiment, the plurality of recesses 80 are formed by arranging a plurality of recesses 80 having substantially the same size in a plane.

[0180] like Fig. 8A As shown, the plurality of recesses 80 may also be arranged in a hexagonal closest-packed configuration on the surface of the first dielectric layer 20A. By being arranged in a hexagonal closest-packed configuration, the plurality of recesses 80 may be arranged at a high density on the surface of the first dielectric layer 20A. For example, the plurality of recesses 80 may also be arranged so that, for one recess 80, an average of more than 5 and less than 7 other recesses 80 are located around it. Thus, the plurality of recesses 80 may be arranged at a high density on the surface of the first dielectric layer 20A. In this way, by arranging the recesses 80 at a high density, the discharge path P may be easily formed. In addition, it becomes easy for the fluid to pass through the discharge path P. In addition, the plurality of recesses 80 may also be arranged regularly. However, they may also be arranged irregularly.

[0181] The plurality of recesses 80 each have an opening 81 and a wall surface 82. Fig. 8A As shown, in the present embodiment, the opening 81 constituting the outer edge of the recess 80 is formed into a substantially circular shape.

[0182] Like in Figure 8B As shown in the cross-sectional shape, the wall surface 82 of the recess 80 is composed of a spherical curved surface. That is, the wall surface 82 of the recess 80 is composed of a concave curved surface that constitutes a part of the surface of a sphere. The wall surface of the recess 80 may also be a hemispherical shape. However, the wall surface 82 of the recess 80 may also be a spherical curved surface that is less than a hemisphere.

[0183] The surface of the first dielectric layer 20A has a plurality of recessed portions 80 and land portions 90 which are regions where the plurality of recessed portions 80 are not arranged, and the plurality of recessed portions 80 have spherical curved surfaces.

[0184] The average entrance diameter of the plurality of recesses 80 formed on the surface of the first dielectric layer 20A is preferably, for example, 0.2 μm to 2 μm. The average depth of the plurality of recesses 80 formed on the surface of the first dielectric layer 20A is preferably 0.1 μm to 1 μm.

[0185] Here, the depth of the recessed portion 80 is defined as the maximum value of the distance from the deepest portion of the recessed portion 80 to the opening 81 of the recessed portion 80 in the depth direction of the recessed portion 80 .

[0186] Furthermore, the average depth of the plurality of recesses 80 formed on the surface of the first dielectric layer 20A may be not less than 25% and not more than 50% of the average entrance diameter of the plurality of recesses 80 .

[0187] The surface of the second dielectric layer 20B facing the first dielectric layer 20A is also provided with a plurality of concave portions 80. Thus, by arranging the surfaces having the plurality of concave portions 80 facing each other, a plurality of cavities 80 are formed, thereby forming a discharge path P. Here, the cavities 80 constituting the discharge path P have spherical curved surfaces. Thus, the resistance of the fluid when passing through the discharge path P is reduced.

[0188] Here, the height of the cavity 80 in the stacking direction T is the same as the depth of the recessed portion 80. Therefore, the average height of the plurality of cavities 80 in the stacking direction T is preferably 0.1 μm or more and 1 μm or less. Thus, the discharge path P can be easily formed.

[0189] The shape of the cavity 80 forming the discharge path P is not particularly limited. However, the cavity 80 is preferably configured so that the dielectric column 91 remains. Here, the dielectric column 91 is formed by a solid portion of the dielectric material existing between the plurality of cavities 80. Figure 8B The solid portions shown between the plurality of recesses 80 form dielectric pillars 91 .

[0190] Here, there are portions where the cavities 80 facing each other are connected to each other and portions where the banks 90 facing each other are in contact with each other at the boundary surface BS of the plurality of dielectric layers 20. In this way, the banks 90 on the surface of the dielectric layer 20 are in contact with the banks 90 on the surface of the opposing dielectric layer 20, so that the dielectric pillars 91 are formed by the solid portions of the dielectric material existing between the plurality of cavities 80.

[0191] The plurality of cavities 80 are connected to each other to form a discharge path P. When viewed in three dimensions, a portion of one cavity 80 is connected to another cavity 80. The connection between the plurality of cavities is continuous, thereby forming a path P through which elements can be discharged. In addition, within the plane in which the cavities 80 are formed, as long as the connection between the plurality of cavities is continuous in any path, a discharge path P through which elements can be discharged can be formed, and a portion of the cavities 80 may be isolated.

[0192] By such a structure, it is possible to ensure that the first main surface side outer layer portion 12 located on the first main surface TS1 side of the position where the cavity 80 is provided and the first main surface side outer layer portion 12 located on the second main surface TS2 side of the position where the cavity 80 is provided are in contact with each other. Therefore, it is possible to improve the adhesion between the first main surface side outer layer portion 12 located on the first main surface TS1 side of the position where the cavity 80 is provided and the first main surface side outer layer portion 12 located on the second main surface TS2 side of the position where the cavity 80 is provided. In other words, it is possible to improve the adhesion between the first dielectric layer 20A and the second dielectric layer 20B that form the discharge path P therebetween. Thus, it is possible to form the discharge path P in the first main surface side outer layer portion 12 while ensuring the connectivity of the first main surface side outer layer portion 12 itself.

[0193] The above structure can easily connect the plurality of cavities 80 to each other. Furthermore, a continuous cavity 80 capable of discharging elements to the outside of the laminate 10 can be formed on the same plane from the first end surface LS1 to the second end surface LS2. Therefore, even when hydrogen is absorbed by the internal electrode layer 30, the hydrogen absorbed by the internal electrode layer 30 can be easily discharged from the external electrode 40 through the cavity 80 to the outside of the laminated ceramic capacitor 1.

[0194] In addition, the shape of the plurality of recesses 80 formed on the surfaces of the dielectric layers 20A and 20B facing each other is not limited to the following. Fig. 8A , Figure 8B For example, the shape of the plurality of recesses 80 may also be as follows Fig.9A , Fig. 9B The form shown. Fig.9A , Fig. 9B is a diagram showing another example of the plurality of recesses 80, Fig. 8A , Figure 8B The corresponding figure.

[0195] like Fig.9A , Fig. 9B As shown, the plurality of recesses 80 may also have recesses with different inlet diameters. Fig.9A , Fig. 9BAs shown, the plurality of recesses 80 may also include a recess 80B having a larger entrance diameter relative to the average entrance diameter and a recess 80C having a smaller entrance diameter relative to the average entrance diameter. In this case, the average depth of the recess 80C having an entrance diameter smaller than the average entrance diameter may also be less than the average depth of the recess 80B having a larger entrance diameter relative to the average entrance diameter. In addition, the recess 80B having a larger entrance diameter relative to the average entrance diameter and the recess 80C having a smaller entrance diameter relative to the average entrance diameter may be regularly arranged, but may also be irregularly arranged. In addition, the plurality of recesses 80 may also include a plurality of recesses whose entrance diameters are different in stages or randomly.

[0196] The plurality of recesses 80B and 80C having different entrance diameters are provided with approximately circular openings 81B and 81C and wall surfaces 82B and 82C having spherical curved surfaces. In addition, the openings 81B and 81C are not limited to being approximately circular, but may be other shapes. In addition, the wall surface 82B of the recess 80B may be approximately hemispherical or a spherical curved surface less than a hemisphere, and the wall surface 82C of the recess 80C may be a spherical curved surface less than a hemisphere.

[0197] Even in this case, the average entrance diameter of the plurality of recesses 80 is preferably 0.2 μm or more and 2 μm or less. In addition, the average depth of the plurality of recesses 80 is preferably 0.1 μm or more and 1 μm or less.

[0198] In addition, the plurality of recesses 80 formed on the surfaces of the dielectric layers 20A and 20B facing each other may be in the form of: Fig. 10A , Fig. 10B The form shown. Fig. 10A , Fig. 10B is a diagram showing another example of the plurality of recesses 80, Fig. 8A , Figure 8B The corresponding figure.

[0199] like Fig. 10A , Fig. 10B As shown in FIG. 1 , the plurality of recesses 80 may include a recess 80D having an opening 81D in a substantially hexagonal shape. Thereby, the plurality of recesses 80 can be arranged at a higher density.

[0200] In this case as well, the wall surface 82D of the recessed portion 80D may have a spherical curved surface. In other words, the wall surface 82D of the recessed portion 80D may have a concave curved surface constituting a part of the surface of a sphere.

[0201] Even in this case, the average entrance diameter of the plurality of recesses 80 is preferably 0.2 μm or more and 2 μm or less. In addition, the average depth of the plurality of recesses 80 is preferably 0.1 μm or more and 1 μm or less.

[0202] In addition, if Fig. 8A , Figure 8B The recess shown, such as Fig.9A , Fig. 9B The recesses with different inlet diameters shown, such as Fig. 10A , Fig. 10B The recesses having different opening shapes shown may be mixed. In addition, the average entrance diameter of the plurality of recesses 80 formed on the surface of the first dielectric layer 20A and the average entrance diameter of the plurality of recesses 80 formed on the surface of the second dielectric layer 20B may be different.

[0203] The discharge path P includes: a path connecting the first end surface LS1 where the first external electrode 40A is arranged to the opening H arranged on the surface of the stacked body 10 exposed from the external electrode 40; and a path connecting the second end surface LS2 where the second external electrode 40B is arranged to the opening H arranged on the surface of the stacked body 10 exposed from the external electrode 40. The opening H is preferably arranged on at least one of the first side surface WS1 and the second side surface WS2. In the present embodiment, the opening H is formed on the first side surface WS1 and the second side surface WS2.

[0204] exist Figure 1 , the area of ​​the opening H arranged on the second side surface WS2 is shown. The opening H is arranged on the surface of the stacked body 10 exposed from the first external electrode 40A and the second external electrode 40B. That is, the opening H is arranged on the exposed surface of the stacked body 10. In the present embodiment, the opening H is arranged on the first side surface WS1 and the second side surface WS2 at a position on the stacking direction T that is the same as the plane on which the discharge path P is formed. In the present embodiment, the opening H is formed as a portion continuous from the planar discharge path P. Therefore, the opening H has the same Figure 6 The cross-section of the discharge path P shown is of a similar shape.

[0205] In the present embodiment, the plurality of cavities 80 forming the discharge path P are arranged between the plurality of dielectric layers 20 constituting the first main surface side outer layer portion 12 on the entire surface of the dielectric layer 20, that is, on the entire surface of the plane orthogonal to the stacking direction T. Specifically, as Figure 7 As shown, the concave portion 80 forming the discharge path P is arranged on the entire surface of the first dielectric layer 20A. That is, the discharge path P is formed substantially on the entire surface of the plane perpendicular to the stacking direction T of the first dielectric layer 20A.

[0206] As described above, the plurality of cavities 80 are preferably arranged at least over the entire surface of the dielectric layer 20 forming either the first main surface side outer layer portion 12 or the second main surface side outer layer portion 13. This can increase the total area of ​​the path through which the fluid passes.

[0207] Through the above structure, as the discharge path P, there can be formed: a path connecting the first end face LS1 where the first external electrode 40A is arranged to the opening portion H arranged on the surface of the stack 10 exposed from the external electrode 40; and a path connecting the second end face LS2 where the second external electrode 40B is arranged to the opening portion H arranged on the surface of the stack 10 exposed from the external electrode 40.

[0208] As described above, the plurality of cavities 80 preferably have at least a path extending from the first end surface LS1 and the second end surface LS2 to the first side surface WS1 or the second side surface WS2 of the stack 10. That is, it is preferred that a plurality of cavities 80 capable of discharging elements to the outside of the stack 10 are arranged on the same plane within the range from the first end surface LS1 to the second end surface LS2.

[0209] In the present embodiment, the discharge path P is formed as a path connecting the surface of the stacked body 10 covered by the external electrode 40 and the surface of the stacked body 10 exposed from the external electrode 40. Thus, even when hydrogen is stored in the internal electrode layer 30, the hydrogen stored in the internal electrode layer 30 can be discharged to the outside of the multilayer ceramic capacitor 1 through the external electrode 40 and the discharge path P. Furthermore, even when hydrogen is stored in the external electrode 40, the hydrogen stored in the external electrode 40 can be discharged to the outside of the multilayer ceramic capacitor 1. Therefore, the amount of hydrogen contained in the internal electrode layer 30 can be reduced, and the diffusion of hydrogen into the dielectric layer 20 can be reduced. As a result, the degradation of the insulation resistance of the multilayer ceramic capacitor 1 can be suppressed.

[0210] In the past, the following laminated ceramic capacitors were known, that is, they are provided with: a laminated body, in which a plurality of dielectric layers and a plurality of internal electrodes are alternately laminated; and a pair of external electrodes, formed on the surface of the laminated body, so as to be electrically connected to the internal electrodes led out to the surface of the laminated body. Moreover, Ni plating is applied to the surface of the external electrode to prevent solder corrosion during installation, and Sn plating is sometimes applied on the Ni plating to improve the weldability during welding installation. The plating of Ni, Sn, etc. is usually formed by an electrolytic plating method. Patent document 1 shows the following problem, that is, when hydrogen is generated due to a chemical reaction in the plating process and the hydrogen is absorbed by the internal electrode, the hydrogen gradually reduces the surrounding dielectric layer, so that the insulation resistance of the laminated ceramic capacitor deteriorates. Moreover, as a solution, the following scheme is shown, that is, when an internal electrode mainly composed of a precious metal such as an Ag-Pd alloy is used, Ni is added to the internal electrode, and Ni is a metal that inhibits the absorption of hydrogen.

[0211] In recent years, in order to reduce material costs, base metals such as Ni are often used as materials for internal electrodes instead of precious metals such as Ag and Pd. Here, in Patent Document 1, Ni is described as a "metal that makes the absorption of hydrogen inert". However, according to the research of the inventors, it is known that even when Ni is used for the internal electrode, the insulation resistance will still deteriorate due to the influence of hydrogen. In addition, when a metal such as Ni that has the ability to absorb hydrogen is used as a base metal constituting the material of the external electrode including the plating layer, the absorbed hydrogen will be released to a certain extent depending on the temperature conditions. Moreover, in particular, in the case of a high temperature and high humidity load test such as the PCBT test, this phenomenon occurs significantly, and the absorbed hydrogen is released and diffused into the dielectric layer, sometimes causing the degradation of the insulation resistance (IR). Therefore, in order to avoid problems such as the degradation of the insulation resistance caused by the inclusion of hydrogen in the stacked ceramic capacitor, it is best to reduce the absolute amount of hydrogen contained in the stacked ceramic capacitor.

[0212] According to the structure of this embodiment, even when hydrogen is stored in the internal electrode layer 30, the hydrogen stored in the internal electrode layer 30 can be discharged to the outside of the multilayer ceramic capacitor 1 through the discharge path P. Therefore, the amount of hydrogen contained in the internal electrode layer 30 can be reduced, and the diffusion of hydrogen into the dielectric layer 20 can be reduced. As a result, the degradation of the insulation resistance of the multilayer ceramic capacitor 1 can be suppressed.

[0213] As a method of discharging hydrogen stored in the internal electrode layer 30 from the external electrode 40 through the discharge path P to the outside of the multilayer ceramic capacitor 1 , the following method can be adopted.

[0214] The completed multilayer ceramic capacitor 1 is placed in a furnace and heat treated at 150° C. for 1 hour. The atmosphere in the furnace at this time is not particularly limited. By performing such a heat treatment, hydrogen atoms accumulated in the internal electrode layer 30 and the external electrode 40 can be bonded to hydrogen molecules, and the bonded hydrogen molecules can be released to the outside of the multilayer ceramic capacitor 1 through the discharge path P.

[0215] In addition, when the external electrode 40 includes multiple layers, the structure of this embodiment can obtain particularly good effects. For example, the external electrode 40 may also include an inner layer and an outer layer, the outer layer is arranged on the outer surface side of the inner layer, and is less likely to allow hydrogen to penetrate than the inner layer. The outer layer is preferably configured to directly or indirectly cover the inner layer. For example, the external electrode 40 may also include an inner layer and an outer layer arranged on the outer surface side of the inner layer, the inner layer contains Ni as a metal component, and the outer layer contains Sn as a metal component. Compared with the Ni plating layer and the sintered layer containing Ni as a metal component, the Sn plating layer is less likely to allow hydrogen to penetrate. Even with a stacked ceramic capacitor 1 having such an external electrode 40, hydrogen absorbed in the internal electrode layer 30 can be discharged to the outside of the stacked ceramic capacitor 1 through the discharge path P formed by the inner layer of the external electrode 40 and the stack 10.

[0216] Hereinafter, a first modified example of the multilayer ceramic capacitor 1 of the present embodiment will be described. In the following description, the same reference numerals are used for the same structures as those of the above-described embodiment, and detailed description thereof will be omitted. Fig.11A is a perspective view of the appearance of a multilayer ceramic capacitor 1 according to a first modified example of the present embodiment. Figure 1 The corresponding figure. Fig. 11B yes Fig.11A The LT cross-sectional view of the multilayer ceramic capacitor along the XIB-XIB line shown is similar to Figure 2 The corresponding figure.

[0217] In this modification, the discharge path P is arranged in the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13 of the stacked body 10. The second main surface side outer layer portion 13 is provided with the same discharge path P as that arranged in the first main surface side outer layer portion 12. Figure 7 The discharge path P is shown.

[0218] On the first side surface WS1 and the second side surface WS2, an opening H similar to the opening H arranged in the first main surface side outer layer portion 12 is arranged in the second main surface side outer layer portion 13. Fig.11A , the region of the opening H of the second principal surface side outer layer portion 13 arranged on the second principal surface TS2 side is shown together with the region of the opening H of the first principal surface side outer layer portion 12 arranged on the first principal surface TS1 side.

[0219] As described above, the discharge path P is preferably arranged on the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13. In other words, the discharge path P is preferably arranged on both sides of the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13. Thus, it is possible to discharge hydrogen stored in the internal electrode layer 30 to the outside of the multilayer ceramic capacitor 1 from the discharge path P arranged on both sides of the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13, not just on one side. In addition, even when the plurality of cavities 80 forming the discharge path P are provided on both sides of the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13, the plurality of cavities 80 are preferably arranged on the entire surface of the first main surface side outer layer portion 12 and the entire surface of the second main surface side outer layer portion 13.

[0220] In addition, if Fig. 12A , Fig. 12B As shown, the opening may be arranged on either the first main surface TS1 or the second main surface TS2. Fig. 12A This is an external perspective view of a multilayer ceramic capacitor 1 in which openings are provided on the first main surface TS1 and the second main surface TS2 . Fig. 12B is a LT cross-sectional view of a multilayer ceramic capacitor 1 having openings arranged on the first main surface TS1 and the second main surface TS2. Fig. 11B The corresponding figure.

[0221] As described above, a discharge hole may be formed to communicate from the discharge path P to the first main surface TS1, the discharge path P is formed by a plurality of cavities 80, and the opening H1 of the discharge hole is arranged on the first main surface TS1. In addition, a discharge hole may be formed to communicate from the discharge path P to the second main surface TS2, the discharge path P is formed by a plurality of cavities 80, and the opening H2 of the discharge hole is arranged on the second main surface TS2. Thus, hydrogen absorbed in the internal electrode layer 30 can be more efficiently discharged to the outside of the multilayer ceramic capacitor 1. Therefore, the effect of this embodiment can be more effectively exerted.

[0222] Furthermore, when an opening is provided on either the first main surface TS1 or the second main surface TS2 , an opening may also be provided on the first side surface WS1 or the second side surface WS2 , but an opening may not be provided on the first side surface WS1 or the second side surface WS2 .

[0223] The shape of the discharge hole is not particularly limited, but is preferably cylindrical. The size of the discharge hole is not particularly limited, but when the discharge hole is formed in a cylindrical shape, the diameter is preferably 0.1 μm or more and 1 μm or less.

[0224] In addition, when the opening is arranged on either the first main surface TS1 or the second main surface TS2 , the firing may be performed after the holes are formed in the laminated sheet before firing.

[0225] Hereinafter, a second modification of the multilayer ceramic capacitor 1 of the present embodiment will be described. In the following description, the same reference numerals are given to the same structures as those of the above-described embodiment, and detailed descriptions thereof will be omitted. Fig.13A is a perspective view of the appearance of a multilayer ceramic capacitor 1 according to a second modified example of the present embodiment. Figure 1 The corresponding figure. Fig. 13B is a cross-sectional view taken along a plane where the discharge path P is formed in the multilayer ceramic capacitor 1 according to the second modified example of the present embodiment, and is similar to FIG. Figure 7 The corresponding figure.

[0226] The discharge path P is not limited to being formed by the plurality of cavities 80 arranged on the entire surface of the dielectric layer 20. As shown in this modification, the region where the plurality of cavities 80 forming the discharge path P are arranged may be a specific region.

[0227] For example, the plurality of cavities 80 forming the discharge path P may be arranged in a cross-shaped region on the surface of the dielectric layer 20 between the plurality of dielectric layers 20 constituting the first main surface side outer layer portion 12. Specifically, Fig. 13B As shown, the concave portion 80 forming the discharge path P may be arranged in a cross-shaped region on the surface of the first dielectric layer 20A. Similarly, the concave portion 80 forming the discharge path P may be arranged in a cross-shaped region on the surface of the second dielectric layer 20B. In this case, the discharge path P is substantially formed in the cross-shaped region on the surface of the first dielectric layer 20A.

[0228] The region where the concave portion 80 forming the cavity forming the discharge path P is arranged includes, for example, a first lead-out region PE1 led to the first external electrode 40A, a second lead-out region PE2 led to the second external electrode 40B, and a discharge lead-out region PD led to the exposed surface of the stacked body 10. Fig. 13B In the illustrated example, the first lead-out area PE1 is led out to the first end surface LS1 , the second lead-out area PE2 is led out to the second end surface LS2 , and the discharge lead-out area PD is led out to the first side surface WS1 and the second side surface WS2 .

[0229] The discharge lead-out region PD led out to the exposed surface of the stacked body 10 forms an opening H on the exposed surface of the stacked body 10. Fig.13A, the region of the opening H of the first main surface side outer layer portion 12 arranged on the first main surface TS1 side is shown. The opening H is preferably arranged on at least one of the first side surface WS1 and the second side surface WS2. In the present embodiment, the opening H is formed on both the first side surface WS1 and the second side surface WS2.

[0230] With such a structure, a path connecting from the first end surface LS1 where the first external electrode 40A is arranged to the opening H arranged on the surface of the stacked body 10 exposed from the external electrode 40 and a path connecting from the second end surface LS2 where the second external electrode 40B is arranged to the opening H arranged on the surface of the stacked body 10 exposed from the external electrode 40 are also formed as the discharge path P. In addition, according to the structure of this modified example, the contact area between the first dielectric layer 20A and the second dielectric layer 20B is increased, so that the bonding force between the first dielectric layer 20A and the second dielectric layer 20B forming the discharge path P therebetween can be improved.

[0231] Hereinafter, a third modification of the multilayer ceramic capacitor 1 of the present embodiment will be described. In the following description, the same reference numerals are used for the same structures as those of the second modification of the above-described embodiment, and detailed descriptions thereof will be omitted. Fig.14 is a perspective view of the appearance of a multilayer ceramic capacitor 1 according to a third modified example of the present embodiment. Fig.13A The corresponding figure.

[0232] In this modification, the discharge path P is arranged in the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13 of the stacked body 10. The second main surface side outer layer portion 13 is provided with the same discharge path P as that arranged in the first main surface side outer layer portion 12. Fig. 13B The discharge path P is shown.

[0233] On the first side surface WS1 and the second side surface WS2, an opening H similar to the opening H arranged in the first main surface side outer layer portion 12 is arranged in the second main surface side outer layer portion 13. Fig.14 , the region of the opening H of the second principal surface side outer layer portion 13 arranged on the second principal surface TS2 side is shown together with the region of the opening H of the first principal surface side outer layer portion 12 arranged on the first principal surface TS1 side.

[0234] As described above, the discharge path P is preferably disposed on the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13. In other words, the discharge path P is preferably disposed on both sides of the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13. Thus, hydrogen stored in the internal electrode layer 30 can be discharged to the outside of the multilayer ceramic capacitor 1 from the discharge path P disposed on both surfaces of the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13, rather than only on one surface.

[0235] Hereinafter, a fourth modification of the multilayer ceramic capacitor 1 of the present embodiment will be described. In the following description, the same reference numerals are used for the same configurations as those of the above-described embodiment, and detailed descriptions thereof will be omitted. Fig.15A is a perspective view of the appearance of a multilayer ceramic capacitor 1 according to a fourth modified example of the present embodiment. Figure 1 The corresponding figure. Fig. 15B is a cross-sectional view taken along a plane on which a discharge path P is formed in a multilayer ceramic capacitor 1 according to a fourth modified example of the present embodiment, and is similar to FIG. Figure 7 The corresponding figure.

[0236] The discharge path P is not limited to being formed by the plurality of cavities 80 arranged on the surface of the dielectric layer 20. As shown in this modification, the discharge path P may be a path formed by a groove.

[0237] For example, the groove forming the discharge path P may be formed on the surface of the dielectric layer 20 between the plurality of dielectric layers 20 constituting the first main surface side outer layer portion 12. Specifically, Fig. 15B As shown, a groove forming the discharge path P may be formed on the surface of the first dielectric layer 20A. Similarly, a groove forming the discharge path P may be formed on the surface of the second dielectric layer 20B. In addition, a groove forming the discharge path P may be formed on the surface of only one of the first dielectric layer 20A and the second dielectric layer 20B.

[0238] The groove forming the discharge path P includes, for example, a first lead-out region PE1 led to the first external electrode 40A, a second lead-out region PE2 led to the second external electrode 40B, and a discharge lead-out region PD led to the exposed surface of the stacked body 10. Fig. 15B In the illustrated example, the first lead-out area PE1 is led out to the first end surface LS1 , the second lead-out area PE2 is led out to the second end surface LS2 , and the discharge lead-out area PD is led out to the first side surface WS1 and the second side surface WS2 .

[0239] The discharge lead-out region PD led out to the exposed surface of the stacked body 10 forms an opening H on the exposed surface of the stacked body 10. Fig.15A, an area of ​​the opening portion H of the first main surface side outer layer portion 12 arranged on the first main surface TS1 side is shown. The opening portion H is preferably arranged on at least one of the first side surface WS1 and the second side surface WS2, for example. In the present embodiment, the opening portion H is formed on both the first side surface WS1 and the second side surface WS2. In addition, the groove forming the discharge path P is arranged in at least one of the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13 of the stack 10. The discharge path P can also be arranged in the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13 of the stack 10.

[0240] Through such a structure, as a discharge path P, there are also formed: a path connecting the first end face LS1 where the first external electrode 40A is arranged to the opening portion H arranged on the surface of the stack 10 exposed from the external electrode 40; and a path connecting the second end face LS2 where the second external electrode 40B is arranged to the opening portion H arranged on the surface of the stack 10 exposed from the external electrode 40.

[0241] In addition, the path connecting the first end surface LS1 on which the first external electrode 40A is arranged to the opening portion H on the surface of the stack 10 exposed from the external electrode 40, and the path connecting the second end surface LS2 on which the second external electrode 40B is arranged to the opening portion H on the surface of the stack 10 exposed from the external electrode 40, can be formed as a common path or as separate paths as shown in the above-mentioned embodiment.

[0242] Next, a method for manufacturing the multilayer ceramic capacitor 1 according to the present embodiment will be described. Fig.16 is with Fig. 11B The corresponding drawings are diagrams for explaining the division of regions of the stacked body 10 .

[0243] A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. The conductive paste for the dielectric sheet and the internal electrode contains a binder and a solvent. The binder and the solvent may be known binders and solvents. The paste containing the conductive material is, for example, a paste in which an organic binder and an organic solvent are added to metal powder.

[0244] On the dielectric sheet, a conductive paste for the internal electrode layer 30 is printed in a given pattern by, for example, screen printing, gravure printing, etc. Specifically, a paste containing a conductive material is applied to the dielectric sheet by the above-mentioned printing method or the like, thereby forming a conductive paste layer. Thus, a dielectric sheet having a pattern of the first internal electrode layer 31 formed thereon and a dielectric sheet having a pattern of the second internal electrode layer 32 formed thereon are prepared. In addition, as dielectric sheets for the first main surface side outer layer portion and the second main surface side outer layer portion, a dielectric sheet having no pattern of the internal electrode layer formed thereon is also prepared.

[0245] A portion of the portion to be the first main surface side outer layer portion 12 is formed by stacking a predetermined number of dielectric sheets on which the pattern of the internal electrode layer is not formed. Specifically, the portion to be the first main surface side outer layer portion 12 is formed except for the portion to be Fig.16 The portion other than the portion of the first main surface side region 10B shown. The portion that becomes the inner layer portion 11 is formed by alternately stacking dielectric sheets having a pattern of the first internal electrode layer 31 and dielectric sheets having a pattern of the second internal electrode layer 32 thereon. A portion that becomes the second main surface side outer layer portion 13 is formed by stacking a predetermined number of dielectric sheets having a pattern of the internal electrode layer not printed thereon. Specifically, the portion that becomes the second main surface side outer layer portion 13 is formed except for the portion that becomes the Fig.16 The portion other than the portion of the second main surface side region 10C shown in FIG. Fig.16 The laminate sheet body of a portion of the main body region 10A of the laminate 10 shown in FIG.

[0246] The laminated sheet body is pressed in the stacking direction by isostatic pressing or other means, thereby producing a laminated block body that is a portion of the main body region 10A of the laminated body 10. Here, during the pressing, a transfer plate having a concave-convex pattern on the surface is pressed against a portion of the laminated block body where a concave portion is to be formed, thereby forming a concave portion in the laminated block body. Here, the desired concave portion described in the embodiment can be formed by controlling the shape, size, depth, density, etc. of the concave-convex pattern provided on the transfer plate.

[0247] The stacked block body is cut into a given size to thereby cut out the stacked small pieces. At this time, the corners and ridges of the stacked small pieces may be rounded by barrel grinding or the like.

[0248] Here, by stacking a plurality of dielectric sheets on which the internal electrode layer pattern is not formed, the portion to be the first main surface side outer layer portion 12 is formed into a Fig.16 The laminated sheet of the first main surface side region 10B shown in FIG. 1 is used as the first main surface side laminated sheet. Similarly, by laminating a plurality of dielectric sheets without forming a pattern of an internal electrode layer, the portion that becomes the second main surface side outer layer portion 13 is made into Fig.16 The laminated sheet of the portion of the second main surface side region 10C shown is referred to as the second main surface side laminated sheet.

[0249] The first main surface side laminated sheet and the second main surface side laminated sheet are pressed in the stacking direction by means of isostatic pressing or the like, thereby producing a first main surface side laminated block that is a part of the first main surface side region 10B and a second main surface side laminated block that is a part of the second main surface side region 10C. Here, during the pressing, a transfer plate having a concave-convex pattern on the surface is pressed against the part of the first main surface side laminated block and the second main surface side laminated block where the concave portion is to be formed, thereby forming a concave portion in the first main surface laminated block and the second main surface laminated block. Here, by controlling the shape, size, depth, density, etc. of the concave-convex pattern provided on the transfer plate, the desired concave portion described in the embodiment can be formed.

[0250] The first main surface side stacking block and the second main surface side stacking block are cut out to the same size as the stacking small piece body. The cut out first main surface side stacking blocks are arranged in a row, and the stacking small piece body before firing is arranged on top of them. Furthermore, the cut out second main surface side stacking blocks are arranged on top of them.

[0251] In this state, the stacked small pieces including the stacked small piece body, the first main surface side stacked block, and the second main surface side stacked block are subjected to temporary compression and pressing at a pressure that can maintain a plurality of cavities, thereby producing a stacked small piece having a discharge path formed by a plurality of cavities. The heat treatment temperature at this time is preferably 60° C. or higher and 100° C. or lower.

[0252] Then, a conductive paste for the base electrode layer containing a metal component, a ceramic component, a solvent, a dispersant, etc. is applied to the first end face and the second end face of the stacked small piece by a dipping method, a screen printing method, or the like. In addition, in the conductive paste of the present embodiment, Ni is used as a metal component, and BaTiO3 is used as a ceramic component. In addition, in the present embodiment, the conductive paste for the base electrode layer is applied so as to extend from the first end face and the second end face of the stacked small piece and cover a portion of each of the first main surface, the second main surface, the first side surface, and the second side surface.

[0253] The laminated small pieces having the internal electrode layer and the dielectric layer and the conductive paste for the base electrode layer applied to the laminated small pieces are simultaneously fired to produce a laminated body having the base electrode layer formed thereon. The firing temperature is preferably 900° C. or higher and 1400° C. or lower.

[0254] Then, a plating layer is formed on the surface of the base electrode layer. The plating layer, for example, includes at least one selected from Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc. More preferably, the plating layer includes at least one of Cu, Ni, and Sn. Alternatively, the plating layer includes multiple types of Cu, Ni, and Sn. In this embodiment, for example, on the base electrode layer, the plating layer is formed in the order of Cu plating, Ni plating, and Sn plating.

[0255] The completed multilayer ceramic capacitor 1 is placed in a furnace and heat treated at 150° C. for 1 hour. The atmosphere in the furnace at this time is not particularly limited. By performing such a heat treatment, hydrogen atoms accumulated in the internal electrode layer 30 and the external electrode 40 can be bonded to hydrogen molecules, and the bonded hydrogen molecules can be released to the outside of the multilayer ceramic capacitor 1 through the discharge path P.

[0256] Through such manufacturing steps, the multilayer ceramic capacitor 1 is manufactured.

[0257] The structure of the multilayer ceramic capacitor 1 is not limited to Figure 1 to Figure 4 For example, the multilayer ceramic capacitor 1 may also be as follows Fig.17 , Fig.18 , Fig.19 The following are the multilayer ceramic capacitors with two-cell structure, three-cell structure, and four-cell structure.

[0258] Fig.17 The illustrated multilayer ceramic capacitor 1 is a duplex structure multilayer ceramic capacitor 1 and includes, as the internal electrode layer 30 , a floating internal electrode layer 35 that is not extended to either the first end surface LS1 or the second end surface LS2 in addition to the first internal electrode layer 33 and the second internal electrode layer 34 . Fig.18 The illustrated multilayer ceramic capacitor 1 is a multilayer ceramic capacitor 1 of a triple structure, and includes a first floating internal electrode layer 35A and a second floating internal electrode layer 35B as the floating internal electrode layer 35 . Fig.19 The illustrated multilayer ceramic capacitor 1 is a multilayer ceramic capacitor 1 of a quadruple structure, that is, as a floating internal electrode layer 35, it has a first floating internal electrode layer 35A, a second floating internal electrode layer 35B, and a third floating internal electrode layer 35C. In this way, by providing the floating internal electrode layer 35 as the internal electrode layer 30, the multilayer ceramic capacitor 1 has a structure in which the opposing electrode portion is divided into a plurality of parts. As a result, a plurality of capacitor components are formed between the opposing internal electrode layers 30, and these capacitor components have a structure connected in series. Therefore, the voltage applied to each capacitor component becomes lower, and the multilayer ceramic capacitor 1 can be made to have a high withstand voltage. In addition, it is self-evident that the multilayer ceramic capacitor 1 of this embodiment can also be a multi-connection structure of four or more.

[0259] According to the multilayer ceramic capacitor 1 of the present embodiment, the following effects are achieved.

[0260] (1) The laminated ceramic capacitor 1 of the present embodiment comprises: a laminate 10 having a plurality of laminated dielectric layers 20 and a plurality of internal electrode layers 30 laminated on the dielectric layers 20, and having a first main surface TS1 and a second main surface TS2 opposite to each other in a lamination direction, a first end surface LS1 and a second end surface LS2 opposite to each other in a length direction perpendicular to the lamination direction, and a first side surface WS1 and a second side surface WS2 opposite to each other in a width direction perpendicular to the lamination direction and the length direction; and an external electrode 40 connected to the internal electrode layer 30, the laminate 10 comprising: an inner layer portion 11 including, in the lamination direction, an internal electrode layer 30 located closest to the first main surface TS1 among the plurality of internal electrode layers 30 to an internal electrode layer located closest to the first main surface TS1 among the plurality of internal electrode layers 30 The internal electrode layer 30 closest to the second main surface TS2 side is disposed so as to face each other with the dielectric layer 20 interposed therebetween; the first main surface side outer layer portion 12 is formed of the plurality of dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1 among the plurality of internal electrode layers 30; and the second main surface side outer layer portion 13 is formed of the plurality of dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2 among the plurality of internal electrode layers 30, and at least one of the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13 is provided with a discharge path P formed along a plane orthogonal to the stacking direction and capable of discharging elements to the outside of the stacked body 10. Thus, even when hydrogen is stored in the internal electrode layer 30, the hydrogen stored in the internal electrode layer 30 can be discharged to the outside of the multilayer ceramic capacitor 1 through the discharge path P. Therefore, the amount of hydrogen contained in the internal electrode layer 30 can be reduced, and the diffusion of hydrogen into the dielectric layer 20 can be reduced. As a result, degradation of the insulation resistance of the multilayer ceramic capacitor 1 can be suppressed.

[0261] (2) The discharge path P of the multilayer ceramic capacitor 1 of the present embodiment is a path connecting the surface of the multilayer body 10 covered by the external electrode 40 and the surface of the multilayer body 10 exposed from the external electrode 40. Thus, hydrogen stored in the internal electrode layer 30 can be discharged to the outside of the multilayer ceramic capacitor 1 more efficiently through the discharge path P.

[0262] (3) The discharge path P of the multilayer ceramic capacitor 1 of the present embodiment includes a plurality of cavities 80 arranged in a plane. Thus, the discharge path P for discharging hydrogen stored in the internal electrode layer 30 to the outside of the multilayer ceramic capacitor 1 can be formed.

[0263] (4) The cavity 80 forming the discharge path P of the multilayer ceramic capacitor 1 of the present embodiment has a spherical curved surface. This reduces the resistance of the fluid when it passes through the discharge path P.

[0264] (5) In the multilayer ceramic capacitor 1 of the present embodiment, the height in the stacking direction of the cavity 80 forming the discharge path P is 0.1 μm or more and 1 μm or less. Thus, the discharge path P can be easily formed.

[0265] (6) The external electrodes 40 of the multilayer ceramic capacitor 1 of the present embodiment include the first external electrode 40A disposed on the first end surface LS1 and the second external electrode 40B disposed on the second end surface LS2. The effects of the present disclosure can also be obtained in the multilayer ceramic capacitor 1 having such a structure.

[0266] (7) The plurality of internal electrode layers 30 of the multilayer ceramic capacitor 1 of the present embodiment include a plurality of first internal electrode layers 31 led to the first end surface LS1 and a plurality of second internal electrode layers 32 led to the second end surface LS2, the first external electrodes 40A are connected to the first internal electrode layers 31, and the second external electrodes 40B are connected to the second internal electrode layers 32. Even in such a multilayer ceramic capacitor 1, the effects of the present disclosure can be obtained.

[0267] (9) The discharge path P of the multilayer ceramic capacitor 1 of the present embodiment includes: a path connecting the first end surface LS1 where the first external electrode 40A is arranged to the opening H arranged on the surface of the multilayer body 10 exposed from the external electrode 40; and a path connecting the second end surface LS2 where the second external electrode 40B is arranged to the opening H arranged on the surface of the multilayer body 10 exposed from the external electrode 40. Thus, hydrogen stored in the internal electrode layer 30 can be discharged to the outside of the multilayer ceramic capacitor 1 more efficiently through the discharge path P.

[0268] (10) The opening H of the multilayer ceramic capacitor 1 of the present embodiment is arranged on at least one of the first side surface WS1 and the second side surface WS2 and is arranged at the same position in the stacking direction as the plane where the discharge path P is formed. Thus, the discharge path P can be easily formed.

[0269] (11) The opening H of the multilayer ceramic capacitor 1 of the present embodiment is disposed on either the first main surface TS1 or the second main surface TS2 . This allows hydrogen stored in the internal electrode layer 30 to be discharged to the outside of the multilayer ceramic capacitor 1 more efficiently through the discharge path P.

[0270] (12) The first external electrode 40A of the multilayer ceramic capacitor 1 of the present embodiment includes the first base electrode layer 50A disposed on the first end surface LS1 and the first plating layer 60A disposed on the first base electrode layer 50A, and the second external electrode 40B includes the second base electrode layer 50B disposed on the second end surface LS2 and the second plating layer 60B disposed on the second base electrode layer 50B. Even in such a multilayer ceramic capacitor 1, the effects of the present disclosure can be obtained.

[0271] (13) In the multilayer ceramic capacitor 1 of the present embodiment, the first base electrode layer 50A is arranged on the first end surface LS1, a part of the first main surface TS1, a part of the second main surface TS2, a part of the first side surface WS1, and a part of the second side surface WS2; the second base electrode layer 50B is arranged on the second end surface LS2, a part of the first main surface TS1, a part of the second main surface TS2, a part of the first side surface WS1, and a part of the second side surface WS2; the first plating layer 60A is arranged on the first base electrode layer 50A, and the second plating layer 60B is arranged on the second base electrode layer 50B. Even in such a multilayer ceramic capacitor 1, the effects of the present disclosure can be obtained.

[0272] (14) The first foundation electrode layer 50A and the second foundation electrode layer 50B of the multilayer ceramic capacitor 1 of the present embodiment include a metal component and a dielectric material. Even in such a multilayer ceramic capacitor 1, the effects of the present disclosure can be obtained.

[0273] (15) The first plating layer 60A and the second plating layer 60B of the multilayer ceramic capacitor 1 of the present embodiment include at least one of Cu, Ni, and Sn. Even in such a multilayer ceramic capacitor 1, the effects of the present disclosure can be obtained.

[0274] (16) The first plated layer 60A of the multilayer ceramic capacitor 1 of the present embodiment includes a first Cu plated layer 63A disposed on the first base electrode layer 50A, a first Ni plated layer 61A disposed on the first Cu plated layer 63A, and a first Sn plated layer 62A disposed on the first Ni plated layer 61A, and the second plated layer 60B includes a second Cu plated layer 63B disposed on the second base electrode layer 50B, a second Ni plated layer 61B disposed on the second Cu plated layer 63B, and a second Sn plated layer 62B disposed on the second Ni plated layer 61B. Even in such a multilayer ceramic capacitor 1, the effects of the present disclosure can be obtained.

[0275] (17) The first plated layer 60A of the multilayer ceramic capacitor 1 of the present embodiment includes a first Ni plated layer 61A disposed on the first base electrode layer 50A and a first Sn plated layer 62A disposed on the first Ni plated layer 61A, and the second plated layer 60B includes a second Ni plated layer 61B disposed on the second base electrode layer 50B and a second Sn plated layer 62B disposed on the second Ni plated layer 61B. Even in such a multilayer ceramic capacitor 1, the effects of the present disclosure can be obtained.

[0276] (18) The first plated layer 60A of the multilayer ceramic capacitor 1 of the present embodiment includes the first Sn plated layer 62A disposed on the first base electrode layer 50A, and the second plated layer 60B includes the second Sn plated layer 62B disposed on the second base electrode layer 50B. Even in such a multilayer ceramic capacitor 1, the effects of the present disclosure can be obtained.

[0277] (19) The first external electrode 40A of the multilayer ceramic capacitor 1 of the present embodiment has the first plated layer 60A directly disposed on the first end surface LS1, and the second external electrode 40B has the second plated layer 60B directly disposed on the second end surface LS2. Even in such a multilayer ceramic capacitor 1, the effects of the present disclosure can be obtained.

[0278] (20) The first plated layer 60A of the multilayer ceramic capacitor 1 of the present embodiment includes a first Ni plated layer 61A disposed on the first end surface LS1 and a first Sn plated layer 62A disposed on the first Ni plated layer 61A, and the second plated layer 60B includes a second Ni plated layer 61B disposed on the second end surface LS2 and a second Sn plated layer 62B disposed on the second Ni plated layer 61B. Even in such a multilayer ceramic capacitor 1, the effects of the present disclosure can be obtained.

[0279] (21) The discharge path P of the multilayer ceramic capacitor 1 of the present embodiment is disposed in the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13. Thus, hydrogen stored in the internal electrode layer 30 can be discharged to the outside of the multilayer ceramic capacitor 1 more efficiently through the discharge path P.

[0280] <Second embodiment>

[0281] Hereinafter, a multilayer ceramic capacitor 1 according to a second embodiment will be described. In the following description, detailed descriptions of the same structures as those of the first embodiment will be omitted. Fig. 20 It is a perspective view of the appearance of the multilayer ceramic capacitor 1 according to the present embodiment. Fig.21 is a LW cross-sectional view showing the first internal electrode layer 131 of the multilayer ceramic capacitor 1 of the present embodiment, and is similar to Figure 4 The corresponding figure. Fig. 221 is a cross-sectional view taken along a line LW showing the second internal electrode layer 132 of the multilayer ceramic capacitor 1 according to the present embodiment. Fig.23 is a cross-sectional view taken along a plane where a discharge path is formed in the multilayer ceramic capacitor 1 of the present embodiment, and is similar to Figure 7 The corresponding figure.

[0282] The multilayer ceramic capacitor 1 of the present embodiment is different from the first embodiment in the form of the internal electrode layers and the external electrodes 40 in the laminated body 10 .

[0283] The plurality of internal electrode layers include a plurality of first internal electrode layers 131 led to the first end surface LS1 and the second end surface LS2 and a plurality of second internal electrode layers 132 led to the first side surface WS1 and the second side surface WS2. The plurality of first internal electrode layers 131 are arranged on the plurality of dielectric layers 20. The plurality of second internal electrode layers 132 are arranged on the plurality of dielectric layers 20. The plurality of first internal electrode layers 131 and the plurality of second internal electrode layers 132 are alternately arranged across the dielectric layers 20 in the stacking direction T of the stack 10. The first internal electrode layers 131 and the second internal electrode layers 132 are arranged to sandwich the dielectric layers 20.

[0284] The first internal electrode layer 131 is arranged on the dielectric layer 20, extending from the first end surface LS1 to the second end surface LS2, so as to be exposed on the first end surface LS1 and the second end surface LS2. More specifically, the first internal electrode layer 131 has a first opposing portion 131A opposed to the second internal electrode layer 132, a first lead portion 131B led from the first opposing portion 131A to the first end surface LS1, and a second lead portion 131C led from the first opposing portion 131A to the second end surface LS2. The first opposing portion 131A is located at the center of the dielectric layer 20. The first lead portion 131B is exposed on the first end surface LS1. The second lead portion 131C is exposed on the second end surface LS2. The first internal electrode layer 131 is not exposed on the first side surface WS1 and the second side surface WS2. The shapes of the first opposing portion 131A, the first lead portion 131B, and the second lead portion 131C of the first internal electrode layer 131 are not particularly limited.

[0285] The second internal electrode layer 132 is arranged on the dielectric layer 20, and is arranged to be exposed not on the first end surface LS1 and the second end surface LS2 but on the first side surface WS1 and the second side surface WS2. Specifically, the second internal electrode layer 132 extends across the first side surface WS1 and the second side surface WS2. More specifically, the second internal electrode layer 132 has a second opposing portion 132A opposed to the first internal electrode layer 131, a third lead portion 132B led out from the second opposing portion 132A to the first side surface WS1, and a fourth lead portion 132C led out from the second opposing portion 132A to the second side surface WS2. The second opposing portion 132A is located in the central portion on the dielectric layer 20. The second opposing portion 132A is formed in a rectangular shape so as to extend in the direction of the first end surface LS1 and the direction of the second end surface LS2. The third lead portion 132B is exposed on the first side surface WS1. The fourth lead portion 132C is exposed on the second side surface WS2. The second internal electrode layer 132 is not exposed at the first end surface LS1 and the second end surface LS2. The shapes of the second opposing portion 132A, the third lead portion 132B, and the fourth lead portion 132C of the second internal electrode layer 132 are not particularly limited.

[0286] In the present embodiment, the first opposing portion 131A and the second opposing portion 132A are opposed to each other via the dielectric layer 20 , thereby forming capacitance and exhibiting capacitor characteristics.

[0287] The external electrode 40 includes a first external electrode 40A, a second external electrode 40B, a third external electrode 40C, and a fourth external electrode 40D.

[0288] The first external electrode 40A is disposed on the first end surface LS1 and connected to the first internal electrode layer 131. More specifically, the first external electrode 40A is connected to the first lead portion 131B of the first internal electrode layer 131. In the present embodiment, the first external electrode 40A is formed to extend from the first end surface LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2 and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0289] The second external electrode 40B is arranged on the second end surface LS2 and connected to the first internal electrode layer 131. In more detail, the second external electrode 40B is connected to the second lead portion 131C of the first internal electrode layer 131. In the present embodiment, the second external electrode 40B is formed to extend from the second end surface LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2 and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0290] The third external electrode 40C is arranged on the first side surface WS1 and is connected to the second internal electrode layer 132. In more detail, the third external electrode 40C is connected to the third lead portion 132B of the second internal electrode layer 132. In the present embodiment, the third external electrode 40C is arranged to extend from the first side surface WS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2.

[0291] The fourth external electrode 40D is arranged on the second side surface WS2 and is connected to the second internal electrode layer 132. In more detail, the fourth external electrode 40D is connected to the fourth lead portion 132C of the second internal electrode layer 132. In the present embodiment, the fourth external electrode 40D is arranged to extend from the second side surface WS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2.

[0292] In addition, as the layer structure of the external electrode 40 of the present embodiment, for example, various layer structures similar to the external electrode 40 of the first embodiment can be adopted.

[0293] For example, the first external electrode 40A may include a first base electrode layer 50A and a first plating layer 60A, and the first plating layer 60A may include a first Ni plating layer 61A and a first Sn plating layer 62A. The second external electrode 40B may include a second base electrode layer 50B and a second plating layer 60B, and the second plating layer 60B may include a second Ni plating layer 61B and a second Sn plating layer 62B. The third external electrode 40C may include a third base electrode layer 50C and a third plating layer 60C, and the third plating layer 60C may include a third Ni plating layer 61C and a third Sn plating layer 62C. The fourth external electrode 40D may include a fourth base electrode layer 50D and a fourth plating layer 60D, and the fourth plating layer 60D may include a fourth Ni plating layer 61D and a fourth Sn plating layer 62D. The first foundation electrode layer 50A, the second foundation electrode layer 50B, the third foundation electrode layer 50C, and the fourth foundation electrode layer 50D may be, for example, sintered layers.

[0294] The multilayer ceramic capacitor 1 of the present embodiment has a discharge path P that can discharge elements to the outside of the multilayer body 10 , similarly to the first embodiment.

[0295] The discharge path P is arranged in at least one of the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13 of the laminate 10 , similarly to the first embodiment. In the present embodiment, the discharge path P is arranged in the first main surface side outer layer portion 12 .

[0296] The discharge path P includes: a path connecting from the first end surface LS1 where the first external electrode 40A is arranged to the opening portion H arranged on the surface of the stacked body 10 exposed from the external electrode 40; and a path connecting from the second end surface LS2 where the second external electrode 40B is arranged to the opening portion H arranged on the surface of the stacked body 10 exposed from the external electrode 40. The discharge path P preferably further includes: a path connecting from the first side surface WS1 where the third external electrode 40C is arranged to the opening portion H arranged on the surface of the stacked body 10 exposed from the external electrode 40; and a path connecting from the second side surface WS2 where the fourth external electrode 40D is arranged to the opening portion H arranged on the surface of the stacked body 10 exposed from the external electrode 40.

[0297] The opening H is preferably disposed on, for example, at least one of the first side surface WS1 and the second side surface WS2 . In the present embodiment, the opening H is formed on the first side surface WS1 and the second side surface WS2 .

[0298] exist Fig. 20 , the region of the opening H arranged on the second side surface WS2 is shown. The opening H is arranged on the surface of the stacked body 10 exposed from the first external electrode 40A, the second external electrode 40B, the third external electrode 40C, and the fourth external electrode 40D. That is, the opening H is arranged on the exposed surface of the stacked body 10. In the present embodiment, the opening H is arranged on the first side surface WS1 and the second side surface WS2 at a position in the stacking direction T that is the same as the plane in which the discharge path P is formed. In the present embodiment, the opening H is formed as a portion continuous from the planar discharge path P.

[0299] In the present embodiment, the plurality of cavities 80 forming the discharge path P are arranged between the plurality of dielectric layers 20 constituting the first main surface side outer layer portion 12, on the entire surface of the dielectric layer 20, that is, on the entire surface of the plane perpendicular to the stacking direction T. Specifically, Fig.23 As shown, the concave portion 80 forming the discharge path P is arranged on the entire surface of the first dielectric layer 20A. That is, the discharge path P is formed substantially on the entire surface of the plane perpendicular to the stacking direction T of the first dielectric layer 20A.

[0300] As described above, the plurality of cavities 80 are preferably arranged at least over the entire surface of the dielectric layer 20 forming either the first main surface side outer layer portion 12 or the second main surface side outer layer portion 13. This can increase the total area of ​​the path through which the fluid passes.

[0301] Hereinafter, a first modified example of the multilayer ceramic capacitor 1 of the present embodiment will be described. In the following description, the same reference numerals are used for the same structures as those of the above-described embodiment, and detailed description thereof will be omitted. Fig.24is a perspective view of the appearance of a multilayer ceramic capacitor 1 according to a first modified example of the present embodiment. Fig. 20 The corresponding figure.

[0302] In this modification, the discharge path P is arranged in the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13 of the stacked body 10. The second main surface side outer layer portion 13 is provided with the same discharge path P as that arranged in the first main surface side outer layer portion 12. Fig.23 The discharge path P is shown.

[0303] On the first side surface WS1 and the second side surface WS2, an opening H similar to the opening H arranged in the first main surface side outer layer portion 12 is arranged in the second main surface side outer layer portion 13. Fig.24 , the region of the opening H of the second principal surface side outer layer portion 13 arranged on the second principal surface TS2 side is shown together with the region of the opening H of the first principal surface side outer layer portion 12 arranged on the first principal surface TS1 side.

[0304] As described above, the discharge path P is preferably arranged on the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13. In other words, the discharge path P is preferably arranged on both sides of the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13. Thus, it is possible to discharge hydrogen stored in the internal electrode layer 30 to the outside of the multilayer ceramic capacitor 1 from the discharge path P arranged on both sides of the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13, not just on one side. In addition, even when the plurality of cavities 80 forming the discharge path P are provided on both sides of the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13, the plurality of cavities 80 are preferably arranged on the entire surface of the first main surface side outer layer portion 12 and the entire surface of the second main surface side outer layer portion 13.

[0305] Hereinafter, a second modification of the multilayer ceramic capacitor 1 of the present embodiment will be described. In the following description, the same reference numerals are given to the same structures as those of the above-described embodiment, and detailed descriptions thereof will be omitted. Fig.25A is a perspective view of the appearance of a multilayer ceramic capacitor 1 according to a second modified example of the present embodiment. Fig. 20 The corresponding figure. Fig.25B is a cross-sectional view taken along a plane where a discharge path is formed in a multilayer ceramic capacitor 1 according to a second modification of the present embodiment, and is similar to FIG. Fig.23 The corresponding figure.

[0306] The discharge path P is not limited to being formed by the plurality of cavities 80 arranged on the entire surface of the dielectric layer 20. As shown in this modification, the region where the plurality of cavities 80 forming the discharge path P are arranged may be a specific region.

[0307] For example, the plurality of cavities 80 forming the discharge path P may be arranged between the plurality of dielectric layers 20 constituting the first main surface side outer layer portion 12 or on the surface of the dielectric layer 20. Fig.25B The area shown.

[0308] The area for configuring the concave portion 80 that becomes the cavity forming the discharge path P includes, for example, a first lead-out area PE1 led to the first external electrode 40A, a second lead-out area PE2 led to the second external electrode 40B, a third lead-out area PE3 led to the third external electrode 40C, a fourth lead-out area PE4 led to the fourth external electrode 40D, and a discharge lead-out area PD led to the exposed surface of the stack 10. Fig.25B In the example shown, the first lead-out area PE1 is led out to the first end surface LS1, the second lead-out area PE2 is led out to the second end surface LS2, the third lead-out area PE3 is led out to the first side surface WS1, the fourth lead-out area PE4 is led out to the second side surface WS2, and the lead-out area PD for discharge is led out to the first side surface WS1 and the second side surface WS2. In addition, the lead-out area PD for discharge is led out to the area between the first external electrode 40A and the third external electrode 40C, and the area between the second external electrode 40B and the third external electrode 40C in the first side surface WS1. Furthermore, the lead-out area PD for discharge is led out to the area between the first external electrode 40A and the fourth external electrode 40D, and the area between the second external electrode 40B and the fourth external electrode 40D in the second side surface WS2.

[0309] The discharge lead-out region PD led out to the exposed surface of the stacked body 10 forms an opening H on the exposed surface of the stacked body 10. Fig.25A , the region of the opening H of the first main surface side outer layer portion 12 arranged on the first main surface TS1 side is shown. The opening H is preferably arranged on at least one of the first side surface WS1 and the second side surface WS2. In the present embodiment, the opening H is formed on both the first side surface WS1 and the second side surface WS2.

[0310] With such a structure, as the discharge path P, a path connecting from the first end surface LS1 where the first external electrode 40A is arranged to the opening H arranged on the surface of the stacked body 10 exposed from the external electrode 40, and a path connecting from the second end surface LS2 where the second external electrode 40B is arranged to the opening H arranged on the surface of the stacked body 10 exposed from the external electrode 40 are formed. Furthermore, as the discharge path P, a path connecting from the region where the first side surface WS1 of the third external electrode 40C is arranged to the opening H arranged on the surface of the stacked body 10 exposed from the external electrode 40, and a path connecting from the region where the second side surface WS2 of the fourth external electrode 40D is arranged to the opening H arranged on the surface of the stacked body 10 exposed from the external electrode 40 are formed. In addition, according to the structure of this modified example, the contact area between the first dielectric layer 20A and the second dielectric layer 20B is increased, so that the bonding force between the first dielectric layer 20A and the second dielectric layer 20B forming the discharge path P therebetween can be improved.

[0311] Hereinafter, a third modification of the multilayer ceramic capacitor 1 of the present embodiment will be described. In the following description, the same reference numerals are used for the same structures as those of the second modification of the above-described embodiment, and detailed descriptions thereof will be omitted. Fig.26 is a perspective view of the appearance of a multilayer ceramic capacitor 1 according to a third modified example of the present embodiment. Fig.25A The corresponding figure.

[0312] In this modification, the discharge path P is arranged in the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13 of the stacked body 10. The second main surface side outer layer portion 13 is provided with the same discharge path P as that arranged in the first main surface side outer layer portion 12. Fig.25B The discharge path P is shown.

[0313] On the first side surface WS1 and the second side surface WS2, an opening H similar to the opening H arranged in the first main surface side outer layer portion 12 is arranged in the second main surface side outer layer portion 13. Fig.24 , the region of the opening H of the second principal surface side outer layer portion 13 arranged on the second principal surface TS2 side is shown together with the region of the opening H of the first principal surface side outer layer portion 12 arranged on the first principal surface TS1 side.

[0314] As described above, the discharge path P is preferably disposed on the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13. In other words, the discharge path P is preferably disposed on both sides of the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13. Thus, hydrogen stored in the internal electrode layer 30 can be discharged to the outside of the multilayer ceramic capacitor 1 from the discharge path P disposed on both surfaces of the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13, rather than only on one surface.

[0315] According to the multilayer ceramic capacitor 1 of the present embodiment, in addition to the above-mentioned (1) to (7) and (9) to (21), the following effects are achieved.

[0316] (8) The plurality of internal electrode layers of the multilayer ceramic capacitor 1 of the present embodiment include a plurality of first internal electrode layers 131 led to the first end surface LS1 and the second end surface LS2 and a plurality of second internal electrode layers 132 led to the first side surface WS1 and the second side surface WS2, and the external electrode 40 includes a first external electrode 40A disposed on the first end surface LS1 and connected to the first internal electrode layer 131, a second external electrode 40B disposed on the second end surface LS2 and connected to the first internal electrode layer 131, a third external electrode 40C disposed on the first side surface WS1 and connected to the second internal electrode layer 132, and a fourth external electrode 40D disposed on the second side surface WS2 and connected to the second internal electrode layer 132. Even in a multilayer ceramic capacitor of such a structure, the effects of the present disclosure can be obtained.

[0317] The present invention is not limited to the configuration of the above-described embodiment, and can be applied with appropriate changes within the scope of the present invention. In addition, a configuration combining two or more of the preferred configurations described in the above-described embodiment is also the present invention.

Claims

1. A laminated ceramic capacitor comprising: A laminate having a plurality of laminated dielectric layers and a plurality of internal electrode layers laminated on the dielectric layers, and having a first main surface and a second main surface opposite to each other in a lamination direction, a first end surface and a second end surface opposite to each other in a length direction orthogonal to the lamination direction, and a first side surface and a second side surface opposite to each other in a width direction orthogonal to the lamination direction and the length direction; and an external electrode connected to the internal electrode layer, The laminated body has: an inner layer portion including, in the stacking direction, from the inner electrode layer located closest to the first main surface among the plurality of inner electrode layers to the inner electrode layer located closest to the second main surface among the plurality of inner electrode layers, and the plurality of inner electrode layers are arranged to face each other with the dielectric layer interposed therebetween; The first main surface side outer layer portion is formed by a plurality of dielectric layers located between the first main surface and the internal electrode layer located closest to the first main surface among the plurality of internal electrode layers; and The second main surface side outer layer portion is formed by a plurality of dielectric layers located between the second main surface and the internal electrode layer located closest to the second main surface among the plurality of internal electrode layers. At least one of the first main surface side outer layer portion and the second main surface side outer layer portion is provided with a discharge path formed along a plane orthogonal to the stacking direction and capable of discharging elements to the outside of the stacked body, The discharge path is included only in the plurality of dielectric layers of at least one of the first principal surface side outer layer portion and the second principal surface side outer layer portion, and is not connected to the plurality of internal electrode layers.

2. The multilayer ceramic capacitor according to claim 1, wherein The discharge path is a path connecting a surface of the stacked body covered by the external electrode and a surface of the stacked body exposed from the external electrode.

3. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein: The discharge path includes a plurality of cavities arranged on the plane.

4. The multilayer ceramic capacitor according to claim 3, wherein: The cavity has a spherical curved surface.

5. The multilayer ceramic capacitor according to claim 3, wherein: The height of the cavity in the stacking direction is greater than or equal to 0.1 μm and less than or equal to 1 μm.

6. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein: The external electrode has: A first external electrode is disposed on the first end surface; and The second external electrode is disposed on the second end surface.

7. The multilayer ceramic capacitor according to claim 6, wherein: The plurality of internal electrode layers have: a plurality of first internal electrode layers led out to the first end surface; and A plurality of second internal electrode layers are led out to the second end surface, The first external electrode is connected to the first internal electrode layer, The second external electrode is connected to the second internal electrode layer.

8. The multilayer ceramic capacitor according to claim 6, wherein: The plurality of internal electrode layers have: a plurality of first internal electrode layers, led out to the first end surface and the second end surface; and A plurality of second internal electrode layers are led out to the first side surface and the second side surface, The external electrode has: The first external electrode is disposed on the first end surface and connected to the first internal electrode layer; The second external electrode is disposed on the second end surface and connected to the first internal electrode layer; A third external electrode is disposed on the first side surface and connected to the second internal electrode layer; and The fourth external electrode is disposed on the second side surface and connected to the second internal electrode layer.

9. The multilayer ceramic capacitor according to claim 6, wherein: The discharge path comprises: a path connecting the first end surface where the first external electrode is arranged to an opening portion arranged on a surface of the laminate exposed from the external electrode; and A path connecting the second end surface where the second external electrode is arranged to the opening portion arranged on the surface of the stacked body exposed from the external electrode.

10. The multilayer ceramic capacitor according to claim 9, wherein The opening is arranged on at least one of the first side surface and the second side surface, and is arranged at the same position in the stacking direction as a plane on which the discharge path is formed.

11. The multilayer ceramic capacitor according to claim 9, wherein The opening is arranged on either the first main surface or the second main surface.

12. The multilayer ceramic capacitor according to claim 6, wherein: The first external electrode has: A first substrate electrode layer is disposed on the first end surface; and A first plating layer is disposed on the first base electrode layer, The second external electrode has: A second base electrode layer is disposed on the second end surface; and The second plating layer is disposed on the second base electrode layer.

13. The multilayer ceramic capacitor according to claim 12, wherein: The first base electrode layer is disposed on the first end surface, a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the second side surface. The second base electrode layer is disposed on the second end surface, a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the second side surface. The first plating layer is arranged on the first base electrode layer, The second plating layer is disposed on the second base electrode layer.

14. The multilayer ceramic capacitor according to claim 12 or claim 13, wherein: The first base electrode layer and the second base electrode layer include a metal component and a dielectric material.

15. The multilayer ceramic capacitor according to claim 12 or claim 13, wherein: The first plating layer and the second plating layer include at least one of Cu, Ni, and Sn.

16. The multilayer ceramic capacitor according to claim 15, wherein The first plating layer comprises: a first Cu plating layer, disposed on the first base electrode layer; a first Ni plating layer disposed on the first Cu plating layer; and a first Sn plating layer, disposed on the first Ni plating layer, The second plating layer comprises: a second Cu plating layer, disposed on the second base electrode layer; a second Ni plating layer disposed on the second Cu plating layer; and The second Sn plating layer is disposed on the second Ni plating layer.

17. The multilayer ceramic capacitor according to claim 15, wherein: The first plating layer comprises: A first Ni plating layer is disposed on the first base electrode layer; and a first Sn plating layer, disposed on the first Ni plating layer, The second plating layer comprises: a second Ni plating layer, disposed on the second base electrode layer; and The second Sn plating layer is disposed on the second Ni plating layer.

18. The multilayer ceramic capacitor according to claim 15, wherein: The first plating layer includes a first Sn plating layer disposed on the first base electrode layer, The second plating layer includes a second Sn plating layer disposed on the second base electrode layer.

19. The multilayer ceramic capacitor according to claim 6, wherein: The first external electrode has a first plating layer directly disposed on the first end surface, The second external electrode has a second plating layer disposed directly on the second end surface.

20. The multilayer ceramic capacitor according to claim 19, wherein The first plating layer comprises: A first Ni plating layer is disposed on the first end surface; and a first Sn plating layer, disposed on the first Ni plating layer, The second plating layer comprises: A second Ni plating layer is disposed on the second end surface; and The second Sn plating layer is disposed on the second Ni plating layer.

21. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein: The discharge path is arranged in the first main surface side outer layer portion and the second main surface side outer layer portion.

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