Semiconductor structure and methods for forming semiconductor structures

Abstract

A semiconductor structure and a method for forming the same, the structure comprising: a substrate; a first dielectric layer on the substrate, the first dielectric layer having a plurality of conductive structures therein, the first dielectric layer exposing the surfaces of the conductive structures; a stop layer on the conductive structures and on the first dielectric layer, the stop layer having a second opening therein, the second opening exposing a portion of the conductive structure surfaces; a second dielectric layer on the stop layer, the second dielectric layer having a first opening therein, the top of the second opening communicating with the bottom of the first opening; an adhesive layer on the sidewall surface of the first opening; and an electrical connection layer located within the first opening and the second opening. The performance of the semiconductor structure is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the semiconductor structure. Background Technology

[0002] Metal interconnect structures are indispensable in semiconductor devices, used to interconnect active regions, transistors, or different layers of metal lines to achieve signal transmission and control. Therefore, the formation of metal interconnect structures has a significant impact on the performance and manufacturing cost of semiconductor devices during semiconductor manufacturing. To increase device density, the size of semiconductor devices in integrated circuits has been continuously reduced. To achieve electrical connections between these semiconductor devices, multi-layer interconnect structures are typically required.

[0003] Generally, in the back-end interconnect process of semiconductor device manufacturing, the first conductive layer (M1) needs to form an electrical connection with the underlying active device structure (including source / drain regions and gate structure regions). Therefore, before forming the first conductive layer, it is usually necessary to pre-form the local interconnect structure of the semiconductor device. The local interconnect structure includes: a zeroth conductive layer (MO) electrically connected to the underlying source / drain regions, and a zeroth gate conductive layer (MOG) electrically connected to the gate structure.

[0004] However, the manufacturing process of semiconductor structures with local interconnect structures in the prior art is complex, and the performance of the resulting semiconductor structures needs to be further improved. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the semiconductor structure, so as to improve the performance of the semiconductor structure.

[0006] To address the aforementioned technical problems, the present invention provides a semiconductor structure comprising: a substrate, the substrate including: a base, an isolation structure located on the base, a gate structure located within the isolation structure, and source / drain doped regions, the source / drain doped regions being located within the base on both sides of the gate structure; a first dielectric layer located on the substrate, the first dielectric layer having a plurality of conductive structures, the first dielectric layer exposing the surfaces of the conductive structures, the conductive structures being electrically connected to the gate structure or the source / drain doped regions; a stop layer located on the conductive structures and on the first dielectric layer, the stop layer having a second opening, the second opening exposing a portion of the surface of the conductive structures; a second dielectric layer located on the stop layer, the second dielectric layer having a first opening, the top of the second opening communicating with the bottom of the first opening; an adhesive layer located on the sidewall surface of the first opening; and an electrical connection layer located within the first opening and the second opening.

[0007] Optionally, the material of the adhesive layer includes a metal or a metal nitride, wherein the metal includes tantalum or titanium; and the metal nitride includes tantalum nitride, titanium nitride, tungsten nitride, or tungsten carbonitride.

[0008] Optionally, the material of the electrical connection layer includes a metal, including tungsten.

[0009] Optionally, the first dielectric layer has a groove; the conductive structure includes a barrier layer located on the sidewall surface and bottom surface of the groove and a conductive layer located on the surface of the barrier layer.

[0010] Optionally, the material of the barrier layer includes a metal nitride, and the material of the conductive layer includes a metal or a metal nitride, wherein the metal nitride includes titanium nitride or tantalum nitride, and the metal includes one or more combinations of copper, aluminum, tungsten, cobalt, nickel and tantalum.

[0011] Optionally, the material of the stop layer is different from the material of the second dielectric layer.

[0012] Optionally, the material of the stop layer includes a dielectric material, which includes silicon nitride, silicon oxynitride, or silicon carbide.

[0013] Optionally, the substrate may also have a fin structure, with the gate structure spanning the fin structure.

[0014] Optionally, the thickness of the adhesive layer ranges from 15 angstroms to 30 angstroms.

[0015] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a first dielectric layer on the substrate, the first dielectric layer having a plurality of conductive structures therein, the first dielectric layer exposing the surface of the conductive structures; forming a second dielectric layer on the conductive structures and on the first dielectric layer, the second dielectric layer having a plurality of first openings therein, the first openings exposing a portion of the surface of the conductive structures; forming an adhesive layer on the sidewall surface of the first openings, the adhesive layer being made of a material containing metal elements; and forming an initial electrical connection layer in the first openings using a selective deposition process.

[0016] Optionally, the method of forming an adhesive layer on the surface of the first opening sidewall includes: forming an adhesive material layer on the surface of the first opening sidewall, the bottom surface, and the surface of the second dielectric layer; etching back the adhesive material layer until the surface of the stop layer is exposed, thereby forming an adhesive layer on the surface of the first opening sidewall.

[0017] Optionally, the process for forming the adhesive material layer includes atomic layer deposition.

[0018] Optionally, the material of the adhesive layer includes a metal or a metal nitride, wherein the metal includes tantalum or titanium; and the metal nitride includes tantalum nitride, titanium nitride, tungsten nitride, or tungsten carbonitride.

[0019] Optionally, the thickness of the adhesive layer ranges from 15 angstroms to 30 angstroms.

[0020] Optionally, before forming the second dielectric layer on the conductive structure and the first dielectric layer, the method further includes: forming a stop layer on the conductive structure and the first dielectric layer; the second dielectric layer is located on the stop layer, and the first opening exposes the surface of the stop layer on the conductive structure.

[0021] Optionally, after forming an adhesive layer on the sidewall surface of the first opening, the method further includes: removing a stop layer at the bottom of the first opening until the top surface of the conductive structure is exposed, forming a second opening communicating with the bottom of the first opening within the stop layer; and forming an initial electrical connection layer within the first opening and the second opening using a selective deposition process.

[0022] Optionally, the material of the initial electrical connection layer includes a metal, including tungsten.

[0023] Optionally, the process parameters for the selective deposition process that forms the initial electrical connection layer include: a temperature of 300°C to 400°C, and a reaction gas of a mixture of hydrogen and tungsten hexafluoride.

[0024] Optionally, the conductive structure includes a barrier layer and a conductive layer located on the surface of the barrier layer.

[0025] Optionally, the method for forming the conductive structure includes: forming a groove in a first dielectric layer, the groove exposing a portion of the substrate surface; forming a barrier layer on the sidewall surface and bottom surface of the groove; and forming a conductive layer on the surface of the barrier layer.

[0026] Optionally, the material of the barrier layer includes a metal nitride, and the material of the conductive layer includes a metal or a metal nitride, wherein the metal nitride includes titanium nitride or tantalum nitride, and the metal includes one or more combinations of copper, aluminum, tungsten, cobalt, nickel and tantalum.

[0027] Optionally, the material of the stop layer is different from the material of the second dielectric layer.

[0028] Optionally, the material of the stop layer includes a dielectric material, which includes silicon nitride, silicon oxynitride, or silicon carbide.

[0029] Optionally, after forming an initial electrical connection layer in the first opening using a selective deposition process, the method further includes: forming a buffer layer on the second dielectric layer and the initial electrical connection layer; forming a pad layer on the buffer layer; and planarizing the pad layer, buffer layer, and initial electrical connection layer until the surface of the second dielectric layer is exposed to form the electrical connection layer.

[0030] Optionally, the padding layer and the initial electrical connection layer are made of the same material.

[0031] Optionally, the process for planarizing the padding layer, buffer layer, and initial electrical connection layer includes a chemical mechanical polishing process.

[0032] Optionally, the material of the buffer layer includes a metal nitride, such as titanium nitride or tantalum nitride.

[0033] Optionally, the substrate includes: a base; a device layer on the base, the device layer including an isolation structure and a device structure located within the isolation structure, the device structure including a transistor, diode, triode, capacitor, inductor, or conductive structure; the conductive structure being electrically connected to the device structure.

[0034] Optionally, the substrate may also have a fin structure.

[0035] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0036] The technical solution of this invention involves first forming an adhesive layer on the sidewall of a first opening, and then forming an initial electrical connection layer within the first opening. When forming the initial electrical connection layer within the first opening, the adhesive layer on the sidewall of the first opening, made of a material containing metallic elements, provides good adhesion between the initial electrical connection layer and the adhesive layer. This allows the adhesive layer to fill the gap between the initial electrical connection layer and the second dielectric layer, thereby improving the overall density of the initial electrical connection layer and the second dielectric layer. Subsequently, during the planarization of the initial electrical connection layer, damage from the planarization process is reduced, thus improving the performance of the semiconductor structure.

[0037] Furthermore, the method includes: forming a stop layer on the conductive structure and the first dielectric layer, with the first opening exposing the surface of the stop layer on the conductive structure; after forming an adhesive layer, removing the stop layer at the bottom of the first opening until the top surface of the conductive structure is exposed; and forming a second opening within the stop layer that communicates with the bottom of the first opening. The adhesive layer is located only on the sidewall surface of the first opening, thereby enabling the stop layer to protect the conductive structure and reducing the damage to the conductive structure caused by the process of forming the adhesive layer and the process of removing the adhesive layer at the bottom of the first opening.

[0038] Furthermore, the material of the adhesive layer includes a metal or a metal nitride, wherein the metal includes tantalum or titanium; and the metal nitride includes tantalum nitride, titanium nitride, tungsten nitride, or tungsten carbonitride. Thus, when the initial electrical connection layer is formed within the first and second openings using a selective deposition process, the material of the initial electrical connection layer cannot grow on the surface of the adhesive layer, resulting in a dense structure from the bottom of the second opening, achieving better performance.

[0039] Furthermore, the process for forming the adhesive material layer includes atomic layer deposition (ALD). The ALD process results in a better bond between the adhesive material layer and the second dielectric layer, thereby filling the gap between the initial electrical connection layer and the second dielectric layer, which improves the overall density of the initial electrical connection layer and the second dielectric layer. Attached Figure Description

[0040] Figure 1 This is a schematic cross-sectional view of a semiconductor structure in one embodiment;

[0041] Figures 2 to 8 This is a cross-sectional schematic diagram of the semiconductor structure formation process in an embodiment of the present invention. Detailed Implementation

[0042] As described in the background section, the manufacturing process of semiconductor structures with local interconnect structures in the prior art is complex, and the performance of the resulting semiconductor structures needs further improvement. The following analysis and explanation will be provided with reference to specific embodiments.

[0043] Figure 1 This is a schematic cross-sectional view of a semiconductor structure in one embodiment.

[0044] Please refer to Figure 1 A substrate 100 is provided; a first dielectric layer 101 and a conductive structure located within the first dielectric layer 101 are formed on the substrate 100, the conductive structure including a barrier layer 103 and a conductive layer 102 located on the barrier layer 103; a stop layer 104 is formed on the first dielectric layer 101 and the conductive structure; a second dielectric layer 105 is formed on the stop layer 104; an opening (not shown) is formed within the second dielectric layer 105 and the stop layer 104; and an electrical connection layer 106 is formed within the opening.

[0045] During the formation of the semiconductor structure, the material of the electrical connection layer 106 includes tungsten. When the electrical connection layer 106 is formed using a selective deposition process, the structure of the electrical connection layer 106 formed by the selective deposition process is relatively dense, which is suitable for growth in small-sized structures. However, the electrical connection layer 106 formed by the selective deposition process has strong directionality during growth, resulting in gaps between the electrical connection layer 106 and the second dielectric layer 105 (as shown in region A in the figure). During subsequent chemical mechanical polishing, the polishing slurry will flow along the gaps to the surface of the conductive structure, causing damage to the conductive structure.

[0046] To address the aforementioned problems, the present invention provides a semiconductor structure and a method for forming the semiconductor structure. The method involves first forming an adhesive layer on the sidewall of a first opening, and then forming an initial electrical connection layer within the first opening. When forming the initial electrical connection layer within the first opening, the adhesive layer, made of a material containing metallic elements, provides good adhesion between the initial electrical connection layer and the adhesive layer. This allows the adhesive layer to fill the gap between the initial electrical connection layer and the second dielectric layer, thereby improving the overall density of the two layers. Furthermore, during subsequent planarization of the initial electrical connection layer, damage from the planarization process is reduced, thus enhancing the performance of the semiconductor structure.

[0047] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0048] Figures 2 to 8 This is a cross-sectional schematic diagram of the semiconductor structure formation process in an embodiment of the present invention.

[0049] Please refer to Figure 2 Substrate 200 is provided.

[0050] In this embodiment, the substrate 200 includes: a substrate (not shown); a device layer (not shown) located on the substrate, the device layer including an isolation structure and a device structure located within the isolation structure, the device structure including a transistor, diode, triode, capacitor, inductor or conductive structure.

[0051] In this embodiment, the substrate is made of silicon.

[0052] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0053] In this embodiment, the substrate is a planar substrate.

[0054] In other embodiments, the substrate also has a fin structure.

[0055] Please continue to refer to this. Figure 2 A first dielectric layer 201 is formed on a substrate 200. The first dielectric layer 201 has a plurality of conductive structures, and the first dielectric layer 201 exposes the surface of the conductive structures.

[0056] The conductive structure is electrically connected to the device structure.

[0057] The conductive structure includes a barrier layer 202 and a conductive layer 203 located on the surface of the barrier layer 202.

[0058] The method for forming the conductive structure includes: forming a groove (not shown) in a first dielectric layer 201, the groove exposing a portion of the device structure surface in the substrate; forming a barrier layer 202 on the sidewall surface and bottom surface of the groove; and forming a conductive layer 203 on the surface of the barrier layer 202.

[0059] The material of the barrier layer 202 includes metal nitrides, and the material of the conductive layer 203 includes metals or metal nitrides, wherein the metal nitrides include titanium nitride or tantalum nitride, and the metals include one or more combinations of copper, aluminum, tungsten, cobalt, nickel and tantalum.

[0060] In this embodiment, the material of the barrier layer 202 includes titanium nitride, and the material of the conductive layer 203 includes cobalt.

[0061] The first dielectric layer 201 is made of a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride. In this embodiment, the first dielectric layer 201 is made of silicon oxide.

[0062] Please refer to Figure 3 A stop layer 204 is formed on the conductive structure and on the first dielectric layer 201.

[0063] The stop layer 204 is used as an etching stop layer for subsequent etching of the second dielectric layer.

[0064] The material of the stop layer 204 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0065] In this embodiment, the material of the stop layer 204 includes silicon nitride, silicon oxynitride, or silicon carbide.

[0066] In other embodiments, the stop layer may not be formed.

[0067] Please continue to refer to this. Figure 3 A second dielectric layer 205 is formed on the stop layer 204. The second dielectric layer 205 has a plurality of first openings 206, and the first openings 206 expose a portion of the surface of the stop layer 204.

[0068] The method of forming the second dielectric layer 205 and the first opening 206 includes: forming an initial second dielectric layer (not shown) on a stop layer 204; forming a patterned layer (not shown) on the initial second dielectric layer, the patterned layer exposing a portion of the surface of the initial second dielectric layer; etching the initial second dielectric layer using the patterned layer as a mask until the surface of the stop layer 204 is exposed, thereby forming the second dielectric layer 205 and the first opening 206 located within the second dielectric layer 205.

[0069] The material of the stop layer 204 is different from the material of the second dielectric layer 205. Therefore, when etching the initial second dielectric layer, the etching process can stop at the stop layer 204.

[0070] The material of the second dielectric layer 205 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0071] In this embodiment, the material of the second dielectric layer 205 includes silicon oxide.

[0072] In another embodiment, the first opening directly exposes the surface of the conductive structure.

[0073] Please refer to Figure 4 An adhesive layer 207 is formed on the sidewall surface of the first opening 206, and the material of the adhesive layer 207 is a material containing metal elements.

[0074] The method of forming an adhesive layer 207 on the sidewall surface of the first opening 206 includes: forming an adhesive material layer (not shown) on the sidewall surface, bottom surface, and second dielectric layer 205 of the first opening 206; etching back the adhesive material layer until the surface of the stop layer 204 is exposed, and forming the adhesive layer 207 on the sidewall surface of the first opening 206.

[0075] The adhesive layer 207 is located only on the sidewall surface of the first opening 206, so that the stop layer 204 can protect the conductive structure and reduce the damage to the conductive structure caused by the process of forming the adhesive material layer and the process of removing the adhesive material layer at the bottom of the first opening 206.

[0076] The process for forming the adhesive material layer includes atomic layer deposition (ALD). The adhesive material layer formed by ALD has a good bonding effect with the second dielectric layer 205, thereby forming an adhesive layer 207 that can fill the gap between the subsequently formed initial electrical connection layer and the second dielectric layer 205, thus improving the overall density of the initial electrical connection layer and the second dielectric layer 205.

[0077] The adhesive layer 207 is made of a metal or a metal nitride, wherein the metal includes tantalum or titanium; and the metal nitride includes tantalum nitride, titanium nitride, tungsten nitride or tungsten carbonitride.

[0078] The adhesive layer 207 is made of the aforementioned material. On one hand, when the initial electrical connection layer is subsequently formed within the first opening 206 and the second opening using a selective deposition process, the material of the initial electrical connection layer will not grow on the surface of the adhesive layer 207. This avoids the situation where the growth direction of the initial electrical connection layer material on the adhesive layer 207 is inconsistent with the growth direction of the initial electrical connection layer material at the bottom of the second opening, resulting in a porous initial electrical connection layer structure. This ensures that the structure of the initial electrical connection layer growing from the bottom of the second opening is dense, resulting in better performance. On the other hand, the aforementioned material is easily etched, thus facilitating the formation of the adhesive layer 207 on the sidewall of the first opening 206.

[0079] In this embodiment, the adhesive layer 207 is made of titanium nitride. The process for forming titanium nitride is simple and low in cost.

[0080] In this embodiment, the thickness of the adhesive layer 207 ranges from 15 angstroms to 30 angstroms. If the thickness of the adhesive layer 207 is too thin, i.e., less than 15 angstroms, the effect on improving the adhesion between the electrical connection layer and the second dielectric layer is not significant; if the thickness of the adhesive layer 207 is too thick, i.e., greater than 30 angstroms, the resistance of the semiconductor structure is relatively large, affecting the performance of the semiconductor structure.

[0081] Please refer to Figure 5 Remove the stop layer 205 at the bottom of the first opening 206 until the top surface of the conductive structure is exposed, and form a second opening 208 in the stop layer 204 that communicates with the bottom of the first opening 206.

[0082] The process for removing the stop layer 205 at the bottom of the first opening 206 includes a dry etching process.

[0083] Please refer to Figure 6 An initial electrical connection layer 209 is formed in the first opening 206 and the second opening 208 using a selective deposition process.

[0084] The selective deposition process can form a dense initial electrical connection layer 209 within the first opening 206 with a large aspect ratio, resulting in a lower resistance and better conductivity of the subsequently formed electrical connection layer.

[0085] The material of the initial electrical connection layer 209 includes metal, including tungsten.

[0086] The parameters of the selective deposition process for forming the initial electrical connection layer 209 include: a temperature of 300 degrees Celsius to 400 degrees Celsius and a reaction gas mixture of hydrogen and tungsten hexafluoride.

[0087] In another embodiment, an initial electrical connection layer is formed within the first opening using a selective deposition process.

[0088] After removing the stop layer 205 at the bottom of the first opening 206, the process further includes cleaning the second opening 208 and the first opening 206 using a wet cleaning process. This cleaning process also eliminates the surface-active state formed on the surface of the adhesive layer 207 during the removal of the stop layer 205 at the bottom of the first opening 206, further preventing the growth of material forming the initial electrical connection layer 209 on the adhesive layer 207, which could affect the quality of the initial electrical connection layer 209.

[0089] Please refer to Figure 7 A buffer layer 210 is formed on the second dielectric layer 205 and the initial electrical connection layer 209; a padding layer 211 is formed on the buffer layer.

[0090] The padding layer 211 and the initial electrical connection layer 209 are made of the same material.

[0091] The materials of the padding layer 211 and the initial electrical connection layer 209 include metals, including tungsten.

[0092] The material of the buffer layer 210 includes one or both of a metal and a metal compound; the metal includes titanium or tantalum; the metal compound includes titanium nitride or tantalum nitride.

[0093] In this embodiment, the material of the buffer layer 210 includes titanium nitride. The buffer layer 210 is used to form a pad layer 211 on the second dielectric layer 205, and also serves as a stop layer for subsequent planarization of the pad layer 211 and the initial electrical connection layer 209.

[0094] Please refer to Figure 8 The padding layer 211, the buffer layer 210 and the initial electrical connection layer 209 are planarized until the surface of the second dielectric layer 205 is exposed, forming the electrical connection layer 212.

[0095] The process for planarizing the pad layer, buffer layer and initial electrical connection layer includes a chemical mechanical polishing process, wherein the polishing solution used in the chemical mechanical polishing process is an acidic solution.

[0096] Because the first opening 206 has an adhesive layer 207 on its sidewall, and the adhesive layer 207 is made of a material containing metal elements, the initial electrical connection layer 209 and the adhesive layer 207 have a good bonding force. As a result, the adhesive layer 207 can fill the gap between the initial electrical connection layer 209 and the second dielectric layer 205, thereby improving the overall density of the initial electrical connection layer 209 and the second dielectric layer 205. When planarizing the initial electrical connection layer 209, the damage caused by the planarization process polishing slurry can be reduced, thereby improving the performance of the semiconductor structure.

[0097] Accordingly, embodiments of the present invention also provide a semiconductor structure, please refer to [the relevant documentation]. Figure 8 ,include:

[0098] Substrate 200, the substrate comprising: a substrate, an isolation structure on the substrate, a gate structure within the isolation structure, and source / drain doped regions, the source / drain doped regions being located within the substrate on both sides of the gate structure;

[0099] A first dielectric layer 201 is located on a substrate, and the first dielectric layer 201 has a plurality of conductive structures therein, and the first dielectric layer 201 exposes the surface of the conductive structures.

[0100] A stop layer 204 is located on the conductive structure and on the first dielectric layer 201. The stop layer 204 has a second opening that exposes a portion of the surface of the conductive structure. The conductive structure is electrically connected to the gate structure or the source / drain doped region.

[0101] A second dielectric layer 205 is located on the stop layer 204, and the second dielectric layer 205 has a first opening, the top of the second opening being connected to the bottom of the first opening;

[0102] Adhesive layer 207 located on the surface of the sidewall of the first opening;

[0103] Electrical connection layer 212 located within the first opening and the second opening.

[0104] In this embodiment, the material of the adhesive layer 207 includes a metal or a metal nitride, wherein the metal includes tantalum or titanium; and the metal nitride includes tantalum nitride, titanium nitride, tungsten nitride or tungsten carbonitride.

[0105] In this embodiment, the material of the electrical connection layer 212 includes metal, and the metal includes tungsten.

[0106] In this embodiment, the first dielectric layer 201 has a groove; the conductive structure includes a barrier layer 202 located on the sidewall surface and bottom surface of the groove and a conductive layer 203 located on the surface of the barrier layer 202.

[0107] In this embodiment, the material of the barrier layer 202 includes a metal nitride, and the material of the conductive layer 203 includes a metal or a metal nitride. The metal nitride includes titanium nitride or tantalum nitride, and the metal includes one or more combinations of copper, aluminum, tungsten, cobalt, nickel, and tantalum.

[0108] In this embodiment, the material of the stop layer 204 is different from the material of the second dielectric layer 205.

[0109] In this embodiment, the material of the stop layer 204 includes a dielectric material, which includes silicon nitride, silicon oxynitride, or silicon carbide.

[0110] In other embodiments, the substrate also has a fin structure, and the gate structure extends across the fin structure.

[0111] In this embodiment, the thickness of the adhesive layer 207 ranges from 15 angstroms to 30 angstroms.

[0112] In the semiconductor structure, since the first opening 206 has an adhesive layer 207 on its sidewall, and the adhesive layer 207 is made of a material containing metal elements, the initial electrical connection layer 209 and the adhesive layer 207 have good bonding force. Thus, the adhesive layer 207 can fill the gap between the initial electrical connection layer 209 and the second dielectric layer 205, thereby improving the overall density of the initial electrical connection layer 209 and the second dielectric layer 205. During the planarization of the initial electrical connection layer 209, the damage caused by the planarization process polishing slurry can be reduced, thereby improving the performance of the semiconductor structure.

[0113] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes: a base, an isolation structure on the base, a gate structure within the isolation structure, and source / drain doped regions, wherein the source / drain doped regions are located within the base on both sides of the gate structure; A first dielectric layer is located on a substrate, the first dielectric layer has a plurality of conductive structures, the first dielectric layer exposes the surface of the conductive structures, and the conductive structures are electrically connected to the gate structure or the source / drain doped region; A stop layer located on the conductive structure and on the first dielectric layer, the stop layer having a second opening that exposes a portion of the surface of the conductive structure; A second dielectric layer located on the stop layer, the second dielectric layer having a first opening, the top of the second opening communicating with the bottom of the first opening; An adhesive layer located on the surface of the first opening sidewall, the material of the adhesive layer including metal or metal nitride; An electrical connection layer located within a first opening and a second opening, the material of the electrical connection layer including metal, the electrical connection layer being in contact with the conductive structure, and the electrical connection layer not growing on the surface of the adhesive layer.

2. The semiconductor structure as described in claim 1, characterized in that, The adhesive layer is made of a metal or a metal nitride, wherein the metal includes tantalum or titanium; and the metal nitride includes tantalum nitride, titanium nitride, tungsten nitride or tungsten carbonitride.

3. The semiconductor structure as described in claim 1, characterized in that, The material of the electrical connection layer includes metal, including tungsten.

4. The semiconductor structure as described in claim 1, characterized in that, The first dielectric layer has a groove; the conductive structure includes a barrier layer located on the sidewall surface and bottom surface of the groove and a conductive layer located on the surface of the barrier layer.

5. The semiconductor structure as described in claim 4, characterized in that, The barrier layer is made of a metal nitride, and the conductive layer is made of a metal or a metal nitride, wherein the metal nitride includes titanium nitride or tantalum nitride, and the metal includes one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum.

6. The semiconductor structure as described in claim 1, characterized in that, The material of the stop layer is different from the material of the second dielectric layer.

7. The semiconductor structure as described in claim 6, characterized in that, The material of the stop layer includes a dielectric material, which includes silicon nitride, silicon oxynitride, or silicon carbide.

8. The semiconductor structure as described in claim 1, characterized in that, The substrate also has a fin structure, and the gate structure spans the fin structure.

9. The semiconductor structure as described in claim 1, characterized in that, The thickness of the adhesive layer ranges from 15 angstroms to 30 angstroms.

10. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; A first dielectric layer is formed on a substrate, the first dielectric layer having a plurality of conductive structures therein, and the first dielectric layer exposing the surface of the conductive structures; A second dielectric layer is formed on the conductive structure and the first dielectric layer, the second dielectric layer having a plurality of first openings, the first openings exposing a portion of the surface of the conductive structure; An adhesive layer is formed on the surface of the first opening sidewall, and the material of the adhesive layer is a material containing a metal element, including a metal or a metal nitride. An initial electrical connection layer is formed in the first opening using a selective deposition process. The material of the initial electrical connection layer includes metal. The initial electrical connection layer is in contact with the conductive structure and does not grow on the surface of the adhesive layer.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The method of forming an adhesive layer on the surface of the first opening sidewall includes: forming an adhesive material layer on the surface of the first opening sidewall, the bottom surface, and the surface of the second dielectric layer; etching back the adhesive material layer until the surface of the stop layer is exposed, thereby forming an adhesive layer on the surface of the first opening sidewall.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The process of forming the adhesive material layer includes atomic layer deposition.

13. The method for forming a semiconductor structure as described in claim 11, characterized in that, The adhesive layer is made of a metal or a metal nitride, wherein the metal includes tantalum or titanium; and the metal nitride includes tantalum nitride, titanium nitride, tungsten nitride or tungsten carbonitride.

14. The method for forming a semiconductor structure as described in claim 10, characterized in that, The thickness of the adhesive layer ranges from 15 angstroms to 30 angstroms.

15. The method for forming a semiconductor structure as described in claim 10, characterized in that, Before forming the second dielectric layer on the conductive structure and the first dielectric layer, the method further includes: forming a stop layer on the conductive structure and the first dielectric layer; the second dielectric layer is located on the stop layer, and the first opening exposes the surface of the stop layer on the conductive structure.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, After forming an adhesive layer on the sidewall surface of the first opening, the method further includes: removing the stop layer at the bottom of the first opening until the top surface of the conductive structure is exposed, forming a second opening communicating with the bottom of the first opening within the stop layer; and forming an initial electrical connection layer within the first opening and the second opening using a selective deposition process.

17. The method for forming a semiconductor structure as described in claim 10, characterized in that, The material of the initial electrical connection layer includes a metal, including tungsten.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, The process parameters for the selective deposition process that forms the initial electrical connection layer include: a temperature of 300°C to 400°C and a reaction gas mixture of hydrogen and tungsten hexafluoride.

19. The method for forming a semiconductor structure as described in claim 10, characterized in that, The conductive structure includes a barrier layer and a conductive layer located on the surface of the barrier layer.

20. The method for forming a semiconductor structure as described in claim 19, characterized in that, The method for forming the conductive structure includes: forming a groove in a first dielectric layer, the groove exposing a portion of the substrate surface; forming a barrier layer on the sidewall surface and bottom surface of the groove; and forming a conductive layer on the surface of the barrier layer.

21. The method for forming a semiconductor structure as described in claim 19, characterized in that, The barrier layer is made of a metal nitride, and the conductive layer is made of a metal or a metal nitride, wherein the metal nitride includes titanium nitride or tantalum nitride, and the metal includes one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum.

22. The method for forming a semiconductor structure as described in claim 15, characterized in that, The material of the stop layer is different from the material of the second dielectric layer.

23. The method for forming a semiconductor structure as described in claim 22, characterized in that, The material of the stop layer includes a dielectric material, which includes silicon nitride, silicon oxynitride, or silicon carbide.

24. The method for forming a semiconductor structure as described in claim 10, characterized in that, After forming an initial electrical connection layer in the first opening using a selective deposition process, the method further includes: forming a buffer layer on the second dielectric layer and the initial electrical connection layer; forming a pad layer on the buffer layer; and planarizing the pad layer, the buffer layer, and the initial electrical connection layer until the surface of the second dielectric layer is exposed to form the electrical connection layer.

25. The method for forming a semiconductor structure as described in claim 24, characterized in that, The padding layer and the initial electrical connection layer are made of the same material.

26. The method for forming a semiconductor structure as described in claim 24, characterized in that, The process for planarizing the padding layer, buffer layer, and initial electrical connection layer includes a chemical mechanical polishing process.

27. The method for forming a semiconductor structure as described in claim 24, characterized in that, The material of the buffer layer includes metal nitrides, including titanium nitride or tantalum nitride.

28. The method for forming a semiconductor structure as described in claim 10, characterized in that, The substrate includes: a base; a device layer on the base, the device layer including an isolation structure and a device structure located within the isolation structure, the device structure including a transistor, diode, triode, capacitor, inductor or conductive structure; the conductive structure is electrically connected to the device structure.

29. The method for forming a semiconductor structure as described in claim 28, characterized in that, The base also has a fin structure.

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