Integrated circuit, semiconductor structure and method of forming the same

Abstract

An integrated circuit (IC) and a method of forming the same are provided. The IC includes a substrate; a conductive layer disposed on the substrate; a barrier layer disposed on the conductive layer; an etch stop layer covering sidewalls of the barrier layer and extending over a first portion of a top surface of the barrier layer; and at least one capacitor structure disposed on a second portion of the top surface of the barrier layer.

Description

Technical Field

[0001] The embodiments of the present invention relate to an integrated circuit, a semiconductor structure, and a method for forming the same. Background Technology

[0002] Many modern electronic devices (e.g., digital cameras, optical imaging devices, etc.) include image sensors. Image sensors convert optical images into digital data that can be represented as digital images. An image sensor includes an array of pixel sensors, which are unit devices used to convert optical images into digital data. Some types of pixel sensors include charge-coupled device (CCD) image sensors and complementary metal-oxide-semiconductor (CMOS) image sensors. Compared to CCD image sensors, CIS (CMOS image sensors) are favored due to their lower power consumption, smaller size, faster data processing speed, direct data output, and lower manufacturing cost. Summary of the Invention

[0003] An embodiment of the present invention provides an integrated circuit comprising: a substrate; a conductive layer disposed on the substrate; a barrier layer disposed on the conductive layer; an etch stop layer covering the sidewalls of the barrier layer and extending over a first portion of the top surface of the barrier layer; and at least one capacitor structure disposed over a second portion of the top surface of the barrier layer.

[0004] This invention provides a semiconductor structure including: a first substrate; a photodetector disposed in the first substrate; an interconnect structure disposed on the first substrate; and a first capacitor. The interconnect structure includes: an interlayer dielectric layer including opposing first sidewalls to at least partially define a first trench covering the photodetector; a lower conductive line embedded in the interlayer dielectric layer and disposed between the photodetector and the first trench; and a barrier layer disposed between the lower conductive line and the first trench, wherein a portion of the top surface of the barrier layer is exposed in the first trench. The first capacitor is disposed within the first trench to contact the portion of the top surface of the barrier layer exposed in the first trench.

[0005] This invention provides a method for forming a semiconductor structure, comprising: forming a first dielectric layer on a first substrate; forming conductive lines in the first dielectric layer; forming a barrier material on the first dielectric layer and the conductive lines; patterning the barrier material to form a barrier layer on the conductive lines; forming an etch stop layer to cover the sidewalls and top surface of the first dielectric layer and the barrier layer; forming a second dielectric layer on the etch stop layer; removing a portion of the second dielectric layer and a portion of the etch stop layer to form a trench in the second dielectric layer and the etch stop layer, wherein the trench exposes a portion of the top surface of the barrier layer; and forming a capacitor structure within the trench. Attached Figure Description

[0006] The best understanding of all aspects of this disclosure can be achieved by reading the following detailed description in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figures 1A to 1F This is a cross-sectional view of a method for forming an integrated circuit (IC) having a capacitor structure according to the first embodiment.

[0008] Figure 2 This is a cross-sectional view of an integrated circuit (IC) with a capacitor structure according to the second embodiment.

[0009] Figure 3A This is a cross-sectional view of an integrated circuit (IC) having a capacitor structure overlaid on a photodetector according to the third embodiment.

[0010] Figure 3B It is along Figure 3A Plan view of section II.

[0011] Figure 4A This is a cross-sectional view of an integrated circuit (IC) having a capacitor structure overlaid on a photodetector according to the fourth embodiment.

[0012] Figure 4B It is along Figure 4A Plan view of section II-II.

[0013] Figure 5 This is a cross-sectional view of an integrated circuit (IC) having a capacitor structure overlaid on a photodetector according to the fifth embodiment.

[0014] Figure 6 This is a cross-sectional view of an integrated circuit (IC) having a capacitor structure overlaid on a photodetector according to the sixth embodiment.

[0015] Figures 7A to 7D This is a cross-sectional view of a method for forming a semiconductor structure having a capacitor structure between a first substrate and a second substrate, according to some embodiments.

[0016] Figure 8 A flowchart of a method for forming an integrated circuit (IC) having a capacitor structure, according to some embodiments, is shown. Detailed Implementation

[0017] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. To simplify this disclosure, specific examples of components and arrangements are described below. These are, of course, merely examples and are not intended to be limiting. For example, the following description of a first feature formed on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for the purpose of brevity and clarity and is not, in itself, intended to indicate a relationship between the various embodiments and / or configurations discussed.

[0018] Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly.

[0019] Some complementary metal-oxide-semiconductor (CIS) image sensors have an array of pixel sensors. The pixel sensors in the array include an array of photodetectors (e.g., a 2×2 photodetector array) disposed in a substrate and multiple pixel devices (e.g., transfer transistors, source-follower transistors, reset transistors, row-select transistors, etc.). For CIS, such as global shutter image sensors, a high-capacitance MIM (metal-insulator-metal) capacitor is required. An MIM capacitor typically includes a capacitor dielectric layer disposed between an upper conductive electrode and a lower conductive electrode. The upper and lower conductive electrodes are typically disposed within an inter-metal dielectric (IMD) layer on the back-end (BEOL) of an integrated circuit (IC). The MIM capacitor may, for example, be electrically coupled to the pixel sensors (e.g., electrically coupled to one or more of the pixel devices). In this embodiment, trench capacitors can be used as decoupling capacitors for the pixel sensors. In some embodiments, decoupling capacitors can be widely used in various circuits. For example, a decoupling capacitor is a capacitor configured to decouple one part of a circuit from another, thereby reducing noise and coupling interference.

[0020] To achieve sufficiently high capacitance in IC applications, MIM capacitors typically occupy a relatively large IC area. However, as the minimum feature size of ICs (e.g., gate size, metal interconnect size, etc.) continues to shrink, the manufacturing process of MIM capacitors faces several challenges, such as the overhang problem of the barrier layer (e.g., TaN) due to the narrow critical dimensions of deep trenches. Specifically, the barrier layer formed by physical vapor deposition (PVD) may overhang at the top of the deep trench. In this case, the MIM capacitor may not completely fill the deep trench due to the overhang of the barrier layer, thus affecting the capacitance of the MIM capacitor. Even with the formation of a barrier layer with better coverage through atomic layer deposition (ALD), the wafer throughput (WPH) of ALD barrier layers is slower, leading to higher costs. Furthermore, the resistance of ALD barrier layers is higher than that of PVD barrier layers, thus affecting IC performance.

[0021] According to some embodiments, a barrier layer is formed first, followed by a capacitor trench to expose a portion of the barrier layer. In this case, the barrier layer is positioned directly beneath the capacitor trench to free up more trench space to accommodate the MIM capacitor, thereby increasing the capacitance of the MIM capacitor. Furthermore, dangling issues can also be addressed by forming a barrier layer outside the capacitor trench. Additionally, the PVD barrier layer has a lower resistance than the ALD barrier layer, reducing resistive-capacitive (RC) delay and thus improving IC performance.

[0022] Figures 1A to 1F This is a cross-sectional view of a method for forming an integrated circuit (IC) having a capacitor structure according to the first embodiment.

[0023] Reference Figure 1A A substrate 101 is provided. In some embodiments, the substrate 101 may be a semiconductor substrate, such as a bulk substrate, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., with p-type or n-type dopants) or undoped. Generally, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer is, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate (typically a silicon or glass substrate). For example, the substrate 101 is a wafer, such as a silicon wafer. The substrate 101 may include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer substrates or gradient substrates, may also be used. Additionally, in the front-end (FEOL) process of semiconductor manufacturing, multiple electronic components, such as photodetectors, transistors, resistors, capacitors, inductors, diodes, etc., can be formed in the device region of substrate 101. In some embodiments, any suitable formation method known or used in semiconductor manufacturing can be used to form electronic components in / on substrate 101.

[0024] A dielectric layer 102 is formed on a substrate 101. In some embodiments, the dielectric layer 102 includes silicon oxide, silicon nitride, silicon oxynitride, silicon phosphosilicate glass (PSG), borosilicate glass (BPSG), spin-coated glass (SOG), fluorinated silica glass (FSG), carbon-doped silicon oxide (e.g., SiCOH), polyimide, and / or combinations thereof. In some other embodiments, the dielectric layer 102 includes a low-k dielectric material having a dielectric constant of less than 4. Exemplary low-k dielectric materials include BLACK. (Applied Materials of Santa Clara, Calif.) Xerogel, Aerogel, Amorphous fluorinated carbon, Parylene, Bis-benzocyclobutene (BCB), Flare (Dow Chemical, Midland, Mich.), hydrogen silsesquioxane (HSQ), or fluorinated silicon oxide (SiOF), and / or combinations thereof. In alternative embodiments, dielectric layer 102 comprises one or more dielectric materials. In some embodiments, dielectric layer 102 is formed by any suitable method (e.g., chemical vapor deposition (CVD), spin coating, etc.).

[0025] A conductive layer 104 is formed in the dielectric layer 102. In some embodiments, the conductive layer 104 may be a conductive wire, conductive circuit, etc., to electrically connect electronic devices in / on the substrate 101. The conductive layer 104 may include a seed layer and a metal layer on the seed layer. The seed layer may be a conformal layer lining the sidewalls and bottom surface of the metal layer. In some embodiments, the seed layer may be a single layer or a composite layer comprising multiple sublayers formed of different materials. For example, the seed layer is a titanium / copper composite layer. The metal layer may include a metallic material, such as Al, Cu, W, Co, Pd, Pt, Ni, other low resistivity metal components, alloys thereof, or combinations thereof, and is formed by an electroplating process. Furthermore, a barrier layer may be formed between the conductive layer 104 and the dielectric layer 102 to separate the conductive layer 104 from the dielectric layer 102 and prevent metal atoms (e.g., Cu, Co, W, or Al atoms) of the conductive layer 104 from diffusing into the dielectric layer 102. The barrier layer may include Ti, TiN, Ta, TaN, alloys thereof, or combinations thereof. In some embodiments, the barrier layer and the conductive layer 104 are formed by a single damascene process, including photolithography and etching processes to form trenches in the dielectric layer 102, lining the trenches with a barrier material, filling the trenches with a conductive material, and performing a planarization process to remove excess conductive and barrier materials, such that the barrier layer, the conductive layer 104, and the dielectric layer 102 have substantially flat surfaces.

[0026] After the conductive layer 104 is formed, a barrier material 106 is formed on the dielectric layer 102 and the conductive layer 104. For example... Figure 1AAs shown, barrier material 106 covers the top surface of dielectric layer 102 and the top surface of conductive layer 104. In some embodiments, barrier material 106 includes Ti, TiN, Ta, TaN, alloys thereof, or combinations thereof, and is formed by PVD (e.g., sputtering). Alternatively, barrier material 106 can be formed by ALD.

[0027] Reference Figure 1B Patterned barrier material 106 is used to form barrier layer 106a on conductive layer 104. Although Figure 1B The width of the barrier layer 106a shown is smaller than the width of the underlying conductive layer 104, but the embodiments of this disclosure are not limited thereto. In some alternative embodiments, the width of the barrier layer 106a may be substantially equal to the width of the underlying conductive layer 104.

[0028] Reference Figure 1C After forming the barrier layer 106a, an etch stop layer 108 is formed to conformally cover the top surface of the first dielectric layer 102, a portion of the top surface of the conductive layer 104, and the sidewalls and top surface of the barrier layer 106a. In some embodiments, the etch stop layer 108 includes silicon carbide, silicon nitride, etc.

[0029] Subsequently, a dielectric layer 110 is formed on the etch stop layer 108. In some embodiments, the dielectric layer 110 includes silicon oxide, silicon nitride, silicon oxynitride, silicon phosphosilicate glass (PSG), borosilicate glass (BPSG), spin-coated glass (SOG), fluorinated silica glass (FSG), carbon-doped silicon oxide (e.g., SiCOH), polyimide, and / or combinations thereof. In some other embodiments, the dielectric layer 110 includes a low dielectric constant dielectric material. Exemplary low dielectric constant dielectric materials include BLACK. (Applied Materials of Santa Clara, Calif.), degelatin, aerogel, amorphous fluorocarbon, parylene, bisbenzocyclobutene, Flare (Dow Chemical, Midland, Mich.), silsesquioxane, or fluorinated silicon oxide, and / or combinations thereof. In alternative embodiments, dielectric layer 110 comprises one or more dielectric materials. In some embodiments, dielectric layer 110 is formed by any suitable method (e.g., CVD, spin coating, etc.). In this embodiment, dielectric layer 110 and etch stop layer 108 are made of different materials. For example, etch stop layer 108 may be a silicon carbide layer, while dielectric layer 110 may be a silicon oxide layer.

[0030] An etching process is performed to remove a portion of the dielectric layer 110 and a portion of the etch stop layer 108, thereby forming a trench 10 in the dielectric layer 110 and the etch stop layer 108. Figure 1C As shown, trench 10 exposes a second portion 106t2 of the top surface of barrier layer 106a, while etch stop layer 108 covers a first portion 106t1 of the top surface of barrier layer 106a. In some embodiments, the etching process includes a dry etching process, such as reactive ion etching (RIE). Etch stop layer 108 and dielectric layer 110 may have different etching selectivity. In this case, etch stop layer 108 can prevent the underlying barrier layer 106a from being damaged by over-etching during the etching process. In some embodiments, trench 10 has a width 10w and a height 10h, the width 10w of trench 10 may be 0.1 μm to 0.2 μm, for example 0.16 μm; the height 10h of trench 10 may be 1.0 μm to 2.0 μm, for example 1.65 μm; and the aspect ratio (i.e., 10h / 10w) of trench 10 may be 5 to 20, for example 10.31. However, the embodiments disclosed herein are not limited thereto. In other embodiments, the aspect ratio of trench 10 may be greater than 5 to achieve higher capacitance of the IC.

[0031] Reference Figure 1D A lower electrode material 112 is formed on the barrier layer 106a, and a dielectric layer 110 is overlaid on it and liner the surface of the trench 10. In some embodiments, the lower electrode material 112 includes a conductive material, such as tantalum, tantalum nitride, titanium, titanium nitride, etc., and can be formed by CVD, PVD, etc. In some embodiments, the lower electrode material 112 may have a thickness in the range of about 10 nm to 50 nm.

[0032] Then, a capacitor dielectric material 114 is formed on the lower electrode material 112 and liner-mounted on the surface of the trench 10. In some embodiments, the capacitor dielectric material 114 comprises a high-k dielectric material having a dielectric constant greater than 4, some other suitable dielectric, or any combination thereof. The high-k dielectric material may be, for example, or include hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, titanium oxide, or some other suitable high-k dielectric, or any combination thereof. In some embodiments, the capacitor dielectric material 114 may have a thickness in the range of about 2 nm to 10 nm.

[0033] Subsequently, an upper electrode material 116 is formed on the capacitor dielectric material 114 and mounted on the surface of the trench 10. In some embodiments, the upper electrode material 116 comprises a conductive material, such as tantalum, tantalum nitride, titanium, titanium nitride, etc., and can be formed by CVD, PVD, etc. In some embodiments, the upper electrode material 116 may have a thickness in the range of about 10 nm to 50 nm. The upper electrode material 116 and the lower electrode material 112 may be made of the same material or different materials.

[0034] Reference Figure 1E The upper electrode material 116 is patterned until the surface of the capacitor dielectric material 114 is exposed, thereby forming the upper electrode 126. Next, a photoresist pattern is formed to cover the upper electrode 126 and a portion of the capacitor dielectric material 114 and the lower electrode material 112 not covered by the upper electrode 126. Subsequently, using the photoresist pattern as a mask, the capacitor dielectric material 114 and the lower electrode material 112 are patterned to expose the top surface of the dielectric layer 110, thereby forming the capacitor structure 120. In some embodiments, the capacitor structure 120 includes a lower electrode 122, a capacitor dielectric layer 124, and an upper electrode 126. The lower electrode 122, which is mounted on the surface of the trench 10, has a U-shaped profile within the trench 10. The upper electrode 126 is disposed above the lower electrode 122. The capacitor dielectric layer 124 is located between the lower electrode 122 and the upper electrode 126 to separate the lower electrode 122 from the upper electrode 126. In this embodiment, the lower electrode 122 and the capacitor dielectric layer 124 have an extension portion 125 protruding from the sidewall of the upper electrode 126. In other words, the capacitor dielectric layer 124 and the lower electrode 122 have a length L1 extending on the dielectric layer 110, and the upper electrode 126 has a length L2 extending on the dielectric layer 110, where the length L1 is greater than the length L2.

[0035] In some embodiments, the upper electrode 126 may be a conformal layer lining the surface of the trench 10, and a recess 126r may be formed on the top surface of the upper electrode 126 within the trench 10. In some alternative embodiments, if the width 10w of the trench 10 is sufficiently wide, more layers may be accommodated within the trench 10. For example, the capacitor structure 120 may include five (i.e., MIMIM), seven (i.e., MIMIMIM) or more layers to increase the capacitance of the capacitor structure 120. In other embodiments, if the width 10w of the trench 10 is narrow, the upper electrode 126 may completely fill the trench 10 and form a T-shaped profile.

[0036] It should be noted that in this embodiment, a barrier layer 106a is formed, and then a trench 10 is formed directly above the barrier layer 106a to accommodate the capacitor structure 120. In this case, the barrier layer 106a is formed outside the trench 10 to free up more trench space to accommodate the capacitor structure 120, thereby increasing the capacitance of the capacitor structure 120 and solving the barrier dangling problem. Furthermore, the barrier layer 106a can be formed by PVD to reduce the resistance of the barrier layer 106a and increase the hourly wafer yield (WPH) of the barrier layer 106a.

[0037] Reference Figure 1F A dielectric layer 127, an etch stop layer 128, and a dielectric layer 129 are sequentially formed on the dielectric layer 110. The dielectric layer 127 can cover the top surface of the dielectric layer 110, overlay the capacitor structure 120, and fill the recess 126r (e.g., Figure 1E (As shown). An etch stop layer 128 is located between dielectric layers 127 and 129. In some embodiments, dielectric layers 127 and 129 include silicon oxide, silicon nitride, silicon oxynitride, silicon phosphosilicate glass (PSG), borosilicate glass (BPSG), spin-on glass (SOG), fluorinated silica glass (FSG), carbon-doped silicon oxide (e.g., SiCOH), polyimide, and / or combinations thereof. In some other embodiments, dielectric layer 110 includes a low-k dielectric material. In some embodiments, etch stop layer 128 includes silicon carbide, silicon nitride, etc. In this embodiment, dielectric layers 127 and 129 have the same dielectric material, but the dielectric material of dielectric layers 127 and 129 is different from that of etch stop layer 128. For example, dielectric layers 127 and 129 are silicon oxide layers, and etch stop layer 128 is a silicon nitride layer.

[0038] After forming dielectric layer 129, conductive features 130 are formed in dielectric layer 127, etch stop layer 128, and dielectric layer 129 to connect the upper electrode 126 of capacitor structure 120, thereby completing integrated circuit (IC) 100. Figure 1FAs shown, the conductive feature 130 may include a via 132 and conductive lines 134 on the via 132. In some embodiments, the conductive feature 130 is formed by a dual damascene method, such as a trench-first process. Specifically, the dielectric layer 129 is patterned by photolithography and etching processes to form trenches 133 therein. The trenches 133 may correspond to the capacitor structure 120. During etching, the trenches 133 stop on the etch stop layer 128, and a portion of the etch stop layer 128 is exposed by the trenches 133. Next, the portion of the etch stop layer 128 exposed in the trenches 133 and the underlying dielectric layer 127 are patterned by photolithography and etching processes to form via openings 131 therein. The via openings 131 expose the upper electrode 126 of the capacitor structure 120. Subsequently, a conductive material is formed on the dielectric layer 129 and filled into the trenches 133 and the via openings 131. Then, excess conductive material on the dielectric layer 129 is removed by a planarization process (e.g., CMP process), thereby forming conductive lines 134 in the trench 133 and vias (or plugs) 124 in the via openings 131. In addition, conductive features 130 can be formed by via-hole first processes, self-aligned processes, etc.

[0039] In some embodiments, the conductive feature 130 includes a seed layer and a metal layer on the seed layer. The seed layer may be a conformal layer lining the sidewalls and bottom surface of the metal layer. Additionally, before forming the conductive feature 130, a barrier layer may be formed, conformally covering the surface of the trench 133 and the surface of the via opening 131, and disposed between the seed layer and layers 127, 128, and 129. The barrier layer prevents metal atoms (e.g., Cu, Co, W, or Al atoms) of the conductive feature 130 from diffusing into the dielectric layers 127 and 129.

[0040] Figure 2 This is a cross-sectional view of an integrated circuit (IC) 200 having a capacitor structure 220 according to the second embodiment.

[0041] Reference Figure 2 IC 200 is similar to Figure 1F The IC 100, but the upper electrode 226 is completely filled in the trench 20 and formed in a T-shaped profile. In some embodiments, the width 20w of the trench 20 is less than Figure 1CThe trench 10 shown has a width of 10w. In this case, the conformal upper electrodes 226 mounted on the surface of the trench 20 can be connected to each other to form a T-shaped profile. That is, the capacitor structure 220 may include a lower electrode 222 with a U-shaped profile, an upper electrode 226 with a T-shaped profile, and a capacitor dielectric layer 224 between the lower electrode 222 and the upper electrode 226 within the trench 20. The structure, materials, and functions of IC 200 are similar to those of IC 100 and have been described in detail in the above embodiments, so they will not be repeated here.

[0042] Figure 3A This is a cross-sectional view of an integrated circuit (IC) 300 having a capacitor structure 120 overlaid on a photodetector 103 according to a third embodiment. Figure 3B It is along Figure 3A Plan view of section II.

[0043] Reference Figure 3A IC 300 may include a substrate 101 and an interconnect structure 150 on the substrate 101. Specifically, the substrate 101 may have a pixel region 101a and a logic region 101b adjacent to the pixel region 101a. The pixel region 101a includes a photodetector 103 disposed in the substrate 101. In some embodiments, the substrate 101 may include a bulk silicon substrate and / or may include a first doping type (e.g., p-type). The photodetector 103 is configured to convert incident electromagnetic radiation (e.g., light) into an electrical signal. The photodetector 103 includes a second doping type opposite to the first doping type (e.g., n-type). In this embodiment, the photodetector 103 is a photodiode in the substrate 101.

[0044] The interconnect structure 150 may overlay the substrate 101 and may be configured to electrically couple devices (e.g., transistors, photodetectors 103, capacitor structures 120, etc.) to each other. Specifically, the interconnect structure 150 may include a plurality of dielectric layers 152 (e.g., 152a, 152b, 152c, 152d, 152e), a plurality of etch stop layers 154 (e.g., 154a, 154b), a plurality of conductive lines 156 (e.g., 156a, 156b), and a plurality of vias 158 (e.g., 158a, 158b). The etch stop layers 154 are disposed between the dielectric layers 152. The conductive lines 156 are arranged in the dielectric layers 152 and the etch stop layers 154. The vias 158 connect to two conductive lines in the conductive lines 156. In some embodiments, dielectric layer 152a may be referred to as an interlayer dielectric (ILD) layer, while dielectric layers 152b, 152c, 152d, and 152e may be referred to as intermetallic dielectric (IMD) layers. The interconnect structure 150 also includes a conductive layer 104 and a barrier layer 106a. The conductive layer 104 may be disposed on dielectric layer 152a and embedded in dielectric layer 152b (corresponding to...). Figure 1F The dielectric layer 102 in the middle). In this embodiment, the conductive layer 104 and the conductive line 156a are substantially at the same level, for example, metal n-1 (Mn-1). Here, when a component is described as "substantially at the same level", it means that the components are formed at substantially the same height in the same layer, or are embedded in the same position in the same layer. In some embodiments, components substantially at the same level are formed of the same material and with the same process steps. In some embodiments, the tops of components substantially at the same level are substantially coplanar. For example, such as Figure 3A As shown, the conductive layer 104 and the conductive line 156a have the same height in the same dielectric layer 152b. The barrier layer 106a is disposed on the conductive layer 104. Additionally, the etch stop layer 154a (corresponding to...) Figure 1F An etch stop layer 154a is applied over the top surface of the dielectric layer 152b and extends to cover a portion of the top surface of the conductive layer 104 and a portion of the top surface and sidewalls of the barrier layer 106a. The composite layer consisting of the dielectric layer 152c and the etch stop layer 154a includes opposing sidewalls 151 to form a trench 10, and the capacitor structure 120 is disposed within the trench 10. In this case, the etch stop layer 154a is in physical contact with the lower sidewall of the capacitor structure 120. The lower electrode 122 is in physical contact with the opposing sidewalls 151 (i.e., the sidewalls of the trench 10) of the composite layer consisting of the dielectric layer 152c and the etch stop layer 154a. Figure 3AAs shown, the interconnect structure 150 also includes a conductive feature 130 disposed on and electrically coupled to the lower electrode 122 of the capacitor structure 120. In this embodiment, the conductive feature 130 and the conductive line 156b are substantially at the same level, for example, metal n (Mn). That is, the top surface of the conductive feature 130 and the top surface of the conductive line 156b are substantially coplanar.

[0045] Reference Figure 3B The trench 10 may have a width 10w in the X direction and a length 10l in the Y direction. In some embodiments, the length 10l is greater than the width 10w. In some alternative embodiments, the length 10l may be equal to or less than the width 10w. The conductive layer 104 may have a width 104w in the X direction and a length 104l in the Y direction, while the barrier layer 106a may have a width 106w in the X direction and a length 106l in the Y direction. Figure 3B As shown, the width 106w of the barrier layer 106a spans the width 10w of the trench 10 (i.e., the width 106w is greater than the width 10w), while the width 104w of the conductive layer 104 spans the width 106w of the barrier layer 106a (i.e., the width 104w is greater than the width 106w). In this case, the contact area between the barrier layer 106a and the conductive layer 104 is greater than the contact area between the barrier layer 106a and the capacitor structure 120 within the trench 10. In some alternative embodiments, the width 104w of the conductive layer 104 may be equal to the width 106w of the barrier layer 106a.

[0046] Refer back Figure 3B The logic region 101b is laterally configured and adjacent to the pixel region 101a. The logic region 101b includes a semiconductor device, such as a transistor 140. The transistor 140 is disposed on the substrate 101. In some embodiments, the transistor 140 includes a source / drain region 142, a gate structure 145, and a spacer 148. The gate structure 145 may include a gate dielectric layer 144 and a gate 146 on the gate dielectric layer 144. The transistor 140 may be electrically coupled to vias (or contact windows) 158a, conductive lines 156a, vias 158b, and conductive lines 156b in the interconnect structure 150. In some embodiments, a capacitor structure 120 may be electrically coupled to the photodetector 103 and / or the transistor 140. In this case, the capacitor structure 120 can be used as a decoupling capacitor to reduce noise and coupling interference of the IC 300.

[0047] Figure 4A This is a cross-sectional view of an integrated circuit (IC) 400 having a capacitor structure 420 overlaid on a photodetector 103 according to the fourth embodiment. Figure 4B It is along Figure 4A Plan view of section II-II.

[0048] Reference Figure 4A IC 400 is similar to Figure 3A IC 300, but Figure 4A The capacitor structure 420 includes a first capacitor region 420a within a first trench 11 and a second capacitor region 420b within a second trench 12. Specifically, the first trench 11 and the second trench 12 are disposed on the same barrier layer 406 on the same conductive layer 404. The first trench 11 may be laterally offset from the second trench 12 by a non-zero distance. The lower electrode 422 of the capacitor structure 420 extends continuously from the surface of the first trench 11 to cover the surface of the second trench 12. The capacitor structure 420 also includes an upper electrode 426 and a capacitor dielectric layer 424. The upper electrode 426 is disposed on the lower electrode 422 and continuously lined on the surfaces of the first trench 11 and the second trench 12. The capacitor dielectric layer 424 is located between the lower electrode 422 and the upper electrode 426 to separate the lower electrode 422 from the upper electrode 426. A conductive feature 130 is disposed on the upper electrode 426 between the first trench 11 and the second trench 12. In other words, the conductive feature 130 is laterally offset from the first and second trenches 11 and 12 by a non-zero distance.

[0049] In some embodiments, the first trench 11 has a width 11w and a height 11h. The width 11w of the first trench 11 can be from 0.10 μm to 0.15 μm, for example, 0.12 μm; the height 11h of the first trench 11 can be from 1.0 μm to 2.0 μm, for example, 1.65 μm; and the aspect ratio (i.e., 11h / 11w) of the first trench 11 can be from 6.67 to 20, for example, 13.75. Additionally, the second trench 12 has a width 12w and a height 12h. The width 12w of the second trench 12 can be from 0.10 μm to 0.15 μm, for example, 0.12 μm; the height 12h of the second trench 12 can be from 1.0 μm to 2.0 μm, for example, 1.65 μm; and the aspect ratio (i.e., 12h / 12w) of the second trench 12 can be from 6.67 to 20, for example, 13.75. In this embodiment, as the number of trenches in IC 400 is twice that of IC 300, the capacitance of the capacitor structure in IC 400 also increases (i.e., doubles). However, the embodiments of this disclosure are not limited thereto. In other embodiments, three, four, or more trenches are also included within the scope of this embodiment, thereby further increasing the capacitance of the capacitor structure in the IC.

[0050] Reference Figure 4BThe first trench 11 may have a width 11w in the X direction and a length 11l in the Y direction, while the second trench 12 may have a width 12w in the X direction and a length 12l in the Y direction. In some embodiments, the length 11l is greater than the width 11w, and the length 12l is greater than the width 12w. The conductive layer 404 may have a width 404w in the X direction and a length 404l in the Y direction, while the barrier layer 406 may have a width 406w in the X direction and a length 406l in the Y direction. Figure 4B As shown, the width 406w of the barrier layer 406 spans the width 11w of the first trench 11 and the width 12w of the second trench 12. That is, the width 406w is greater than the sum of the widths 11w and 12w. The width 404w of the conductive layer 404 spans the width 406w of the barrier layer 406 (i.e., the width 404w is greater than the width 406w). In this case, the contact area between the barrier layer 406 and the conductive layer 404 is greater than the contact area between the barrier layer 406 and the capacitor structures 420 in the first trench 11 and the second trench 12. In some alternative embodiments, the width 404w of the conductive layer 404 may be equal to the width 406w of the barrier layer 406.

[0051] Figure 5 This is a cross-sectional view of an integrated circuit (IC) 500 having a capacitor structure 520 overlaid on a photodetector 103 according to the fifth embodiment.

[0052] Reference Figure 5 IC 500 is similar to Figure 4A The IC 400 is used, but the capacitor structure 520 is divided into two capacitors 520a and 520b. Specifically, the first capacitor 520a is formed in the first trench 11 and connects the barrier layer 506a and the conductive feature 530a on the conductive layer 504a. The first capacitor 520a may include a lower electrode 522a, an upper electrode 526a, and a capacitor dielectric layer 524a between the lower electrode 522a and the upper electrode 526a. Similarly, the second capacitor 520b is formed in the second trench 12 and connects the barrier layer 506b and the conductive feature 530b on the conductive layer 504b. The second capacitor 520b may include a lower electrode 522b, an upper electrode 526b, and a capacitor dielectric layer 524b between the lower electrode 522b and the upper electrode 526b. The first capacitor 520a and the second capacitor 520b are separated from each other by a portion of dielectric layer 152d and a portion of dielectric layer 152c between them. In this embodiment, the first capacitor 520a and the second capacitor 520b are electrically connected to different conductive layers 504a / 504b and different conductive features 530a / 530b, thereby increasing the flexibility of the internal wiring.

[0053] Figure 6This is a cross-sectional view of an integrated circuit (IC) 600 having a capacitor structure 620 overlaid on a photodetector 103 according to the sixth embodiment.

[0054] Reference Figure 6 The interconnect structure 150 includes multiple dielectric layers 152 (e.g., 152a, 152b, 152c, 152d, 152e, 152f, 152g), multiple etch stop layers 154 (e.g., 154a, 154b, 154c, 154d), multiple conductive lines 156 (e.g., 156a, 156b, 156c), and multiple vias 158 (e.g., 158a, 158b). The etch stop layers 154 are disposed between the dielectric layers 152. The conductive lines 156 are arranged in the dielectric layers 152 and the etch stop layers 154. The vias 158 connect to two conductive lines in the conductive lines 156. It should be noted that the capacitor structure 620 can penetrate the dielectric layers 152c, 152d, and 152e, as well as the etch stop layers 154b and 154c, thereby connecting the lower conductive line 156a (e.g., metal n-1 (Mn-1)) and the upper conductive line 156c (e.g., metal n+1 (Mn+1)). In other words, the capacitor structure 620 can cross at least one layer of metal in the interconnect structure 150 in the vertical direction, such as the intermediate conductive line 156b (e.g., metal n (Mn)).

[0055] In some embodiments, Figure 6 The height of the capacitor structure 620 is greater than Figure 3A The height of the capacitor structure 620. In this embodiment, by increasing the height of the capacitor structure 620, the area between the lower and upper electrodes of the capacitor structure 620 can be increased. This can increase... Figure 6 The capacitance of the medium capacitor structure is 620.

[0056] In addition, although Figure 6 Only a single capacitor structure 620 within a single deep trench is shown in this embodiment, but the embodiments of this disclosure are not limited thereto. In other embodiments, the number of deep trenches can be adjusted as needed. That is, capacitor structures within two deep trenches (e.g., capacitor structures 520 / 620), three deep trenches, or more deep trenches may also be included in the scope of this embodiment to increase the capacitance of the capacitor structure in the IC.

[0057] Figures 7A to 7D This is a cross-sectional view of a method for forming a semiconductor structure having a capacitor structure between a first substrate and a second substrate, according to some embodiments.

[0058] Reference Figure 7AIC 700 is provided. IC 700 may be one of IC 300, IC 400, IC 500, or IC 600 having at least one capacitor structure 120, 420, 520, or 620 in the interconnect structure 150. The configuration, materials, and functions of IC 300, IC 400, IC 500, and IC 600 have been described in detail in previous embodiments and will not be repeated here. For clarity, Figure 7A Only the top conductive feature or top conductive line 156T is shown in the internal interconnect structure 150, while... Figure 7A Other components, such as dielectric layers, etch stop layers, conductive lines, vias, and capacitor structures, are omitted.

[0059] In some embodiments, IC 700 may include logic dies (e.g., central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC), application processor (AP), microcontroller, etc.), memory dies (e.g., dynamic random access memory (DRAM) dies, static random access memory (SRAM) dies, etc.), power management dies (e.g., power management integrated circuit (PMIC) dies), radio frequency (RF) dies, sensor dies, microelectromechanical systems (MEMS) dies, signal processing dies (e.g., digital signal processing (DSP) dies), front-end dies (e.g., analog front-end (AFE) dies), application-specific dies (e.g., application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), etc.), similar dies, or combinations thereof.

[0060] Reference Figure 7B Another IC 800 is provided to be bonded to IC 700. In some embodiments, IC 800 may include logic dies (e.g., central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC), application processor (AP), microcontroller, etc.), memory dies (e.g., dynamic random access memory (DRAM) dies, static random access memory (SRAM) dies, etc.), power management dies (e.g., power management integrated circuit (PMIC) dies), radio frequency (RF) dies, sensor dies, microelectromechanical systems (MEMS) dies, signal processing dies (e.g., digital signal processing (DSP) dies), front-end dies (e.g., analog front-end (AFE) dies), application-specific dies (e.g., application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), etc.), similar dies, or combinations thereof. In this embodiment, IC 800 is different from IC 700. For example, IC 700 may be an SoC wafer, while IC 800 may be an ASIC wafer.

[0061] Specifically, IC 800 may include a substrate 801 and interconnect structures 850 on the substrate 801. In some embodiments, the substrate 801 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., having p-type or n-type dopants) or undoped. Generally, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer is, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate (typically a silicon or glass substrate). For example, the substrate 801 is a wafer, such as a silicon wafer. The substrate 801 may include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer substrates or gradient substrates, may also be used. Additionally, in the front-end (FEOL) process of semiconductor manufacturing, multiple electronic components, such as photodetectors, transistors, resistors, capacitors, inductors, diodes, etc., can be formed in the device region of substrate 801. In some embodiments, any suitable formation method known or used in semiconductor manufacturing can be used to form electronic components in / on substrate 801.

[0062] In some embodiments, the interconnect structure 850 includes an interlayer dielectric (ILD) layer 852 and a plurality of conductive features (not shown) including conductive lines 856 and vias. The ILD layer 852 includes a plurality of dielectric layers. The conductive features are arranged in the dielectric layers. For clarity, the top conductive line exposed on the ILD layer 852 is labeled “856T”.

[0063] like Figure 7B As shown, IC 800 is flipped upside down and mounted onto IC 700. Specifically, IC 700 and IC 800 are joined face-to-face via interconnect structure 150 and interconnect structure 850. In some embodiments, before IC 800 is joined to IC 700, interconnect structure 150 and interconnect structure 850 are aligned such that top conductive line 156T can be joined to top conductive line 856T. In some embodiments, the alignment of top conductive line 156T and top conductive line 856T can be achieved using an optical sensing method. After alignment, interconnect structure 150 and interconnect structure 850 are joined together using a hybrid bonding process to form hybrid bonding structure 50.

[0064] In some embodiments, interconnect structure 150 and interconnect structure 850 are hybridized together by applying pressure and heat. It is noteworthy that the hybrid bonding process includes at least two bonding processes, including metal-to-metal bonding and non-metal-to-non-metal bonding, such as dielectric-to-dielectric bonding or fusion bonding. Figure 7B As shown, the hybrid bonding structure 50 includes top conductive lines 156T and 856T bonded by metal-to-metal bonding, and dielectric layers 152 and 852 bonded by non-metal-to-non-metal bonding.

[0065] Reference Figure 7C After performing the hybrid bonding process, the back side 101bs of the substrate 101 of IC 700 is thinned or polished until the photodetector 103 is exposed or nearly exposed. In some alternative embodiments, doped regions and / or negatively charged films are formed on the photodetector 103 to repair defects formed during the thinning of the substrate 101.

[0066] Reference Figure 7D According to some embodiments, optical elements are then formed on the photodetector 103 to guide light into the photodetector 103. Specifically, a dielectric layer 702 may be formed on the back side 101bs of the substrate 101. A reflective grid 704 is formed in the dielectric layer 702 to divide the dielectric layer 702 into a plurality of inner regions 703. The reflective grid 704 may laterally surround the inner regions 703, such that the inner regions 703 may be configured as rectangular, square, or other design shapes as needed. The inner regions 703 may correspond to the photodetector 103 below. That is, the reflective grid 704 may laterally surround the photodetector 103 in an upper view. In some embodiments, the reflective grid 704 may be a metal grid for reflecting light into the photodetector 103. Alternatively, the reflective grid 704 may be a composite grid including a metal grid and a low-refractive-index (low-n) grid covered by a metal grid. The low-n grid has a "low" refractive index relative to the dielectric layer 702 to promote total internal reflection, thereby preventing radiation from passing between adjacent internal regions 703.

[0067] After forming the reflective grid 704, a filter film 706 is formed on the dielectric layer 702 and the reflective grid 704. In some embodiments, the filter film 706 extends to cover the reflective grid 704 and the internal region 703 surrounded by the reflective grid 704. Subsequently, a plurality of microlenses 708 are formed on the filter film 706. Figure 7DAs shown, microlenses 708 correspond to photodetectors 103 below. In some embodiments, microlenses 708 are configured to focus incident radiation (e.g., light) onto photodetectors 103. For example, microlenses 708 may have a convex upper surface configured to focus radiation onto photodetectors 103.

[0068] Figure 8 A flowchart 1000 illustrating a method for forming a memory device according to some embodiments is provided. Although the disclosed method 1000 is shown and described herein as a series of actions or events, it should be understood that the order in which these actions or events are shown should not be construed as limiting. For example, some actions may occur in a different order, and / or may occur simultaneously with other actions or events besides those shown and / or described herein. Furthermore, not all of the actions shown may be necessary when implementing one or more aspects or embodiments described herein. Additionally, one or more of the actions illustrated herein may be performed in one or more separate actions and / or stages. Figure 8 Shown by Figures 1A to 1E Some embodiments of the disclosed method.

[0069] Reference Figure 8 At box 1010, a first dielectric layer is formed on the first substrate. Figure 1A Cross-sectional views corresponding to some embodiments of block 1010 are shown.

[0070] Reference Figure 8 At box 1020, a conductive line is formed in the first dielectric layer. Figure 1A Cross-sectional views corresponding to some embodiments of block 1020 are shown.

[0071] Reference Figure 8 At box 1030, a barrier material is formed between the first dielectric layer and the conductive line. Figure 1A Cross-sectional views corresponding to some embodiments of block 1030 are shown.

[0072] Reference Figure 8 At box 1040, patterned barrier material is used to form a barrier layer on the conductive line. Figure 1B Cross-sectional views corresponding to some embodiments of block 1040 are shown.

[0073] Reference Figure 8At box 1050, an etch stop layer is formed to cover the sidewalls and top surface of the first dielectric layer and the barrier layer. Next, at box 1060, a second dielectric layer is formed on the etch stop layer. Subsequently, at box 1070, a portion of the second dielectric layer and a portion of the etch stop layer are removed to form a trench in the second dielectric layer and the etch stop layer, wherein the trench exposes a portion of the top surface of the barrier layer. Figure 1C Cross-sectional views are shown corresponding to some embodiments of blocks 1050 to 1070.

[0074] Reference Figure 8 At frame 1080, a capacitor structure is formed within the trench. Figure 1D and Figure 1E Cross-sectional views corresponding to some embodiments of block 1080 are shown.

[0075] According to one embodiment, an integrated circuit includes: a substrate; a conductive layer disposed on the substrate; a barrier layer disposed on the conductive layer; an etch stop layer covering the sidewalls of the barrier layer and extending over a first portion of the top surface of the barrier layer; and at least one capacitor structure disposed over a second portion of the top surface of the barrier layer.

[0076] In some embodiments, the etch stop layer physically contacts the lower sidewall of the at least one capacitor structure. In some embodiments, the integrated circuit further includes: a first dielectric layer laterally surrounding the conductive layer, wherein the etch stop layer covers the top surface of the first dielectric layer and a portion of the top surface of the conductive layer; and a second dielectric layer disposed on the etch stop layer such that the etch stop layer is disposed between the first dielectric layer and the second dielectric layer, wherein the composite layer formed by the second dielectric layer and the etch stop layer includes opposing sidewalls to define at least one trench, and the at least one capacitor structure is disposed within the at least one trench. In some embodiments, the at least one capacitor structure includes: a lower electrode lined to the surface of the at least one trench and electrically connected to the conductive layer by contacting a second portion of the top surface of the barrier layer; an upper electrode disposed on the lower electrode; and a capacitor dielectric layer disposed between the lower electrode and the upper electrode to separate the lower electrode from the upper electrode. In some embodiments, the lower electrode physically contacts the opposing sidewall of the composite layer formed by the second dielectric layer and the etch stop layer. In some embodiments, the contact area between the barrier layer and the conductive layer is larger than the contact area between the barrier layer and the at least one capacitor structure. In some embodiments, the at least one capacitor structure includes: a first capacitor region disposed within a first trench defined by opposing first sidewalls of the composite layer formed by the second dielectric layer and the etch stop layer; and a second capacitor region disposed within a second trench defined by opposing second sidewalls of the composite layer formed by the second dielectric layer and the etch stop layer, wherein the lower electrode of the at least one capacitor structure extends continuously from the surface of the first trench to cover the surface of the second trench. In some embodiments, the substrate includes a pixel region and a logic region, the at least one capacitor structure is disposed above the substrate of the pixel region, and further includes a photodetector disposed in the substrate of the pixel region.

[0077] According to one embodiment, a semiconductor structure includes: a first substrate; a photodetector disposed in the first substrate; an interconnect structure disposed on the first substrate; and a first capacitor. The interconnect structure includes: an interlayer dielectric layer including opposing first sidewalls to at least partially define a first trench overlying the photodetector; a lower conductive line embedded in the interlayer dielectric layer and disposed between the photodetector and the first trench; and a barrier layer disposed between the lower conductive line and the first trench, wherein a portion of the top surface of the barrier layer is exposed in the first trench. The first capacitor is disposed within the first trench to contact the portion of the top surface of the barrier layer exposed in the first trench.

[0078] In some embodiments, the interconnect structure further includes: an etch stop layer covering the sidewalls of the barrier layer and extending over a portion of the top surface of the barrier layer not covered by the first capacitor. In some embodiments, the etch stop layer physically contacts the lower sidewall of the first capacitor. In some embodiments, the interconnect structure includes: an upper conductive line disposed on the first capacitor, wherein the interlayer dielectric layer comprises a plurality of dielectric layers, and the plurality of conductive lines are arranged in the plurality of dielectric layers, wherein the first capacitor penetrates the plurality of dielectric layers to connect the upper conductive line and the lower conductive line. In some embodiments, the first capacitor includes: a lower electrode disposed within the first trench and electrically connected to the lower conductive line through a portion contacting the top surface of the barrier layer; an upper electrode disposed on the lower electrode; and a capacitor dielectric layer disposed between the lower electrode and the upper electrode to separate the lower electrode and the upper electrode. In some embodiments, the lower electrode has a U-shaped profile within the first trench, while the upper electrode has a T-shaped profile. In some embodiments, the interlayer dielectric layer further includes opposing second sidewalls to at least partially define a second trench, the second trench being laterally offset from the first trench, wherein a second capacitor is disposed within the second trench. In some embodiments, the semiconductor structure further includes: a second substrate bonded to the first substrate such that the interconnect structure is disposed between the first substrate and the second substrate; a metal grid disposed on the back side of the first substrate, wherein the metal grid laterally surrounds the photodetector in an upward viewing angle; a filter film disposed on the metal grid; and a microlens disposed on the filter film and corresponding to the photodetector.

[0079] According to one embodiment, a method for forming a semiconductor structure includes: forming a first dielectric layer on a first substrate; forming conductive lines in the first dielectric layer; forming a barrier material in the first dielectric layer and the conductive lines; patterning the barrier material to form a barrier layer on the conductive lines; forming an etch stop layer to cover the first dielectric layer and the sidewalls and top surface of the barrier layer; forming a second dielectric layer on the etch stop layer; removing a portion of the second dielectric layer and a portion of the etch stop layer to form a trench in the second dielectric layer and the etch stop layer, wherein the trench exposes a portion of the top surface of the barrier layer; and forming a capacitor structure within the trench.

[0080] In some embodiments, forming the capacitor structure includes: forming a lower electrode material on the barrier layer, the lower electrode material being covered by the second dielectric layer and lining the surface of the trench; forming a capacitor dielectric material, the capacitor dielectric material being covered by the lower electrode material and lining the surface of the trench; forming an upper electrode material, the upper electrode material being covered by the capacitor dielectric material and lining the surface of the trench; and patterning the upper electrode material to form an upper electrode, and patterning the capacitor dielectric material and the lower electrode material to form a capacitor dielectric layer and a lower electrode, wherein the length of the capacitor dielectric layer and the lower electrode extending on the second dielectric layer is greater than the length of the upper electrode extending on the second dielectric layer. In some embodiments, the bottom width of the barrier layer is greater than the width of the trench. In some embodiments, the method of forming the semiconductor structure further includes: forming a photodetector in a first substrate before forming the first dielectric layer, wherein the photodetector corresponds to the capacitor structure; bonding a second substrate to the first substrate after forming the capacitor structure such that the capacitor structure is located between the second substrate and the first substrate; thinning the back side of the first substrate to expose the photodetector; forming a metal grid on the thinned back side of the first substrate; forming a filter film on the metal grid; and forming a microlens on the filter film.

[0081] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art will understand that this disclosure can be used as a basis for designing or modifying other processes and structures to achieve the same purposes and / or realize the same advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and modifications thereto without departing from the spirit and scope of this disclosure.

Claims

1. An integrated circuit, comprising: Substrate; A conductive layer is disposed on the substrate; A barrier layer is disposed on the conductive layer, wherein a first portion of the top surface of the conductive layer is covered by the barrier layer, and a second portion of the top surface of the conductive layer is exposed outside the barrier layer. An etch stop layer covers the sidewalls of the barrier layer and extends over a first portion of the top surface of the barrier layer; as well as At least one capacitor structure is disposed on the second portion of the top surface of the barrier layer.

2. The integrated circuit of claim 1, wherein the etch stop layer physically contacts the lower sidewall of the at least one capacitor structure.

3. The integrated circuit according to claim 1, further comprising: A first dielectric layer laterally surrounds the conductive layer, wherein the etch stop layer covers the top surface of the first dielectric layer and the second portion of the top surface of the conductive layer; as well as A second dielectric layer is disposed on the etch stop layer such that the etch stop layer is disposed between the first dielectric layer and the second dielectric layer, wherein the composite layer formed by the second dielectric layer and the etch stop layer includes opposing sidewalls to define at least one trench, and the at least one capacitor structure is disposed within the at least one trench.

4. The integrated circuit of claim 3, wherein the at least one capacitor structure comprises: The lower electrode is fitted onto the surface of the at least one trench and is electrically connected to the conductive layer through the second portion of the top surface of the barrier layer. The upper electrode is disposed on the lower electrode; as well as A capacitor dielectric layer is disposed between the lower electrode and the upper electrode to separate the lower electrode from the upper electrode.

5. The integrated circuit of claim 4, wherein the lower electrode physically contacts the opposing sidewalls of the composite layer formed by the second dielectric layer and the etch stop layer.

6. The integrated circuit according to claim 1, wherein the contact area between the barrier layer and the conductive layer is greater than the contact area between the barrier layer and the at least one capacitor structure.

7. The integrated circuit of claim 3, wherein the at least one capacitor structure comprises: The first capacitor region is disposed within a first trench defined by opposing first sidewalls of the composite layer formed by the second dielectric layer and the etch stop layer; as well as The second capacitor region is disposed within a second trench defined by opposing second sidewalls of the composite layer formed by the second dielectric layer and the etch stop layer, wherein the lower electrode of the at least one capacitor structure extends continuously from the surface of the first trench to cover the surface of the second trench.

8. The integrated circuit of claim 1, wherein the substrate includes a pixel region and a logic region, the at least one capacitor structure is disposed above the substrate of the pixel region, and further includes a photodetector disposed in the substrate of the pixel region.

9. A semiconductor structure, comprising: First substrate; A photodetector is disposed in the first substrate; An interconnect structure is disposed on the first substrate, the interconnect structure comprising: An interlayer dielectric layer, including opposing first sidewalls, defines at least partially a first trench overlying the photodetector; The lower conductive line is embedded in the interlayer dielectric layer and disposed between the photodetector and the first trench; and A barrier layer is disposed between the lower conductive line and the first trench, wherein a portion of the top surface of the barrier layer is exposed in the first trench; and A first capacitor is disposed within the first trench to contact a portion of the top surface of the barrier layer exposed in the first trench, wherein a first portion of the top surface of the lower conductive line is covered by the barrier layer, and a second portion of the top surface of the lower conductive line is exposed in the barrier layer.

10. The semiconductor structure according to claim 9, wherein the interconnect structure further comprises: An etch stop layer covers the sidewalls of the barrier layer and extends over the remaining portion of the top surface of the barrier layer not covered by the first capacitor.

11. The semiconductor structure of claim 10, wherein the etch stop layer physically contacts the lower sidewall of the first capacitor.

12. The semiconductor structure according to claim 9, wherein the interconnect structure comprises: The upper conductive line is disposed on the first capacitor. The interlayer dielectric layer comprises multiple dielectric layers, and multiple conductive lines are arranged within the multiple dielectric layers. The first capacitor penetrates the plurality of dielectric layers to connect the upper conductive line and the lower conductive line.

13. The semiconductor structure of claim 9, wherein the first capacitor comprises: The lower electrode is disposed in the first trench and is electrically connected to the lower conductive line through the portion that contacts the top surface of the barrier layer; The upper electrode is disposed on the lower electrode; as well as A capacitor dielectric layer is disposed between the lower electrode and the upper electrode to separate the lower electrode from the upper electrode.

14. The semiconductor structure of claim 13, wherein the lower electrode has a U-shaped profile within the first trench, and the upper electrode has a T-shaped profile.

15. The semiconductor structure of claim 9, wherein the interlayer dielectric layer further comprises opposing second sidewalls to at least partially define a second trench, the second trench being laterally offset from the first trench, wherein a second capacitor is disposed within the second trench.

16. The semiconductor structure according to claim 9, further comprising: A second substrate is bonded to the first substrate such that the interconnect structure is disposed between the first substrate and the second substrate; A metal grid is disposed on the back side of the first substrate, wherein the metal grid laterally surrounds the photodetector in an upward viewing angle; A filter film is disposed on the metal grid; as well as A microlens is disposed on the filter film and corresponds to the photodetector.

17. A method for forming a semiconductor structure, comprising: A first dielectric layer is formed on a first substrate; A conductive layer is formed in the first dielectric layer; A barrier material is formed on the first dielectric layer and the conductive layer; The barrier material is patterned such that a barrier layer is formed on the conductive layer, wherein a first portion of the top surface of the conductive layer is covered by the barrier layer, and a second portion of the top surface of the conductive layer is exposed outside the barrier layer. An etch stop layer is formed to cover the sidewalls and top surface of the first dielectric layer and the barrier layer; A second dielectric layer is formed on the etch stop layer; A portion of the second dielectric layer and a portion of the etch stop layer are removed to form a trench in the second dielectric layer and the etch stop layer, wherein the trench exposes a second portion of the top surface of the barrier layer, and the etch stop layer extends over a first portion of the top surface of the barrier layer. as well as A capacitor structure is formed within the trench, such that the capacitor structure is disposed on the second portion of the top surface of the barrier layer.

18. The method for forming a semiconductor structure according to claim 17, wherein forming the capacitor structure comprises: A lower electrode material is formed on the barrier layer, the lower electrode material is covered with the second dielectric layer, and the surface of the trench is lined. A capacitor dielectric material is formed, wherein the lower electrode material is covered on the capacitor dielectric material and the surface of the trench is lined; An upper electrode material is formed, the upper electrode material is covered with the capacitor dielectric material and lining the surface of the trench; as well as The upper electrode material is patterned to form an upper electrode, and the capacitor dielectric material and the lower electrode material are patterned to form a capacitor dielectric layer and a lower electrode, wherein the length of the capacitor dielectric layer and the lower electrode extending on the second dielectric layer is greater than the length of the upper electrode extending on the second dielectric layer.

19. The method for forming a semiconductor structure according to claim 17, wherein the bottom width of the barrier layer is greater than the width of the trench.

20. The method for forming a semiconductor structure according to claim 17, further comprising: Before forming the first dielectric layer, a photodetector is formed in the first substrate, wherein the photodetector corresponds to the capacitor structure; After the capacitor structure is formed, a second substrate is bonded to the first substrate so that the capacitor structure is located between the second substrate and the first substrate; The back side of the first substrate is thinned to expose the photodetector; A metal grid is formed on the thinned back side of the first substrate; A filter film is formed on the metal grid; as well as Microlenses are formed on the filter film.

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