Optical sensor, display device and method of manufacturing an optical sensor

Abstract

The application discloses a photoelectric sensor, a display device and a preparation method of the photoelectric sensor. The photoelectric sensor comprises a substrate, a photoelectric conversion layer, a spacing layer and a top electrode. The photoelectric conversion layer is arranged between the substrate and the top electrode. The spacing layer is arranged between the photoelectric conversion layer and the top electrode. The spacing layer comprises a conductive area and an insulating area. The conductive area is used for realizing electrical connection between the photoelectric conversion layer and the top electrode. In the above manner, the photoelectric sensor device with closer arrangement can be prepared.

Description

Technical Field

[0001] This invention relates to the field of optoelectronic technology, and in particular to an optoelectronic sensor, a display device, and a method for fabricating the optoelectronic sensor. Background Technology

[0002] The fabrication of printed circuit boards (PCBs) involves numerous vias. The function of vias is to conduct electricity between the upper and lower substrates. However, during fabrication, the location, size, and bevel angle of the vias all affect the final product quality. In particular, the size of the vias, limited by equipment and processes, often cannot be made very small, typically having a diameter greater than 4 micrometers. Combined with subsequent patterning and routing constraints, this restricts the final layout design, thus limiting the circuit arrangement. Furthermore, via offset and etching angles must also be considered, resulting in numerous process-related issues that urgently require improvement. Summary of the Invention

[0003] The main technical problem solved by this invention is to provide a photoelectric sensor, a display device, and a method for manufacturing the photoelectric sensor, which can produce photoelectric sensor devices with a more compact arrangement.

[0004] To solve the above-mentioned technical problems, one technical solution adopted by the present invention is: to provide a photoelectric sensor, the photoelectric sensor including a substrate, a photoelectric conversion layer, a spacer layer and a top electrode; the photoelectric conversion layer is disposed between the substrate and the top electrode; the spacer layer is disposed between the photoelectric conversion layer and the top electrode, the spacer layer including a conductive region and an insulating region, the conductive region being used to realize the electrical connection between the photoelectric conversion layer and the top electrode.

[0005] In one embodiment, the spacer layer is an amorphous silicon layer or a low-temperature polycrystalline silicon layer, and the conductive region is a P-type doped region.

[0006] In one embodiment, the sheet resistance of the conductive region is less than or equal to 3000 ohms per square centimeter.

[0007] In one embodiment, the P-type doped region is one or more of a boron doped region and a gallium doped region.

[0008] In one embodiment, the N-type doped region is one or more of phosphorus doped regions and arsenic doped regions.

[0009] In one embodiment, the thickness of the conductive region of the spacer layer is 100~200 nm.

[0010] In one embodiment, the conductive region does not extend beyond the area where the photoelectric conversion layer is located.

[0011] In one embodiment, the photoelectric conversion layer includes a photodiode.

[0012] To solve the above-mentioned technical problems, another technical solution adopted by the present invention is to provide a display device, which includes a display panel and a photoelectric sensor. The display panel is used to realize the display function, and the photoelectric sensor is any of the above-mentioned photoelectric sensors.

[0013] To solve the above-mentioned technical problems, another technical solution adopted by the present invention is: to provide a method for fabricating a photoelectric sensor, the method comprising providing a substrate; forming a photoelectric conversion layer on the substrate; forming a spacer layer on the photoelectric conversion layer; performing a conductive treatment on the spacer layer to form a conductive region; and forming a top electrode on the spacer layer, the top electrode covering the conductive region.

[0014] In one embodiment, forming a spacer layer on the photoelectric conversion layer includes: forming a low-temperature polycrystalline silicon layer or an amorphous silicon layer on the photoelectric conversion layer; and ion-doping a portion of the low-temperature polycrystalline silicon layer or the amorphous silicon layer to form a conductive region.

[0015] In one embodiment, ion doping of a portion of a low-temperature polycrystalline silicon layer or amorphous silicon layer to form a conductive region includes: ion implantation of a portion of a low-temperature polycrystalline silicon layer or amorphous silicon layer, wherein the implanted ions are one or more of boron ions and gallium ions to form a P-type doped region; or the implanted ions are one or more of phosphorus ions and arsenic ions to form an N-type doped region.

[0016] The beneficial effects of this invention are as follows: Unlike existing technologies, this invention sets a portion of the spacer layer as a conductive region and other regions as insulating regions, eliminating the need for perforations in the spacer layer. Instead, the spacer layer itself is designed to be conductive. In this way, the arrangement of photoelectric sensors is no longer limited by via technology, enabling the fabrication of more densely packed photoelectric sensor devices, a larger light-receiving area, improved performance, and higher yield rates. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the structure of a photoelectric sensor according to one embodiment of this application;

[0018] Figure 2 This is a schematic diagram of the structure of a photoelectric sensor in another embodiment of this application;

[0019] Figure 3 This is a schematic flowchart of a photoelectric sensor fabrication method according to one embodiment of this application;

[0020] Figure 4A This is a schematic flowchart of a photoelectric sensor fabrication method according to another embodiment of this application;

[0021] Figure 4BThis is a schematic flowchart of a photoelectric sensor fabrication method according to another embodiment of this application. Detailed Implementation

[0022] To make the purpose, technical solution and effects of this application clearer and more explicit, the following describes this application in further detail with reference to the accompanying drawings and embodiments.

[0023] Photoelectric sensors are key components in various photoelectric detection systems, converting light signals (e.g., infrared, visible, and ultraviolet radiation) into electrical signals. A typical photoelectric sensor consists of a substrate and a photodiode on the substrate. A photodiode absorbs light signals—photons—and converts them into electrical signals—current. The photodiode, in the direction away from the substrate, sequentially includes a bottom electrode, a diode structure layer, a dielectric layer, and a top electrode. Generally, the dielectric layer has vias that expose the diode structure layer, enabling electrical connection between the diode structure layer and the top electrode. The presence of these vias restricts the layout and wiring of the photoelectric sensor, limiting the final layout design and resulting in lower circuit density.

[0024] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of a photoelectric sensor according to one embodiment of this application. In this embodiment, a photoelectric sensor is provided, comprising a substrate 10, a photoelectric conversion layer 20, a spacer layer 30, and a top electrode 40. The photoelectric conversion layer 20 is disposed between the substrate 10 and the top electrode 40, and the spacer layer 30 is disposed between the photoelectric conversion layer 20 and the top electrode 40. The spacer layer 30 includes a conductive region 31 and an insulating region 32, and the conductive region 31 is used to achieve electrical connection between the photoelectric conversion layer 20 and the top electrode 40.

[0025] The substrate 10 includes a substrate and an array layer disposed on the substrate. The array layer includes thin-film transistors (TFTs) to function as switches.

[0026] The photoelectric conversion layer 20 can be a diode structure layer for photoelectric conversion of light. The diode structure layer can be a PIN junction or a PN junction structure. Alternatively, the photodiode can be a PN photodiode, a PIN photodiode, avalanche photodiode, MIM diode junction, MIS diode junction, MOS diode junction, SIS diode junction, and MS diode junction, etc., without further limitation.

[0027] The top electrode 40 is a transparent electrode layer. In this embodiment, the transparent electrode layer can be made of indium tin oxide (ITO), a transparent conductive material. In other embodiments, the transparent electrode layer can be replaced with an IZO transparent electrode layer, which is made of indium zinc oxide (IZO), a transparent conductive material.

[0028] The spacer layer 30 is used to isolate the photoelectric conversion layer 20 from the top electrode 40, and also to provide electrical connection between the photoelectric conversion layer 20 and the top electrode 40. That is, a part of the spacer layer 30 is a conductive region 31, and a part is an insulating region 32.

[0029] In this embodiment, by setting a portion of the spacer layer as a conductive area and the rest as an insulating area, it is no longer necessary to drill holes in the spacer layer. Instead, a localized area of ​​the spacer layer itself is designed to be conductive. In this way, the arrangement of the photoelectric sensor is no longer limited by via technology, enabling the fabrication of more densely packed photoelectric sensor devices, a larger area for light reception, improved performance, and increased yield.

[0030] In one embodiment, the spacer layer 30 can be an amorphous silicon layer or a low-temperature polycrystalline silicon layer. That is, in this application, a-Si (amorphous silicon) or LTPS (Low Temperature Poly-Silicon) is used instead of inorganic films such as silicon oxide or silicon nitride to achieve isolation between the photoelectric conversion layer 20 and the top electrode 40. Simultaneously, local areas of the spacer layer 30 are treated, such as by ion doping, to transform certain areas of the spacer layer 30 into regions with high conductivity, thereby enabling conduction between the photoelectric conversion layer 20 and the top electrode 40. Alternatively, the conductive region 31 can be an N-type doped region or a P-type doped region, and the insulating region 32 can be an undoped region.

[0031] In one embodiment, the sheet resistance of the conductive region 31 of the spacer layer 30 is less than or equal to 3000 ohms per square centimeter, so that the conductivity satisfies the electrical connection between the top electrode 40 and the photoelectric conversion layer 20. For example, the sheet resistance of the conductive region is 2000 Ω / cm. 2 2200 Ω / cm 2 2500 Ω / cm 2 2800 Ω / cm 2 wait.

[0032] This application does not impose restrictions on the type and concentration of doped elements in the doped region, as long as the sheet resistance of the conductive region 31 after doping meets the conduction requirements between the top electrode 40 and the photoelectric conversion layer 20. P-type or N-type doping can be performed on a portion of the amorphous silicon layer or the low-temperature polycrystalline silicon layer to form N-type or P-type doped regions. For example, the N-type doped region can be one or more of phosphorus doping or arsenic doping, and the P-type doped region can be one or more of boron doping or gallium doping.

[0033] In one embodiment, the thickness of the conductive region 31 of the spacer layer 30 is 100~200 nm, for example, it can be 100 nm, 120 nm, 150 nm, 180 nm, 200 nm, etc. When ion doping is performed on the spacer layer 30, the doping depth should be equal to or slightly less than the thickness of the conductive region 31 to ensure that electrical conduction can be achieved after doping. Where the thickness of the photoelectric sensor device allows, the thicker the conductive region, the better. At the same time, the conductive region 31 does not extend beyond the area where the photoelectric conversion layer 20 is located; that is, only the photoelectric conversion region conducts electricity, while other regions should be kept insulated.

[0034] Please see Figure 2 , Figure 2 This is a schematic diagram of the structure of a photoelectric sensor according to another embodiment of this application. In this embodiment, the photoelectric sensor includes a substrate, a photoelectric conversion layer, a spacer layer, and a top electrode.

[0035] The substrate includes a substrate and an array layer disposed on the substrate. The array layer includes a buffer layer, an active layer, and multiple metal layers and multiple insulating layers disposed on the active layer. Specifically, the buffer layer includes a silicon nitride layer (SiNx) and a silicon oxide layer (SiOx) disposed on a stack; the active layer is a polycrystalline silicon layer, and the active layer includes a channel region, a lightly doped region, and a heavily doped region; the metal layers include a first metal layer (M1), a second metal layer (M2), and a third metal layer (M3), etc.

[0036] Further, the substrate includes a thin-film transistor (TFT), which includes a gate, a gate insulating layer, an active layer, a source, and a drain, sequentially located on the substrate. Typically, the gate of the TFT is electrically connected to the scan line, one of the source and drain of the TFT is electrically connected to the data line, and the other of the source and drain of the TFT is electrically connected to a photodiode (specifically, to the bottom electrode of the photodiode). More preferably, the gate of the TFT and the scan line are located in the same metal layer; the source and drain of the TFT, the data line, and the bottom electrode of the photodiode are located in the same metal layer. It should be noted that... Figure 2The thin-film transistor shown is a bottom-gate thin-film transistor, which is a commonly used structure known in the art. However, for those skilled in the art, there are many other designs of thin-film transistors, such as top-gate thin-film transistors, which are all suitable for this invention and are not limited here.

[0037] The photoelectric conversion layer 20 can be a photodiode structure layer, which can be a multilayer PIN junction including a first sublayer (not shown) having a first conductivity type, a second sublayer (not shown) made of intrinsic semiconductor material, and a third sublayer (not shown) having a second conductivity type opposite to the first conductivity type. In this embodiment, the first, second, and third sublayers are preferably made of amorphous silicon, with the first conductivity type being p-type and the second conductivity type being n-type. In other embodiments, the first and third sublayers can also be made of microcrystalline silicon, silicon germanide, cadmium telluride, cadmium selenide, cadmium sulfide, copper indium selenide, copper indium gallium selenide, or dye-sensitized titanium dioxide. The first sublayer is adjacent to the transparent electrode layer (i.e., the top electrode 40), the second sublayer is disposed between the first sublayer and the bottom electrode layer, and the third sublayer is disposed between the second sublayer and the bottom electrode layer. Typically, an insulating layer (not shown) is disposed between the third sublayer of the photodiode structure and the bottom electrode layer. The two layers can be electrically connected to the underlying bottom electrode layer through vias (not shown) penetrating this insulating layer. In this embodiment, the bottom electrode layer is made of a metal such as gold, silver, copper, aluminum, or an alloy thereof, or other known metallic materials. As those skilled in the art know, the bottom electrode layer can also be made of a metal and a metal barrier material covering the metal, wherein the metal barrier material includes titanium or tantalum.

[0038] In one embodiment, spacers comprising monocrystalline silicon or low-temperature polycrystalline silicon can be used instead of the insulating layers in the array layer to achieve isolation between the film layers, and ion doping can be performed on certain regions to achieve electrical connections between the film layers. The conductivity of the conductive region of the spacer layer in the array layer should be greater than the conductivity of the conductive region of the spacer layer at the photodiode.

[0039] In one embodiment, the photoelectric sensor further includes an optical fiber guide plate (not shown) and an encapsulation layer (not shown) disposed on the top electrode away from the photoelectric conversion layer. Light passing through the optical fiber guide plate is reflected at the object surface (such as a fingerprint) where it is connected to the optical fiber guide plate. The reflected light enters the photodiode, which converts the optical signal into an electrical signal and outputs it through a thin-film transistor, thereby reflecting information about the object surface.

[0040] The photoelectric sensors provided in the above embodiments can be applied to fingerprint recognition, vein imaging, and counterfeit currency recognition, etc.

[0041] Based on this, this application also provides a display device, which includes a display panel and a photoelectric sensor. The display panel can be an organic light-emitting diode (OLED) display panel, capable of displaying functions. The photoelectric sensor can be any of the photoelectric sensors described in the above embodiments. The display device can be a mobile phone, tablet computer, etc., and the photoelectric sensor it carries can be used for fingerprint recognition, enabling the display device to have fingerprint recognition functionality, such as using fingerprint recognition to unlock the display device. The display device can also be a wearable device such as a wristband or watch, and the photoelectric sensor it carries can be used for vein imaging, enabling the wearable device to detect the frequency of changes in blood concentration and the human pulse rate.

[0042] Please refer to the following: Figure 3 and Figure 4A and Figure 4B , Figure 3 This is a schematic flowchart of a photoelectric sensor fabrication method according to one embodiment of this application. Figures 4A-4B This is a schematic flowchart of a photoelectric sensor fabrication method according to another embodiment of this application. In this embodiment, the photoelectric sensor fabrication method includes:

[0043] S110: Provides a substrate.

[0044] The substrate includes a substrate, insulated cross-shaped scan lines and data lines located on the substrate, and a TFT disposed at the intersection of the scan lines and data lines; the gate of the TFT is electrically connected to the scan line, and one of the source / drain electrodes of the TFT is electrically connected to the data line; the substrate also includes an insulating layer covering the other of the drain / source electrodes of the TFT, and a via exposing the other of the drain / source electrodes of the TFT, the via being used for electrically connecting the other of the drain / source electrodes of the TFT to the bottom electrode layer of a photodiode. The substrate may be made of glass or quartz.

[0045] like Figure 4A As shown, a substrate is provided, and silicon nitride (SiNx) and silicon oxide (SiNx) are sequentially deposited on the substrate to form a buffer layer. Then, an amorphous silicon layer (a-Si) is deposited on the buffer layer, and hydrogen removal and high-temperature crystallization are performed to obtain a polycrystalline silicon layer. Exposure, development, and etching are then performed to obtain the active layer. A mask is used to perform ion implantation on the polycrystalline silicon layer to obtain heavily doped regions, forming the source and drain active regions. After doping, a first insulating layer is formed, which can be a silicon nitride or silicon oxide layer. The gate layer of the thin-film transistor is formed on the first insulating layer. Using the gate as a mask, the active layer is lightly doped (LDD) to obtain a lightly doped region. After doping, a second insulating layer (protective layer) is formed, which can be a silicon nitride or silicon oxide layer. The source and drain of the thin-film transistor are formed on the first insulating layer. Subsequently, a third insulating layer is formed, which can be a silicon nitride or silicon oxide layer.

[0046] S120: A photoelectric conversion layer is formed on the substrate.

[0047] A bottom electrode layer and a photodiode structure layer are formed on a substrate. The bottom electrode layer can be made of a metallic material, and the photodiode structure layer is a multilayer structure. Forming the photodiode structure layer specifically includes forming a third sublayer of a second conductivity type, followed by forming a second sublayer made of an intrinsic semiconductor material on the third sublayer using, for example, a vapor phase epitaxy method, and then forming a first sublayer having a first conductivity type opposite to the second conductivity type. The first, second, and third sublayers are preferably made of amorphous silicon, with the first conductivity type being p-type and the second conductivity type being n-type. In other embodiments, the first and third sublayers may also be made of microcrystalline silicon, silicon germanide, cadmium telluride, cadmium selenide, cadmium sulfide, copper indium selenide, copper indium gallium selenide, or dye-sensitized titanium dioxide.

[0048] like Figure 4B As shown, a third metal layer (M3) is formed on the third insulating layer, and the bottom electrode can be on the same layer as the third metal layer. Then, a photodiode structure layer (PIN) is formed on the third metal layer.

[0049] S130: A spacer layer is formed on the photoelectric conversion layer.

[0050] In this process, an amorphous silicon layer or a low-temperature polycrystalline silicon layer is formed in the photodiode structure layer as a spacer layer. The polycrystalline silicon layer can be formed by laser irradiation of the amorphous silicon using excimer laser annealing (ELA) or microarray lens laser annealing (MLA) techniques.

[0051] like Figure 4B As shown, amorphous silicon (a-Si) is formed on the photodiode structure layer.

[0052] S140: Conduct the spacer layer to form a conductive region.

[0053] Ion implantation (Doping) can be used to dopant a portion of the spacer layer.

[0054] Specifically, an intermediate layer can be formed on the spacer layer first. This intermediate layer can be formed by deposition methods, such as physical vapor deposition (PVD) methods like magnetron sputtering or vacuum evaporation, or chemical vapor deposition (CVD) methods like plasma-enhanced chemical vapor deposition (PECVD). Since the intermediate layer affects the ion beam energy and slows down the ion beam rate during ion implantation, it is typically an organic or inorganic porous layer to facilitate subsequent ion implantation into the polycrystalline silicon layer and the removal of the intermediate layer. That is, the intermediate layer can be an organic or inorganic porous membrane. The material forming the intermediate layer is selected from at least one of polyolefin resins, polyesters (PE), polytetrafluoroethylene (PTFE), polyurethane (PU), and polylactic acid esters. A sparse, non-dense intermediate layer allows for relatively smooth ion implantation into the polycrystalline silicon layer, resulting in doped polycrystalline silicon with the desired doping concentration. Furthermore, the intermediate layer is easy to remove after ion implantation, and the removal process does not adversely affect the polycrystalline silicon layer.

[0055] A patterned photoresist is formed on the upper surface of the intermediate layer. There are no restrictions on the specific type of photoresist; it can be either positive or negative, and those skilled in the art can choose flexibly according to actual needs. The method of forming the photoresist is also not limited. In this invention, the method includes, but is not limited to, coating. The photoresist layer is sequentially exposed and developed to obtain the patterned photoresist. Those skilled in the art can flexibly select the exposure area and exposure time, as well as the specific type of developer and development time, according to the specific type of photoresist; no restrictions are imposed here.

[0056] Ion implantation is performed on the polysilicon layer from above the patterned photoresist. After ion implantation, the polysilicon layer is divided into doped regions (conductive regions) and undoped regions (insulating regions).

[0057] The implanted ions are one or more of boron (B) ions and gallium (Ga) ions to form a P-type doped region; or the implanted ions are one or more of phosphorus (P) ions and arsenic (As) ions to form an N-type doped region.

[0058] To ensure ions can penetrate the intermediate layer and be successfully implanted into the polycrystalline silicon layer, the ion beam energy for polycrystalline silicon doping is 5–50 keV, such as 5 keV, 10 keV, 15 keV, 20 keV, 25 keV, 30 keV, 35 keV, 40 keV, 45 keV, or 50 keV, and the ion beam dose is 10¹¹–10¹⁷ / cm². 2 For example, 10¹¹ / cm 2 1012 / cm 2 1013 / cm 2 1014 / cm 2 1015 / cm2 1016 / cm 2 Or 1017 / cm 2 Those skilled in the art can flexibly adjust the ion beam implantation energy and dosage within the aforementioned range based on the specific material and thickness of the intermediate layer, so that ions can be successfully implanted into the polycrystalline silicon layer to obtain the doped polycrystalline silicon with the aforementioned doping concentration.

[0059] After the intermediate layer is peeled off, the hardened photoresist is also removed. To successfully and completely peel the intermediate layer from the surface of the polysilicon layer, a stripping solution can be used. This stripping is performed by bringing the stripping solution into contact with the intermediate layer. In other words, a stripping solution that can chemically react with the intermediate layer is used, but which does not react with the polysilicon layer or adversely affect the doped ions within it. Therefore, the specific type of stripping solution depends on the specific material of the intermediate layer, and those skilled in the art can flexibly select the appropriate solution based on the specific type of intermediate layer.

[0060] like Figure 4B As shown, ion implantation is performed on amorphous silicon (a-Si) to form heavily doped regions.

[0061] S150: A top electrode is formed on the spacer layer, and the top electrode covers the conductive region.

[0062] The resulting top electrode layer is a transparent electrode layer. This transparent electrode layer can be made of indium tin oxide (IZO), a transparent conductive material; in other embodiments, the transparent electrode layer can be replaced with an IZO transparent electrode layer, which is made of indium zinc oxide (IZO), a transparent conductive material.

[0063] like Figure 4B As shown, a top electrode is formed on an amorphous silicon (a-Si) layer, and the top electrode covers the heavily doped region.

[0064] In this embodiment, by setting a portion of the spacer layer as a conductive area and the rest as an insulating area, it is no longer necessary to drill holes in the spacer layer; instead, the spacer layer itself is designed to be conductive. In this way, the arrangement of the photoelectric sensor is no longer limited by via technology, enabling the fabrication of more densely packed photoelectric sensor devices, a larger area for light reception, improved performance, and increased yield.

[0065] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this invention.

Claims

1. A photosensor, characterized by, The photoelectric sensor comprises: a substrate; a top electrode; a photoelectric conversion layer disposed between the substrate and the top electrode; a spacer layer disposed between the photoelectric conversion layer and the top electrode, the spacer layer comprising a conductive region and an insulating region, the conductive region being configured to electrically connect the photoelectric conversion layer and the top electrode; the spacer layer is an amorphous silicon layer or a low-temperature polysilicon layer, the conductive region is an N-type doped region or a P-type doped region, and the insulating region is an undoped region; the depth of the doped region is less than or equal to the thickness of the conductive region.

2. The photosensor according to claim 1, wherein The substrate comprises a substrate and an array layer disposed on the substrate, and the photoelectric conversion layer comprises a photodiode structure layer, and the conductivity of the conductive region of the spacer layer in the array layer is greater than the conductivity of the conductive region of the spacer layer at the photodiode.

3. The photoelectric sensor according to claim 1, wherein the sheet resistance of the conductive region is less than or equal to 3000 ohms per square centimeter.

4. The photoelectric sensor according to claim 1, wherein the P-type doped region is one or more of a boron doped region and a gallium doped region; or the N-type doped region is one or more of a phosphorus doped region and an arsenic doped region.

5. The photoelectric sensor according to claim 1, wherein the thickness of the spacer layer is 100-200 nm.

6. The photoelectric sensor according to claim 1, wherein the conductive region does not exceed the area where the photoelectric conversion layer is located, and the photoelectric conversion layer comprises a photodiode.

7. A display device, characterized by The display panel is configured to realize a display function, and the photoelectric sensor is the photoelectric sensor according to any one of claims 1-6.

8. A method of manufacturing a photoelectric sensor, characterized by, The method comprises: providing a substrate; forming a photoelectric conversion layer on the substrate; forming a spacer layer on the photoelectric conversion layer; conducting the spacer layer to form a conductive region; forming a top electrode on the spacer layer, the top electrode covering the conductive region; the spacer layer is an amorphous silicon layer or a low-temperature polysilicon layer, and the conductive region is an N-type doped region or a P-type doped region.

9. The method of fabricating a photosensor according to claim 8, wherein The method of conducting the spacer layer to form a conductive region comprises: forming an intermediate layer on the spacer layer; the method of conducting the spacer layer comprises ion implantation, and the ion beam energy of the ion implantation is 5KeV-50KeV.

10. The method of fabricating a photosensor according to claim 8, wherein The method of forming a spacer layer on the photoelectric conversion layer comprises: forming a low-temperature polysilicon layer or an amorphous silicon layer on the photoelectric conversion layer; ion doping a part of the low-temperature polysilicon layer or the amorphous silicon layer to form the conductive region.

11. The method of fabricating a photosensor according to claim 10, wherein The method of ion doping a part of the low-temperature polysilicon layer or the amorphous silicon layer to form the conductive region comprises: ion implanting a part of the low-temperature polysilicon layer or the amorphous silicon layer, the implanted ions being one or more of boron ions and gallium ions to form a P-type doped region; or the implanted ions being one or more of phosphorus ions and arsenic ions to form an N-type doped region.

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