Display panel and manufacturing method thereof

Abstract

The application provides a display panel and a manufacturing method thereof. A protection layer is arranged between a gate sub-layer and a gate insulating layer in a gate layer. The protection layer can protect the gate insulating layer from a wet etching process, and is beneficial to reducing the time of exposure of the gate insulating layer to an etching gas atmosphere in a dry etching process, thereby reducing the thickness loss of the gate insulating layer. In the embodiment of the application, the thickness of the second gate insulating part at any position is greater than 5 / 6 of the thickness of the first gate insulating part.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a manufacturing method thereof. BACKGROUND

[0002] In order to meet the demand of high charging rate for low impedance of high resolution and high frequency medium size products, a bottom metal layer is usually prepared before the metal Mo layer is prepared to make the crystal size of the formed metal Mo layer larger. The metal Mo / bottom metal double-layer structure has lower impedance as the gate electrode. At present, the gate electrode is manufactured by two dry etching processes. Since the etching time of the gate electrode with the double-layer structure is long, the gate insulating layer is in the etching gas atmosphere for a long time, and there is a certain thickness loss. The thickness loss is more than 20%. The reduction of the film thickness of the gate insulating layer will reduce the threshold voltage Vth and the critical conduction state of the device, which is not conducive to the increase of the threshold voltage gap.

[0003] Therefore, it is necessary to use a suitable process to manufacture the gate electrode to reduce the loss of the film thickness of the gate insulating layer. SUMMARY

[0004] Embodiments of the present application provide a display panel and a manufacturing method thereof to solve the technical problem of high loss of the film thickness of the gate insulating layer caused by the existing gate manufacturing process.

[0005] Embodiments of the present application provide a display panel, which comprises an array substrate, wherein the array substrate comprises:

[0006] a substrate;

[0007] an active layer located on the substrate;

[0008] a gate insulating layer located on the active layer, wherein the gate insulating layer comprises a first gate insulating part and a second gate insulating part adjacent to the first gate insulating part;

[0009] a gate layer located on the gate insulating layer, wherein the gate layer comprises a gate sub-layer and a protective layer, and the protective layer is located between the gate sub-layer and the gate insulating layer;

[0010] wherein the first gate insulating part is arranged corresponding to the gate layer, and the thickness of any position of the second gate insulating part is greater than 5 / 6 of the thickness of the first gate insulating part.

[0011] In the display panel provided by the embodiments of the present application, the active layer comprises an active part and a doped part adjacent to the active layer, the projection of the gate layer on the substrate covers the projection of the active part on the substrate, and the projection of the second gate insulating part on the substrate covers the projection of the doped part on the substrate.

[0012] In the display panel provided in the embodiment of the present application, the doped portion comprises a first doped portion and a second doped portion, and the second doped portion is located between the first doped portion and the active portion.

[0013] The second gate insulating portion comprises a first sub-portion and a second sub-portion, the second sub-portion is located between the first gate insulating portion and the first sub-portion, the projection of the first sub-portion on the substrate covers the projection of the first doped portion on the substrate, the projection of the second sub-portion on the substrate covers the projection of the second doped portion on the substrate, and the thickness of the second sub-portion is greater than the thickness of the first sub-portion.

[0014] In the display panel provided in the embodiment of the present application, the thickness of the protective layer is 5 nm to 50 nm.

[0015] In the display panel provided in the embodiment of the present application, the display panel comprises a display area and a non-display area adjacent to the display area, and the gate layer comprises a plurality of test gates located in the non-display area, and the spacing between two adjacent test gates is less than 2 μm.

[0016] In the display panel provided in the embodiment of the present application, the thickness of the first gate insulating portion is 100 nm to 150 nm, and the thickness of the second gate insulating portion at any position is less than the thickness of the first gate insulating portion.

[0017] The embodiment of the present application provides a manufacturing method of a display panel, comprising the following steps:

[0018] A substrate is provided, and an active layer is formed on the substrate.

[0019] A gate insulating layer is formed on the active layer, the gate insulating layer comprises a first gate insulating portion and a second gate insulating portion adjacent to the first gate insulating portion, and the thickness of the second gate insulating portion at any position is greater than 5 / 6 of the thickness of the first gate insulating portion.

[0020] A gate layer is formed on the gate insulating layer, the gate layer comprises a gate sub-layer and a protective layer, the protective layer is located between the gate sub-layer and the gate insulating layer, and the first gate insulating portion is arranged correspondingly to the gate layer.

[0021] In the manufacturing method of the display panel provided in the embodiment of the present application, the step of forming the gate layer on the gate insulating layer further comprises:

[0022] A second gate material sub-layer, a first gate material sub-layer, and an organic photoresist are sequentially formed on the gate insulating layer.

[0023] The first gate material sub-layer is patterned by using a wet etching process to form a first gate material layer.

[0024] The second gate material layer is formed by patterning the second gate material sub-layer by using a first dry etching process.

[0025] The gate sub-layer and the protective layer are respectively formed by patterning the first gate material layer and the second gate material layer by using a second dry etching process.

[0026] In the manufacturing method of the display panel provided in the embodiments of the present application, the etching time of the first dry etching process is less than the etching time of the second dry etching process.

[0027] In the manufacturing method of the display panel provided in the embodiments of the present application, the step of forming the second gate material layer by patterning the second gate material sub-layer by using the first dry etching process further comprises:

[0028] The active layer is ion doped to form a first doped part of the active layer.

[0029] The present application has the following beneficial effects: The present application provides a display panel and a manufacturing method thereof. By arranging a protective layer between the gate sub-layer and the gate insulating layer in the gate layer, the protective layer can protect the gate insulating layer from the wet etching process, and is conducive to reducing the time for which the gate insulating layer is exposed to the etching gas atmosphere in the dry etching process, thereby reducing the thickness loss of the gate insulating layer. In the embodiments of the present application, the thickness of the second gate insulating part at any position is greater than 5 / 6 of the thickness of the first gate insulating part. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0031] Figure 1 The top view structural schematic diagram of the display panel provided in the embodiments of the present application;

[0032] Figure 2 The flowchart schematic diagram of the manufacturing method of the display panel provided in the embodiments of the present application;

[0033] Figures 3-8The structural schematic diagram of the manufacturing method of the display panel provided in the embodiment of the present application is shown. The figure description is as follows: 1-array substrate, 11-substrate, 12-light shielding layer, 13-buffer layer, 14-active layer, 15-gate insulating layer, 16-gate layer, 17-interlayer insulating layer, 18-source / drain electrode layer, 19-insulating layer, 141-doped part, 1411-first doped part, 1412-second doped part, 142-active part, 151-first gate insulating part, 152-second gate insulating part, 1521-first subpart, 1522-second subpart, 161-protective layer, 162-gate sublayer, 1610-first gate material sublayer, 1611-first gate material layer, 1620-second gate material sublayer, 1621-second gate material layer, 110-organic photoresist, 1601-test gate, AA-display area, AZ-non-display area. DETAILED DESCRIPTION

[0034] The technical solutions in the embodiments of the present application will be described clearly and completely in the following with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a group of embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application. In addition, it should be understood that the specific implementation manners described herein are only used for illustrating and explaining the present application, and are not used for limiting the present application. In the description of the present application, it should be understood that the orientations or positional relationships indicated by the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “upper”, “lower”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inner”, “outer”, “clockwise”, “counterclockwise” and the like are the orientations or positional relationships shown in the drawings, and are only used for the convenience of describing the present application and simplifying the description, and thus cannot be understood as indicating or implying that the devices or elements indicated must have particular orientations, be constructed and operated in particular orientations, and thus cannot be understood as limiting the present application. In addition, the terms “first” and “second” are only used for description purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features limited by “first” and “second” can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of “multiple” is two or more, unless otherwise specifically limited.

[0035] The present application provides a display panel and a manufacturing method thereof. The following will be described in detail respectively. It should be noted that the description order of the following embodiments is not limited as the preferred order of the embodiments.

[0036] Reference Figure 1The embodiment of the present application provides a display panel, comprising an array substrate 1, the array substrate 1 comprising a substrate 11, an active layer 14 located on the substrate 11, a gate insulating layer 15 located on the active layer 14, and a gate layer 16 located on the gate insulating layer 15; the gate insulating layer 15 comprises a first gate insulating part 151 and a second gate insulating part 152 adjacent to the first gate insulating part 151, the gate layer 16 comprises a gate sub-layer 162 and a protective layer 161, and the protective layer 161 is located between the gate sub-layer 162 and the gate insulating layer 15; wherein the first gate insulating part 151 is arranged corresponding to the gate layer 16, and the thickness of the second gate insulating part 152 at any position is greater than 5 / 6 of the thickness of the first gate insulating part 151.

[0037] It can be understood that, in order to meet the demand of high charging rate for low impedance of high resolution and high frequency medium-sized products, a bottom metal layer is usually prepared before the metal Mo layer is prepared, so that the crystal size of the formed metal Mo layer is larger, and the impedance of the metal Mo / bottom metal double-layer structure as the gate electrode is lower. At present, two dry etching processes are used to manufacture the gate electrode. Since the etching time of the gate electrode with the double-layer structure is long, the gate insulating layer is in the etching gas atmosphere for a long time, and there is a certain thickness loss. The thickness loss amount is more than 20%. The reduction of the thickness of the gate insulating layer film will cause the threshold voltage Vth to drop, the critical conduction state of the device to reduce, and the threshold voltage gap to increase. Therefore, a suitable process needs to be used to manufacture the gate electrode to reduce the loss amount of the thickness of the gate insulating film. In the embodiment of the present application, the protective layer 161 located between the gate sub-layer 162 and the gate insulating layer 15 is arranged in the gate layer 16. The protective layer 161 can protect the gate insulating layer 15 from the influence of the wet etching process, and is beneficial to reducing the time of the gate insulating layer 15 exposed to the etching gas atmosphere in the dry etching process, thereby reducing the thickness loss amount of the gate insulating layer 15. In the embodiment of the present application, the thickness of the second gate insulating part 152 at any position is greater than 5 / 6 of the thickness of the first gate insulating part 151.

[0038] It should be noted that, referring to Figures 1-8The gate layer 16 includes the gate sub-layer 162 and the protection layer 161, the material of the gate sub-layer 162 can be etched by a wet etching process, the material of the protection layer 161 cannot be etched by the wet etching process, and the material of the gate sub-layer 162 and the material of the protection layer 161 can be etched by a dry etching process. For example, the material of the gate sub-layer 162 can include Mo, and the material of the protection layer 161 can include W. In the process of manufacturing the gate layer 16, a first gate material sub-layer 1610 is first deposited, the material of the first gate material sub-layer 1610 includes W, a second gate material sub-layer 1620 is deposited on the first gate material sub-layer 1610, the material of the second gate material sub-layer 1620 includes Mo, the material lattice of the first gate material sub-layer 1610 is similar to the material lattice of the second gate material sub-layer 1620, the first gate material sub-layer 1610 can induce the grain growth of the second gate material sub-layer 1620, the appearance of grain boundaries will hinder the flow of free charges, when the grain size increases, the number of grain boundaries decreases, and the resistivity will be significantly reduced. The first gate material sub-layer 1610 and the second gate material sub-layer 1620 are patterned by one wet etching process and two dry etching processes to form the gate sub-layer 162 and the protection layer 161. The wet etching process uses aluminate solution for etching, and the aluminate solution can only etch metal Mo and cannot etch metal W. That is, in the wet etching process, the first gate material sub-layer 1610 can be etched, the second gate material sub-layer 1620 cannot be etched, and the first gate material sub-layer 1610 and the second gate material sub-layer 1620 can be etched by the dry etching process. The first gate material sub-layer 1610 and the second gate material sub-layer 1620 are etched by one wet etching process and two dry etching processes to form the gate sub-layer 162 and the protection layer 161, respectively. The thickness of the protection layer 161 is less than the thickness of the gate layer 16. In the first dry etching process, since only the protection layer 161 needs to be etched at this time, compared with the conventional dry etching process which etches the gate sub-layer 162 and the protection layer 161 at the same time, the first dry etching process in the embodiment of the application only etches the protection layer 161, and the etching time is shorter. The second gate insulating portion 152 is in the etching gas atmosphere for a shorter time, so the thickness loss of the second gate insulating portion 152 is less, which is beneficial to increase the threshold voltage.

[0039] It is worth noting that the display panel can be a liquid crystal display (LCD) panel, or an organic light-emitting diode (OLED) display panel; the active layer 14 can include an oxide semiconductor or a low-temperature polysilicon semiconductor; and the gate insulating layer 15 can be made of SiNx, SiOx, or a mixture thereof.

[0040] In some embodiments, referring to Figure 1 , the active layer 14 includes an active portion 142 and a doped portion 141 adjacent to the active layer 14, a projection of the gate layer 16 on the substrate 11 covers a projection of the active portion 142 on the substrate 11, and a projection of the second gate insulating portion 152 on the substrate 11 covers a projection of the doped portion 141 on the substrate 11.

[0041] It can be understood that the array substrate 1 comprises the substrate 11, a light shielding layer 12, a buffer layer 13, the active layer 14, the gate insulating layer 15, the gate layer 16, the interlayer insulating layer 17, the source-drain layer 18, and the insulating layer 19. The light shielding layer 12 is located on the substrate 11, the buffer layer 13 is located on the substrate 11 and covers the light shielding layer 12, the active layer 14 is located on the light shielding layer 12, the gate insulating layer 15 is located on the light shielding layer 12 and covers the active layer 14, the gate layer 16 is located on the gate insulating layer 15, the interlayer insulating layer 17 is located on the gate insulating layer 15 and covers the gate layer 16, the source-drain layer 18 is located on the interlayer insulating layer 17, the source-drain layer 18 comprises a source electrode and a drain electrode, the insulating layer 19 is located on the interlayer insulating layer 17 and covers the source-drain layer 18, the insulating layer 19 can be a passivation layer, the array substrate 1 further comprises a through hole, the through hole penetrates the gate insulating layer 15 and the interlayer insulating layer 17, the active layer 14 comprises the active part 142 and the doped part 141 adjacent to the active layer 14, the source electrode and the drain electrode are overlapped with the doped part 141 of the active layer 14 through the through hole, a projection of the gate layer 16 on the substrate 11 covers a projection of the active part 142 on the substrate 11, the first gate insulating part 151 is arranged corresponding to the gate layer 16, a projection of the second gate insulating part 152 on the substrate 11 covers a projection of the doped part 141 on the substrate 11, specifically, a projection of the first gate insulating part 151 on the substrate 11 coincides with a projection of the gate layer 16 on the substrate 11, a projection of the active part 142 on the substrate 11 coincides with a projection of the gate layer 16 on the substrate 11, since the second gate insulating part 152 is not covered by the gate layer 16, in a dry etching process, the etching gas can etch the second gate insulating part 152 to cause the thickness of the second gate insulating part 152 to be less than the thickness of the first gate insulating part 151, at the same time, the gate layer 16 shields the active part 142, so as to facilitate ion doping on the part of the active layer 14 which is not shielded by the gate layer 16 to form the doped part 141.

[0042] In some embodiments, referring to Figure 1 and Figure 8The doping portion 141 comprises a first doping portion 1411 and a second doping portion 1412, and the second doping portion 1412 is located between the first doping portion 1411 and the active portion 142; the second gate insulating portion 152 comprises a first sub-portion 1521 and a second sub-portion 1522, and the second sub-portion 1522 is located between the first gate insulating portion 151 and the first sub-portion 1521, the projection of the first sub-portion 1521 on the substrate covers the projection of the first doping portion 1411 on the substrate 11, and the projection of the second sub-portion 1522 on the substrate covers the projection of the second doping portion 1412 on the substrate 11, and the thickness of the second sub-portion 1522 is greater than the thickness of the first sub-portion 1521.

[0043] It can be understood that the first doping portion 1411 can be a heavily doped portion, and the second doping portion 1412 can be a lightly doped portion, that is, the doping ion concentration of the first doping portion 1411 is greater than the doping ion concentration of the second doping portion 1412, the second doping portion 1412 is located between the active portion 142 and the first doping portion 1411, the second gate insulating portion 152 comprises the first sub-portion 1521 and the second sub-portion 1522, the second sub-portion 1522 is located between the first gate insulating portion 151 and the first sub-portion 1521, that is, the first sub-portion 1521 is arranged corresponding to the first doping portion 1411, the second sub-portion 1522 is arranged corresponding to the second doping portion 1412, the projection of the first sub-portion 1521 on the substrate covers the projection of the first doping portion 1411 on the substrate 11, the projection of the second sub-portion 1522 on the substrate covers the projection of the second doping portion 1412 on the substrate 11, the thickness loss of the second gate insulating portion 152 is caused by two dry etching processes, the thickness loss of the first sub-portion 1521 is caused by two dry etching processes, and the thickness loss of the second sub-portion 1522 is caused by one of the two dry etching processes, so the thickness of the second sub-portion 1522 is greater than the thickness of the first sub-portion 1521.

[0044] In some embodiments, referring to Figure 1 The thickness of the protective layer 161 is 5 nm to 50 nm.

[0045] It can be understood that the protective layer 161 not only protects the gate insulating layer 15 from being etched during the wet etching process, but also helps to induce the grain growth of the gate sub-layer 162 to form larger-sized grains, thereby reducing the resistivity of the gate layer 16. Therefore, the thickness of the protective layer 161 is 5 nm to 50 nm. When the thickness of the protective layer 161 is less than 5 nm, the thickness of the protective layer 161 is too small to prevent the etching liquid in the wet etching process from etching the gate insulating layer 15, and the effect of the protective layer 161 on inducing the grain growth of the gate sub-layer 162 is weakened. When the thickness of the protective layer 161 is greater than 50 nm, in the first dry etching process, the thicker the protective layer 161, the longer the time of the protective layer 161 in the etching gas atmosphere of the dry etching process, and the greater the thickness loss of the gate insulating layer 15, which has a greater impact on the threshold voltage. In addition, the greater the thickness of the protective layer 161, the greater the thickness of the gate layer 16, which is not conducive to the thinning design of the display panel. Therefore, the thickness of the protective layer 161 is 5 nm to 50 nm.

[0046] In some embodiments, referring to Figure 1 , the display panel includes a display area AA and a non-display area AZ adjacent to the display area AA, and the gate layer 16 includes a plurality of test gates 1601 located in the non-display area AZ, and the spacing between two adjacent test gates 1601 is less than 2 μm.

[0047] It can be understood that the display panel includes the display area AA and a non-display area adjacent to the display area AA, and the gate layer 16 includes a plurality of test gates 1601 located in the non-display area AZ, and the gate layer 16 also includes a gate located in the display area AA. The gate and the test gate 1601 are made by the same manufacturing process, the test gate 1601 is connected to the gate through a wire, and the test gate 1601 is connected to an electrical signal test device to detect the electrical parameters of the gate. Since the gate layer 16 is made by one wet etching process and two dry etching processes, the time of the array substrate 1 in the etching gas atmosphere of the dry etching process is greatly reduced, and the side etching effect of the dry etching process on the gate layer 16 is weakened. In other words, compared with the metal gate layer made by only two dry etching processes, the difference between the actual size and the design size of the test gate 1601 is smaller in the present application, the spacing between two adjacent test electrodes is less than 2 μm in the present application, that is, the spacing between two adjacent test electrodes is reduced, and the test gate 1601 is located in the frame area. The reduction of the spacing between the test gates 1601 is conducive to the reduction of the width of the frame, and is more conducive to the realization of narrow frame.

[0048] In some embodiments, referring to Figure 1 The thickness of the first gate insulation part 151 is 100-150 nm, and the thickness of the second gate insulation part 152 at any position is less than the thickness of the first gate insulation part 151.

[0049] It can be understood that the thickness of the first gate insulation part 151 is 100-150 nm, the thickness of the second gate insulation part 152 at any position is greater than 5 / 6 of the thickness of the first gate insulation part 151, and the thickness of the second gate insulation part 152 at any position is less than the thickness of the first gate insulation part 151.

[0050] In the embodiments of the present application, the thickness loss of the gate insulation layer of the display panel is significantly reduced. Referring to Table 1, the display panel in the embodiments of the present application is the example, and the display panel using only two dry etching processes to manufacture the gate film layer is the comparative example. The thickness of the first gate insulation part is 120 nm, i.e., the original manufacturing size of the gate insulation layer before the thickness loss is 120 nm. It can be seen from the test data that the thickness loss of the gate insulation layer of the display panel in the embodiments of the present application is 15-19 nm, and the thickness loss of the gate insulation layer of the display panel using only two dry etching processes to manufacture the gate film layer is 25-35 nm. The one wet etching process and two dry etching processes used in the embodiments of the present application have less effect on the thickness of the gate insulation layer.

[0051]

[0052] Table 1 Thickness loss of gate insulation layer

[0053] Referring to Figures 2-8 The embodiments of the present application provide a manufacturing method of a display panel, which comprises the following steps:

[0054] S10: providing a substrate 11, and forming an active layer 14 on the substrate 11;

[0055] S20: forming a gate insulation layer 15 on the active layer 14, the gate insulation layer 15 comprising a first gate insulation part 151 and a second gate insulation part 152 adjacent to the first gate insulation part 151, and the thickness of the second gate insulation part 152 at any position is greater than 5 / 6 of the thickness of the first gate insulation part 151;

[0056] Specifically, the material of the gate insulating layer 15 includes SiNx, SiOx or a mixture, the gate insulating layer 15 includes the first gate insulating part 151 and the second gate insulating part 152 adjacent to the first gate insulating part 151, the thickness of the second gate insulating part 152 at any position is greater than 5 / 6 of the thickness of the first gate insulating part 151, and the thickness of the second gate insulating part 152 at any position is less than the thickness of the first gate insulating part 151.

[0057] S30: forming a gate layer 16 on the gate insulating layer 15, the gate layer 16 including a gate sub-layer 162 and a protective layer 161, the protective layer 161 being located between the gate sub-layer 162 and the gate insulating layer 15, and the first gate insulating part 151 being arranged corresponding to the gate layer 16.

[0058] Specifically, the material lattice of the protective layer 161 is similar to the material lattice of the gate sub-layer 162, for example, the material of the gate sub-layer 162 includes Mo, the material of the protective layer 161 includes W, the thickness of the protective layer 161 is less than the thickness of the gate sub-layer 162, the protective layer 161 is located between the gate sub-layer 162 and the gate insulating layer 15, and the first gate insulating part 151 is arranged corresponding to the gate layer 16.

[0059] In some embodiments, the step of forming the gate layer 16 on the gate insulating layer 15 further includes:

[0060] forming a first gate material sub-layer 1610, a second gate material sub-layer 1620 and an organic photoresist 110 on the gate insulating layer 15 in sequence;

[0061] Specifically, referring to Figure 3 forming the first gate material sub-layer 1610, the second gate material sub-layer 1620 and the organic photoresist 110 on the gate insulating layer 15 in sequence, the organic photoresist 110 being located on the first gate material sub-layer 1610 and covering part of the first gate material sub-layer 1610, and the width of the organic photoresist 110 being 1.5 μm to 2.3 μm.

[0062] patterning the second gate material sub-layer 1620 to form a second gate material layer 1621 by using a wet etching process;

[0063] Specifically, referring to Figure 4The etching solution of the wet etching process is aluminate solution, the material of the second gate material sub-layer 1620 includes Mo, the material of the first gate material sub-layer 1610 includes W, the aluminate solution can etch the second gate material sub-layer 1620, the aluminate solution cannot etch the first gate material sub-layer 1610, that is, the second gate material sub-layer 1620 is patterned by the wet etching process to form the second gate material layer 1621, and in the wet etching process, the organic photoresist 110 is soaked in the aluminate solution, the organic photoresist 110 will have a certain volume expansion, that is, the projection of the organic photoresist 110 on the gate insulating layer 15 covers the projection of the second gate material layer 1621 on the gate insulating layer 15, and the area of the organic photoresist 110 is greater than the area of the second gate material layer 1621.

[0064] The first gate material sub-layer 1610 is patterned by the first dry etching process to form a first gate material layer 1611.

[0065] Specifically, referring to Figures 5-6 The first gate material sub-layer 1610 is etched by the first dry etching process, at this time, mainly the part of the first gate material sub-layer 1610 which is not shielded by the organic photoresist 110 is etched to expose part of the second gate insulating part 152, because the thickness of the protection layer 161 is less than the thickness of the gate sub-layer 162, the time for etching the first gate material sub-layer 1610 by the first dry etching process is greatly reduced, that is, the time for the gate insulating layer 15 to be in the etching gas atmosphere is reduced, and the thickness loss of the gate insulating layer 15 is reduced.

[0066] The second gate material layer 1621 and the first gate material layer 1611 are patterned by the second dry etching process to form the gate sub-layer 162 and the protection layer 161, respectively.

[0067] Specifically, referring to Figures 7-8The second dry etching process is used to etch the organic photoresist 110, the second gate material layer 1621 and the first gate material layer 1611, so as to completely expose the second gate insulation part 152. The etching parameters of the first dry etching process and the second dry etching process are different, including the composition of etching gas, the concentration of etching gas and etching time, etc. Compared with the conventional gate layer 16 which is manufactured by using only two dry etching processes, the thickness of the second gate material layer 1621 is greater than the thickness of the first gate material layer 1611 in the embodiment of the application. In the second dry etching process, the etching time of the second gate material layer 1621 plays a leading role. Since the etching gas of the first dry etching process has a small amount of side etching effect on the second gate material layer 1621, the etching time required for etching the second gate material layer 1621 to form the gate sub-layer 162 with a certain size is reduced. The influence of the etching gas atmosphere on the gate insulation layer 15 is weakened, and the thickness loss of the gate insulation layer 15 is reduced.

[0068] In some embodiments, the etching time of the first dry etching process is less than the etching time of the second dry etching process.

[0069] It can be understood that, since the first dry etching process only etches the first gate material sub-layer 1610, and the second dry etching process etches the organic photoresist 110, the second gate material layer 1621 and the first gate material layer 1611, the thickness of the first gate material sub-layer 1610 is equal to the thickness of the first gate material layer 1611, and the thickness of the first gate material sub-layer 1610 is less than the thickness of the first gate material layer 1611. The thickness and the etching time are in a positive correlation, therefore, the etching time of the first dry etching process is less than the etching time of the second dry etching process.

[0070] In some embodiments, the step of using the first dry etching process to pattern the first gate material sub-layer 1610 to form the first gate material layer 1611 further comprises:

[0071] The active layer 14 is ion doped to form a first doped part 1411 of the active layer 14.

[0072] Specifically, referring to Figures 5-6The first gate material sub-layer 1610 is etched by a first dry etching process to expose part of the second gate insulating part 152. The exposed part of the second gate insulating part 152 is used for ion doping to form the first doping part 1411 of the active layer 14. The first doping part 1411 of the active layer 14 is formed under the action of a certain voltage. The ion doping process shares the manufacturing process of the gate layer 16, and one photo mask process is saved, thereby saving the production cost.

[0073] In the embodiment of the present application, the protection layer 161 is arranged between the gate sub-layer 162 and the gate insulating layer 15. The protection layer 161 can protect the gate insulating layer 15 from the wet etching process, and is beneficial to reducing the time of the gate insulating layer 15 exposed to the etching gas atmosphere in the dry etching process, thereby reducing the time of the gate insulating layer 15 in the etching gas atmosphere, and reducing the thickness loss of the gate insulating layer 15. In the embodiment of the present application, the thickness of the second gate insulating part 152 at any position is greater than 5 / 6 of the thickness of the first gate insulating part 151.

[0074] The above detailed the embodiments of the present application. The specific examples are applied to explain the principles and implementation modes of the present application. The above embodiment is only used to help understand the method and the core idea of the present application. Meanwhile, according to the idea of the present application, the specific implementation mode and the application range can be changed by the person skilled in the art. The above description should not be understood as the limitation of the present application.

Claims

1. A display panel, characterized in that, Includes an array substrate, the array substrate comprising: Substrate; An active layer is located on the substrate; A gate insulating layer is located on the active layer, and the gate insulating layer includes a first gate insulating portion and a second gate insulating portion adjacent to the first gate insulating portion; A gate layer is located on the gate insulating layer, the gate layer includes a gate sub-layer and a protective layer, the protective layer being located between the gate sub-layer and the gate insulating layer; Wherein, the first gate insulating portion is disposed corresponding to the gate layer, and the thickness of the second gate insulating portion at any position is greater than 5 / 6 of the thickness of the first gate insulating portion; The active layer includes an active portion and a doped portion adjacent to the active portion, and the projection of the gate layer on the substrate covers the projection of the active portion on the substrate. The thickness of the protective layer is less than the thickness of the gate sublayer; The projection of the gate sublayer onto the substrate falls within the projection of the protective layer onto the substrate.

2. The display panel according to claim 1, characterized in that, The projection of the second gate insulating portion on the substrate covers the projection of the doped portion on the substrate.

3. The display panel according to claim 2, characterized in that, The doped portion includes a first doped portion and a second doped portion, wherein the second doped portion is located between the first doped portion and the active portion; The second gate insulating portion includes a first sub-portion and a second sub-portion, the second sub-portion being located between the first gate insulating portion and the first sub-portion, the projection of the first sub-portion on the substrate covering the projection of the first doped portion on the substrate, the projection of the second sub-portion on the substrate covering the projection of the second doped portion on the substrate, and the thickness of the second sub-portion being greater than the thickness of the first sub-portion.

4. The display panel according to claim 1, characterized in that, The thickness of the protective layer is 5nm to 50nm.

5. The display panel according to claim 1, characterized in that, The display panel includes a display area and a non-display area adjacent to the display area. The gate layer includes a plurality of test gates located in the non-display area, and the spacing between two adjacent test gates is less than 2 μm.

6. The display panel according to claim 1, characterized in that, The thickness of the first gate insulating portion is 100-150 nm, and the thickness of the second gate insulating portion at any point is less than the thickness of the first gate insulating portion.

7. A method for manufacturing a display panel, characterized in that, Includes the following steps: A substrate is provided, on which an active layer is formed; A gate insulating layer is formed on the active layer. The gate insulating layer includes a first gate insulating portion and a second gate insulating portion adjacent to the first gate insulating portion. The thickness of the second gate insulating portion at any position is greater than 5 / 6 of the thickness of the first gate insulating portion. A gate layer is formed on the gate insulating layer. The gate layer includes a gate sub-layer and a protective layer. The protective layer is located between the gate sub-layer and the gate insulating layer. The first gate insulating portion is disposed corresponding to the gate layer. The active layer includes an active portion and a doped portion adjacent to the active portion, and the projection of the gate layer on the substrate covers the projection of the active portion on the substrate. The thickness of the protective layer is less than the thickness of the gate sublayer; The projection of the gate sublayer onto the substrate falls within the projection of the protective layer onto the substrate.

8. The method for manufacturing a display panel according to claim 7, characterized in that, The step of forming a gate layer on the gate insulating layer further includes: A second gate material sublayer, a first gate material sublayer, and an organic photoresist are sequentially formed on the gate insulating layer. The first gate material sublayer is patterned using a wet etching process to form the first gate material layer; The second gate material sublayer is patterned using a first dry etching process to form the second gate material layer; The first gate material layer and the second gate material layer are patterned using a second dry etching process to form the gate sub-layer and the protective layer, respectively.

9. The method for manufacturing a display panel according to claim 8, characterized in that, The etching time of the first dry etching process is shorter than that of the second dry etching process.

10. The method for manufacturing a display panel according to claim 8, characterized in that, Following the step of patterning the second gate material sublayer using a first dry etching process to form the second gate material layer, the method further includes: The active layer is ion-doped to form a first doped portion of the active layer.

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