A p-type tungsten diselenide field effect transistor based on 3R phase and a preparation method thereof

Abstract

The application discloses a p-type tungsten diselenide field effect transistor based on 3R phase and a preparation method thereof, and belongs to the technical field of semiconductor devices. The device comprises a p-type doped silicon substrate, a silicon dioxide gate dielectric arranged on the p-type doped silicon substrate, a 3R phase double-layer tungsten diselenide channel material arranged on the silicon dioxide gate dielectric, and source-drain electrodes arranged on the surface of the 3R phase double-layer tungsten diselenide channel material. Meanwhile, a preparation method of the p-type tungsten diselenide field effect transistor based on 3R phase is provided. The p-type tungsten diselenide field effect transistor based on 3R phase prepared by the application can improve the electrical performance of the field effect transistor, and is beneficial to large-scale device integration of transition metal chalcogenides in the future.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor devices, and more particularly relates to a p-type tungsten diselenide field effect transistor based on a 3R phase and a preparation method thereof. BACKGROUND

[0002] Two-dimensional (2D) transition metal dichalcogenides (TMDCs) have been the subject of intense research due to their potential applications in optoelectronics and transistors below 10 nanometers. Tungsten diselenide, as one of the transition metal dichalcogenide materials, has a bipolar transport behavior and has a wide application prospect in integrated circuits. Double-layer tungsten diselenide can provide better metal contact and less interface scattering than single-layer, with higher carrier mobility and smaller band gap, while maintaining ultra-thin properties.

[0003] In the prior art, 2H stacking, as the most stable structure among various stacking structures and the most easily obtained stacking structure, has always been considered as the main choice of channel material, but through the research of the present application, the electrical performance of the existing field effect transistor device can be improved. SUMMARY

[0004] In view of the defects and improvement needs of the prior art, the present application provides a p-type tungsten diselenide field effect transistor based on a 3R phase and a preparation method thereof, which aims to improve the electrical performance of the field effect transistor.

[0005] To achieve the above-mentioned purpose, according to one aspect of the present application, a p-type tungsten diselenide field effect transistor based on a 3R phase is provided, comprising: a p-type doped silicon substrate, a silicon dioxide gate dielectric disposed on the p-type doped silicon substrate, a 3R phase double-layer tungsten diselenide channel material disposed on the silicon dioxide gate dielectric, and a source-drain electrode disposed on the surface of the 3R phase double-layer tungsten diselenide channel material.

[0006] Further, the thickness of the 3R phase double-layer tungsten diselenide channel material is 1.4 nanometers.

[0007] Further, the thickness of the silicon dioxide gate dielectric is 5-300 nanometers.

[0008] Further, the source-drain electrode comprises a bottom layer contact metal and an upper layer metal.

[0009] The bottom layer contact metal material is one of nickel, platinum, and palladium.

[0010] The upper layer metal material is one of gold, silver, palladium, osmium, iridium, platinum, gold, titanium, aluminum, chromium, germanium, molybdenum, nickel, tungsten, copper, cobalt, or iron.

[0011] Furthermore, the bottom contact metal material is nickel with a thickness of 10-30 nanometers, and the top metal material is gold with a thickness of 30-60 nanometers.

[0012] According to another aspect of the present invention, a method for fabricating a tungsten diselenide field-effect transistor based on the 3R phase as described in any one of the first aspects is provided, the method comprising:

[0013] Step S1: Clean the silicon substrate with p-type doping and silicon dioxide surface, and perform high-temperature rapid annealing;

[0014] Step S2: Use salt-assisted chemical vapor deposition to grow a double layer of tungsten diselenide with 3R and 2H phases;

[0015] Step S3: Prepare a labeling layer for the bilayer tungsten diselenide of the 3R phase and 2H phase;

[0016] Step S4, Isolation region etching, includes: using a marker layer to locate the position of the 3R phase double-layer tungsten diselenide, and defining an active region and an isolation region on the surface of the 3R phase double-layer tungsten diselenide;

[0017] Step S5: Prepare source and drain electrodes on the surface of the 3R phase double-layer tungsten diselenide.

[0018] Furthermore, in step S1, during the high-temperature rapid annealing process of the silicon substrate, a high-temperature rapid annealing furnace is used, with an annealing temperature of 850-1050 degrees Celsius and an annealing time of 1 minute.

[0019] Furthermore, in step S4, the etching is reactive ion etching.

[0020] Further, in step S2, the conditions for salt-assisted chemical vapor deposition are as follows: potassium chloride mass 0-5 mg, tungsten dioxide mass 30-50 mg, sulfur elemental powder mass 100-300 mg, growth temperature 850-1050 degrees Celsius, argon gas flow rate of 90-110 standard flow rate and hydrogen gas flow rate of 8-12 standard flow rate, growth pressure 1000-2500 Pa, and growth time 10-20 minutes.

[0021] Furthermore, in step S3, the material of the marking layer includes a bottom contact metal and an upper metal: the bottom contact metal is 20 nanometers of nickel, and the upper metal is 40 nanometers of gold.

[0022] In summary, the above-described technical solutions conceived in this invention can achieve the following beneficial effects:

[0023] (1) This invention proposes to directionally select 3R phase tungsten diselenide as the channel material when fabricating field-effect transistors based on tungsten diselenide to improve the electrical performance of the field-effect transistor and maintain the consistency of device performance. This makes up for the lack of subjective selection of the stacking structure of the channel material in the prior art. At the same time, in the prior art, tungsten diselenide has a variety of stacking structures, but most of the tungsten diselenide obtained by chemical vapor deposition is 3R stacking with 0-degree turn and 2H stacking with 60-degree turn. Other double-layer structures cannot be obtained in a controllable manner due to poor stability. 2H stacking, as the most stable structure among the various stacking structures, is also the easiest to obtain and has always been considered the main choice for channel material. This invention negates the idea that a more stable structure represents better electronic properties, and also negates the technical understanding that the same number of layers but different stacking structures have consistent electronic properties. It overcomes technical bias and selects 3R stacking with better electrical properties as the channel material of the field-effect transistor, thereby improving the electrical performance of the field-effect transistor and facilitating the large-scale device integration of transition metal chalcogenides in the future.

[0024] (2) This invention avoids the pollution and impact on material quality introduced by traditional transfer methods by preparing devices in situ on tungsten diselenide obtained by direct growth, reduces the complexity of the process, preserves the intrinsic properties of double-layer tungsten diselenide to the greatest extent possible, and improves electrical performance.

[0025] In summary, the 3R phase-based tungsten diselenide field-effect transistor and its fabrication method of the present invention can promote the research on transition metal dichalcogenides such as tungsten diselenide and the application of bilayer tungsten diselenide in integrated circuits. Attached Figure Description

[0026] Figure 1 A schematic diagram of a p-type tungsten diselenide field-effect transistor based on the 3R phase provided in an embodiment of the present invention.

[0027] Figure 2 A schematic diagram of a p-type tungsten diselenide field-effect transistor based on the 2H phase provided in an embodiment of the present invention.

[0028] Figure 3 This is an optical microscope image of a double-layered tungsten diselenide with 3R and 2H stacks on 100 nm silicon dioxide obtained in an embodiment of the present invention.

[0029] Figure 4 The photoluminescence spectrum data of double-layer tungsten diselenide obtained in an embodiment of the present invention are shown below. Figure 4 In the figure, (a) and (b) represent the photoluminescence spectra of bilayer tungsten diselenide in the 2H phase and 3R phase, respectively.

[0030] Figure 5The present invention provides Raman spectral data of double-layered tungsten diselenide obtained in an embodiment of the invention, wherein... Figure 5 In the figure, (a) and (b) represent the Raman spectra of the 2H phase and the 3R phase of the double-layer tungsten diselenide, respectively.

[0031] Figure 6 The low wavenumber Raman spectral data of double-layer tungsten diselenide obtained in the embodiments of the present invention are shown below. Figure 5 In the figure, (a) and (b) represent the low wavenumber Raman spectra of the 2H phase and 3R phase of the double-layer tungsten diselenide, respectively.

[0032] Figure 7 The output characteristic curve of the field-effect transistor prepared according to an embodiment of the present invention. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0034] Example 1

[0035] like Figure 1 As shown, the 3R-phase p-type tungsten diselenide field-effect transistor provided by the present invention comprises, from bottom to top: a p-type doped silicon substrate, a silicon dioxide gate dielectric disposed on the p-type doped silicon substrate, a 3R-phase double-layer tungsten diselenide channel material disposed on the silicon dioxide gate dielectric, and source and drain electrodes disposed on the surface of the 3R-phase double-layer tungsten diselenide channel material.

[0036] The thickness of the 3R phase double-layer tungsten diselenide channel material is 1.4 nanometers.

[0037] The thickness of the silicon dioxide gate dielectric is 5-300 nanometers.

[0038] The source / drain electrode includes a bottom contact metal and an upper metal layer. The bottom contact metal material is one of nickel, platinum, and palladium, and the upper metal material is one of gold, silver, palladium, osmium, iridium, platinum, gold, titanium, aluminum, chromium, germanium, molybdenum, nickel, tungsten, copper, cobalt, or iron. In this embodiment, the bottom contact metal material of the source / drain electrode is nickel, and the upper metal material is gold. The thickness of nickel is 10-30 nanometers, and the thickness of gold is 30-60 nanometers.

[0039] Example 2

[0040] This invention provides a method for fabricating a tungsten diselenide field-effect transistor based on the 3R phase, wherein the field-effect transistor is the tungsten diselenide field-effect transistor based on the 3R phase in Example 1, and the fabrication method includes the following steps:

[0041] Step S1: Clean the silicon substrate with p-type doping and silicon dioxide surface, and perform high-temperature rapid annealing; specifically, during the high-temperature rapid annealing process of the silicon substrate, a high-temperature rapid annealing furnace (RTA) is used, the annealing temperature is 850-1050 degrees Celsius, and the annealing time is 1 minute.

[0042] Step S2: A double layer of 3R phase and 2H phase tungsten diselenide is grown by salt-assisted chemical vapor deposition; wherein, tungsten diselenide is grown directly on a silicon substrate with p-type doping and a silicon dioxide surface.

[0043] Step S3: Prepare a marker layer (Mark) from the double-layer tungsten diselenide in step S2; specifically, the marker layer is metal, with a bottom layer of 20 nanometer nickel and an upper layer of 40 nanometer gold.

[0044] Step S4: Etching of the isolation area. The location of the 3R phase double-layer tungsten diselenide is determined by the marker layer. The active area and the isolation lead metal area are defined on the surface of the 3R phase double-layer tungsten diselenide. The resist is then homogenized, exposed by electron beam and developed, etched, and the resist is removed.

[0045] Step S5: Prepare source and drain electrodes on the surface of a 3R phase double-layer tungsten diselenide; specifically including: spin coating, electron beam exposure and development, metal deposition, and stripping to prepare the source and drain layers to obtain a field-effect transistor.

[0046] In step S2, the deposition conditions for growing a double-layer tungsten diselenide stacked by 3R and 2H using salt-assisted chemical vapor deposition are as follows: molten salt is potassium chloride, with a mass of 0-5 mg; tungsten source is tungsten dioxide, with a mass of 30-50 mg; sulfur source is elemental sulfur powder, with a mass of 100-300 mg; growth temperature is 850-1050 degrees Celsius; argon gas is introduced at a standard flow rate of 90-110 kPa and hydrogen gas at a standard flow rate of 8-12 kPa; growth pressure is 1000-2500 Pa; and growth time is 10-20 minutes.

[0047] In this process, potassium chloride and tungsten dioxide are mixed and placed in an alumina boat, on which a silicon dioxide substrate is placed upside down. During growth, the alumina boat is located in the center of the heating furnace. Selenium powder is placed in a ceramic boat, which is located at the edge of the heating furnace during growth. The heating furnace heats up downstream, and once the temperature reaches the growth temperature, it slides upstream for heat preservation to begin the growth timer. By adding potassium chloride to the tungsten dioxide, the reaction temperature can be lowered.

[0048] Preferably, the mass ratios of potassium chloride, tungsten dioxide, and elemental sulfur powder are 2 mg, 40 mg, and 200 mg, respectively, which can serve as stable growth conditions. Preferably, the growth temperature is 890°C, the growth pressure is maintained at a low pressure of 1700 Pa, and argon gas at a standard flow rate of 105 and hydrogen gas at a standard flow rate of 8 are introduced during growth. Under the preferred growth temperature, growth pressure, and potassium chloride / tungsten dioxide mass ratio, the molten mixture of potassium chloride and tungsten dioxide can reach its melting point to obtain growth nuclei, and the growth requirements of double-layer tungsten diselenide are met without exceeding the expected number of layers. Under the preferred tungsten dioxide to selenium powder mass ratio, tungsten diselenide can continuously grow around the nuclei and reach a considerable size while maintaining a regular morphology.

[0049] Preferably, a silicon substrate with a surface layer of 100 nm silica and a thickness of approximately 500 μm is selected. The substrate is annealed for 1 minute in a high-temperature rapid annealing furnace (RTA) at 890°C, the same temperature as the tungsten diselenide growth temperature. This heat treatment of the silicon substrate improves the amorphous structure of the silica, which is beneficial for better lattice matching during tungsten diselenide growth on its surface, thus improving the quality of the grown tungsten diselenide material. Preferably, in step S4, reactive ion etching is used for the etching of the isolation region.

[0050] In this embodiment, step S1 specifically includes:

[0051] Step S11: Add 150 ml of deionized water and 30 ml of ammonia to a glass dish and heat it to 70 degrees Celsius on a hot plate. Then add 30 ml of hydrogen peroxide and continue heating. When bubbles start to appear from the bottom after 7-10 minutes, place a silicon wafer with a surface of 100 nanometers of silica into the dish and start timing for 10 minutes. After 10 minutes, remove the wafer and immerse it in deionized water. Then remove the silicon wafer and rinse it with deionized water. When rinsing, tilt the silicon wafer towards the tweezers so that the deionized water flows from the higher part to the tweezers to prevent dirt from the tweezers from remaining on the silicon wafer. Dry the silicon wafer with a nitrogen gun.

[0052] Step S12, substrate high-temperature rapid annealing: Place the cleaned silicon wafer into a high-temperature rapid annealing furnace, set the heating curve, hold at 890 degrees Celsius for 1 minute, and then let it cool naturally to room temperature; cut the silicon wafer into substrates of 1*1 cm size.

[0053] Step S2 specifically includes:

[0054] Step S21, Weighing and Placing: Weigh 200 mg of selenium powder into a ceramic boat (selenium powder mass fraction greater than or equal to 99.5%); weigh 40 mg of tungsten dioxide into a corundum boat (tungsten dioxide mass fraction 99.99%); weigh 3 mg of potassium chloride and mix it with tungsten dioxide (potassium chloride mass fraction 99.999%); place the substrate face down on top of the tungsten dioxide and potassium chloride mixture; turn on the chemical vapor deposition system and introduce argon gas to break the vacuum; push the corundum boat into the center of the quartz tube furnace and push the ceramic boat into the pre-tested and calibrated position at the edge of the quartz tube furnace; evacuate to below 10 Pa.

[0055] Step S22, Chemical Vapor Deposition: Introduce argon at a rate of 105 standard milliliters per minute and hydrogen at a rate of 10 standard milliliters per minute. Turn on the furnace and heat to 890 degrees Celsius downstream of the quartz tube. Once the temperature is reached, slide the furnace upstream. At this point, the tungsten source is located in the center of the furnace. The reaction time is 15 minutes, during which the angle valve is continuously adjusted to stabilize the pressure at around 1700 Pa. After the time is up, turn off the furnace and slide it downstream for natural cooling. At the same time, turn off the hydrogen and fully open the angle valve. After natural cooling, introduce argon to break the vacuum and remove the ceramic boat and corundum boat. The growth stage is complete.

[0056] Step S3 specifically includes: dripping polymethyl methacrylate (PMMA) electron beam photoresist onto the surface of a silicon wafer with grown tungsten diselenide, and homogenizing the coating at 3000 rpm for 60 seconds; then drying it on a hot plate at 180 degrees Celsius for 90 seconds; exposing the marking layer pattern using an electron beam evaporation (EBL) device; immersing the silicon wafer in a developer solution with a mass ratio of methyl isobutyl ketone (MIBK) to isopropanol (IPA) of 1:3 for 50 seconds, then rinsing it with isopropanol and drying it with a nitrogen gun; performing metal deposition using an electron beam evaporation (EBE) device, depositing 20 nm of nickel and 40 nm of gold; immersing it in an acetone solution at 50 degrees Celsius for 30 minutes, rinsing it with a syringe until all excess metal is removed, then rinsing it with isopropanol and drying it with a nitrogen gun.

[0057] Step S4 specifically includes: drawing the active and isolation regions; applying AR-P617 electron beam photoresist to the silicon wafer surface; homogenizing the photoresist at 4000 rpm for 60 seconds; drying the photoresist on a hot plate at 150 degrees Celsius for 60 seconds; exposing the isolation region layout using an electron beam exposure device; etching using a reactive ion etching (RIE) device at a power of 3 watts for 6 minutes; immersing the photoresist in an N-methylpyrrolidone (NMP) solution for 12 hours to remove the photoresist; then rinsing with isopropanol and drying with a nitrogen gun; continuing to remove the photoresist using a high-temperature annealing furnace at a temperature of 300 degrees Celsius for 2 hours, during which 100 standard milliliters of argon gas are introduced.

[0058] Step S5 specifically includes: the spin coating, electron beam exposure and development processes are the same as those for the S3 marking layer; source and drain metal deposition is performed using an electron beam evaporation device, depositing 20 nm of nickel and 40 nm of gold; immersion in acetone solution at 50 degrees Celsius for 30 minutes, rinsing with a syringe until all excess metal is removed, then immersion in isopropanol for cleaning, and drying with a nitrogen gun, thus completing the device fabrication.

[0059] Using the above method, a double-layer tungsten diselenide with 3R and 2H stacking can be obtained on a silicon wafer. Tungsten disulfide is observed and characterized using optical microscopy, Raman spectroscopy, low-wavenumber Raman spectroscopy, and photoluminescence spectroscopy. 3R-stacked double-layer tungsten diselenide is selected, and a back-gate field-effect transistor is fabricated on top of it, resulting in a 3R-phase-based double-layer tungsten diselenide field-effect transistor, such as... Figure 1 As shown.

[0060] Similarly, in the above preparation method, in steps S4 and S5, the position of the 2H phase double-layer tungsten diselenide is determined using a marker layer, and source and drain electrodes are fabricated on the surface of the 2H phase double-layer tungsten diselenide, resulting in a 2H phase-based double-layer tungsten diselenide field-effect transistor, such as... Figure 2 As shown.

[0061] An optical microscope image of the 3R and 2H stacked tungsten diselenide bilayer prepared in step S2 is shown below. Figure 3 As shown, the color of the double-layer region is darker than that of the single-layer region. The double-layer region without a corner between the single layer and the double-layer region is a 3R stacked structure, while the double-layer region with a 60-degree corner between the single layer and the double-layer region is a 2H stacked structure. The size of the double-layer region is mostly around 40 micrometers.

[0062] To better distinguish between 3R and 2H stacked bilayer tungsten diselenide, in this embodiment, photoluminescence spectroscopy, Raman spectroscopy, and low wavenumber Raman spectroscopy were performed on the single-layer and bilayer regions of the two stacks on a 100 nm silicon dioxide substrate. The laser used was 532 nm.

[0063] The photoluminescence spectral data of the double-layer tungsten diselenide obtained in the embodiments of the present invention are as follows: Figure 4 As shown in (a) and (b), the band gap of the single-layer region of both stacks is 1.60 eV, with high peak intensity, exhibiting obvious direct band gap characteristics. The peak intensity of the double layer is plotted by magnification by 20 times. The double-layer tungsten diselenide has two peaks, the main peak being the direct transition peak and the secondary peak being the indirect transition peak. The difference between the two stacks lies in the indirect transition peak of the double-layer region. The indirect transition band gap of the 3R stack is 1.55 eV, while that of the 2H stack is 1.56 eV. The indirect transition band gap of the 3R stack is smaller than that of the 2H stack.

[0064] Raman spectral data of double-layer tungsten diselenide obtained in the embodiments of the present invention are as follows: Figure 5As shown in (a) and (b), the main characteristic peaks of tungsten diselenide are at wavenumbers of 248.5 and 260, respectively, corresponding to A 1g Vibrational modes and 2LA vibrational modes; the difference between the two stacked Raman spectra is that the intensity of the 3R stacked bilayer is weaker than that of the monolayer, being half that of the monolayer; while the intensity of the 2H stacked bilayer is stronger than that of the monolayer, being 2 to 3 times stronger than that of the monolayer.

[0065] Low wavenumber Raman spectra of double-layer tungsten diselenide, such as Figure 6 As shown in (a) and (b), the Raman spectra in the low wavenumber range reveal layer-to-layer shear vibration modes (S) and breathing vibration modes (LB). In the monolayer region, no peaks appear because there is no interlayer vibration. In the bilayer region, there is a clear difference: the shear vibration mode and breathing vibration mode of the 3R stack are located at wavenumbers of 15.3 and 26.4, respectively, with a weak shear vibration peak. In the 2H stack, the shear vibration mode and breathing vibration mode are located at wavenumbers of 16.4 and 28.5, respectively, with the peak intensity of the shear vibration being about three times that of the breathing vibration.

[0066] The electrical performance of tungsten diselenide (TDS) field-effect transistors (FETs) based on the 2H phase and the 3R phase was tested using a B1500A semiconductor parameter analyzer and a low-temperature probe station. The output current curves of the 3R and 2H stacked TDS FETs are shown below. Figure 7 As shown, the calculated mobility of the 3R stacked double-layer tungsten diselenide back-gate field-effect transistor is 140 cm⁻¹. 2 V -1 s -1 The field-effect mobility of the 2H stacked bilayer tungsten diselenide is 93 cm⁻¹. 2 V -1 s -1 The performance of the p-type tungsten diselenide field-effect transistor is significantly lower than that of the 3R stack. Therefore, by choosing 3R stacking, the performance of the p-type tungsten diselenide field-effect transistor can be effectively improved. Thus, this invention selects a 3R stacked double-layer tungsten diselenide as the channel material to fabricate the field-effect transistor.

[0067] This invention avoids the pollution and impact on material quality introduced by traditional transfer methods by fabricating devices in situ on tungsten diselenide obtained through direct growth, reduces process complexity, preserves the intrinsic properties of double-layered tungsten diselenide to the greatest extent possible, and improves electrical performance.

[0068] Meanwhile, experiments have also revealed that double-layer tungsten diselenide can provide better metal ohmic contact and achieve greater source and drain current compared to single-layer tungsten diselenide, while also having a thinner thickness than multi-layer tungsten diselenide to meet the needs of continuously scaling transistor sizes.

[0069] The single layer of bilayer tungsten diselenide has a thickness of three atomic layers and exhibits a triangular prism geometry. The outer sulfur atoms are covalently bonded to the central tungsten atoms. The layers are controlled by van der Waals forces, which are relatively weak and allow sliding and rotation between adjacent layers, resulting in different stacking structures. The electronic properties of the material are highly sensitive to the interactions between the bilayers. Different stacking structures will alter the conduction band minimum (CBM) and conduction band maximum (VBM), and the direct and indirect band gaps of bilayer tungsten diselenide will differ, significantly affecting transport characteristics. Therefore, the stacking mode can be used as a key parameter for adjusting electrical performance.

[0070] This invention compares the electrical test results of fabricated 3R stacked field-effect transistors with those of 2H stacked field-effect transistors, and finds that 3R stacking exhibits superior electrical performance. This is primarily reflected in the mobility of the 3R stacked bilayer tungsten diselenide back-gate field-effect transistor, which reaches 140 cm⁻¹. 2 V -1 s -1 The field-effect mobility of the 2H stacked bilayer tungsten diselenide is 93 cm⁻¹. 2 V - 1 s -1 The electrical performance of the effect transistor is significantly lower than that of a 3R stack. Therefore, this invention utilizes a 3R stacked double-layer tungsten diselenide to fabricate the effect transistor, thereby improving its electrical performance.

[0071] This invention proposes a method for directionally selecting 3R-phase tungsten diselenide as the channel material in the fabrication of field-effect transistors (FETs) to improve their electrical performance while maintaining consistent device performance. This addresses the deficiency in existing technologies regarding the lack of subjective selection of channel materials. Furthermore, in existing technologies, 2H stacking, being the most stable and readily available stacking structure, has long been considered the primary choice for channel materials. This invention negates the notion that a more stable structure necessarily represents better electronic properties, and also rejects the notion that different stacking structures with the same number of layers possess consistent electronic properties. By overcoming this technological bias, it selects 3R stacking, which offers superior electrical properties, as the channel material for FETs, thereby improving their electrical performance and facilitating the large-scale device integration of transition metal dichalcogenides (TDCs) in the future.

[0072] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A p-type tungsten diselenide field-effect transistor based on a 3R phase, characterized in that, include: The composition includes a p-type doped silicon substrate, a silicon dioxide gate dielectric disposed on the p-type doped silicon substrate, a 3R phase double-layer tungsten diselenide channel material disposed on the silicon dioxide gate dielectric, and source / drain electrodes disposed on the surface of the 3R phase double-layer tungsten diselenide channel material; the thickness of the 3R phase double-layer tungsten diselenide channel material is 1.4 nanometers; and the thickness of the silicon dioxide gate dielectric is 5-300 nanometers.

2. The p-type tungsten diselenide field-effect transistor based on the 3R phase according to claim 1, characterized in that, The source and drain electrodes include a bottom contact metal and an upper metal layer; The underlying contact metal material is one of nickel, platinum, and palladium; The upper metal material is one of the following: gold, silver, palladium, osmium, iridium, platinum, titanium, aluminum, chromium, germanium, molybdenum, nickel, tungsten, copper, cobalt, or iron.

3. The p-type tungsten diselenide field-effect transistor based on the 3R phase according to claim 2, characterized in that, The bottom contact metal material is nickel with a thickness of 10-30 nanometers, and the top metal material is gold with a thickness of 30-60 nanometers.

4. A method for fabricating a p-type tungsten diselenide field-effect transistor based on the 3R phase as described in any one of claims 1-3, characterized in that, The method includes: Step S1: Clean the silicon substrate with p-type doping and silicon dioxide surface, and perform high-temperature rapid annealing; Step S2: Use salt-assisted chemical vapor deposition to grow a double layer of tungsten diselenide with 3R and 2H phases; Step S3: Prepare a labeling layer for the bilayer tungsten diselenide of the 3R phase and 2H phase; Step S4, Isolation region etching, includes: using a marker layer to locate the position of the 3R phase double-layer tungsten diselenide, and defining an active region and an isolation region on the surface of the 3R phase double-layer tungsten diselenide; Step S5: Prepare source and drain electrodes on the surface of the 3R phase double-layer tungsten diselenide; In step S2, the conditions for salt-assisted chemical vapor deposition are as follows: potassium chloride mass 0-5 mg, tungsten dioxide mass 30-50 mg, selenium elemental powder mass 100-300 mg, growth temperature 850-1050 degrees Celsius, argon gas flow rate of 90-110 standard flow rate and hydrogen gas flow rate of 8-12 standard flow rate, growth pressure 1000-2500 Pa, and growth time 10-20 minutes.

5. The preparation method according to claim 4, characterized in that, In step S1, during the high-temperature rapid annealing of the silicon substrate, a high-temperature rapid annealing furnace is used, with an annealing temperature of 850-1050 degrees Celsius and an annealing time of 1 minute.

6. The preparation method according to claim 5, characterized in that, In step S4, the etching is reactive ion etching.

7. The preparation method according to claim 4, characterized in that, In step S3, the material of the marking layer includes a bottom contact metal and an upper metal: the bottom contact metal is 20 nanometers of nickel, and the upper metal is 40 nanometers of gold.

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