Method for manufacturing a storage device

Abstract

The present invention discloses a method for manufacturing a memory device, comprising the following steps. A plurality of memory cells are formed on a substrate. Each memory cell includes a first electrode, a second electrode, and a memory material layer. The second electrode is vertically disposed above the first electrode, and the memory material layer is vertically disposed between the first and second electrodes. A conformal spacer layer is formed on the memory cell. A non-conformal spacer layer is formed on the conformal spacer layer. A first opening is formed vertically extending through a sidewall portion of the non-conformal spacer layer and a sidewall portion of the conformal spacer layer.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a storage device, and in particular to a method for manufacturing a storage device with a spacer layer. Background Art

[0002] Semiconductor memory is a semiconductor device used to store data in computers or electronic products. It can be broadly categorized as volatile memory or non-volatile memory. Volatile memory refers to computer memory whose stored data disappears when the operating power is interrupted. In contrast, non-volatile memory is characterized by its ability to withstand power outages. For example, magnetic random access memory (MRAM) is a non-volatile memory technology. Unlike standard memory devices, MRAM uses magnetism to store data rather than electrical charge. Typically, an MRAM cell consists of a data layer and a reference layer. The data layer is composed of a magnetic material whose magnetization can be switched between two opposing states by an applied magnetic field, thereby storing binary information. The reference layer can be composed of a magnetic material whose magnetization can be locked, so that a magnetic field applied to the data layer and partially penetrating the reference layer is insufficient to switch the magnetization of the reference layer. During a read operation, when the magnetization directions of the data layer and the reference layer are the same or different, the resistance of the MRAM cell is different, so the magnetization polarity of the data layer can be identified accordingly. Summary of the Invention

[0003] The present invention provides a method for manufacturing a memory device, which utilizes a conformal spacer layer formed on a memory cell and a non-conformal spacer layer formed on the conformal spacer layer, thereby enhancing the protection effect of the memory cell in subsequent manufacturing processes and further improving the manufacturing yield of the memory device.

[0004] One embodiment of the present invention provides a method for manufacturing a memory device, comprising the following steps: forming a plurality of memory cells on a substrate, each memory cell comprising a first electrode, a second electrode, and a memory material layer; the second electrode being disposed vertically above the first electrode, and the memory material layer being disposed vertically between the first and second electrodes; forming a conformal spacer layer on the plurality of memory cells, and forming a non-conformal spacer layer on the conformal spacer layer; and forming a first opening vertically through a sidewall portion of the non-conformal spacer layer and a sidewall portion of the conformal spacer layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figures 1 to 9 FIG. 1 is a schematic diagram of a method for manufacturing a storage device according to an embodiment of the present invention, wherein

[0006] Figure 2 for Figure 1 Schematic diagram of the situation afterwards;

[0007] Figure 3 for Figure 2 Schematic diagram of the situation afterwards;

[0008] Figure 4 for Figure 3 Schematic diagram of the situation afterwards;

[0009] Figure 5 for Figure 4 Schematic diagram of the situation afterwards;

[0010] Figure 6 for Figure 5 Schematic diagram of the situation afterwards;

[0011] Figure 7 for Figure 6 Schematic diagram of the situation afterwards;

[0012] Figure 8 for Figure 7 Schematic diagram of the situation afterwards;

[0013] Figure 9 for Figure 8 Schematic diagram of the situation afterwards;

[0014] Figure 10 FIG. 4 is a schematic diagram of a method for manufacturing a storage device according to another embodiment of the present invention.

[0015] Description of main component symbols

[0016] 10 base

[0017] 11 Dielectric layer

[0018] 21 Dielectric layer

[0019] 22 Metal Interconnect

[0020] 23 Stop layer

[0021] 30 Intermetallic Dielectric Layer

[0022] 40 Metal Interconnect

[0023] 41 Barrier layer

[0024] 42 metal layers

[0025] 50 storage units

[0026] 51 first electrode

[0027] 52 Storage Material Layer

[0028] 53 second electrode

[0029] 54 cap layer

[0030] 62 first spacer layer

[0031] 62A Part 1

[0032] 62B Part 2

[0033] 62C Part 3

[0034] 62S side wall

[0035] 64 second spacer layer

[0036] 64A Part 1

[0037] 64B Part 2

[0038] 64C Part 3

[0039] 64S side wall

[0040] 66 third spacer layer

[0041] 66P spacer structure

[0042] 70 patterned mask layer

[0043] 72 Low-k dielectric layer

[0044] 74 Stop Layer

[0045] 76 Low-k dielectric layer

[0046] 91 Etching Process

[0047] 92 Etching Process

[0048] 93 Etching Process

[0049] 100 Storage Device

[0050] BS bottom surface

[0051] CS1 connection structure

[0052] CS21 connection structure

[0053] CS22 connection structure

[0054] CS31 connection structure

[0055] CS32 connection structure

[0056] D1 First direction

[0057] D2 Second direction

[0058] OP1 First Opening

[0059] OP2 Second opening

[0060] OS protrusion structure

[0061] R1 Zone 1

[0062] R2 Second Zone

[0063] SW1 side wall

[0064] SW2 side wall

[0065] TK1 thickness

[0066] TK2 thickness

[0067] TK3 thickness

[0068] TS top surface

[0069] W1 width

[0070] W2 width DETAILED DESCRIPTION

[0071] The following detailed description of the present invention discloses sufficient details to enable those skilled in the art to practice the present invention. The embodiments set forth below are to be considered illustrative rather than restrictive. It will be apparent to those skilled in the art that various changes and modifications in form and details may be made without departing from the spirit and scope of the present invention.

[0072] Before further describing each embodiment, specific terms used throughout the document are explained below.

[0073] The terms “on,” “over,” and “over” should be interpreted in the broadest sense, so that “on” means not only “directly on” something, but also includes being on something with other intervening features or layers, and “over” or “over” means not only being “over” or “above” something, but also includes being “over” or “above” something with no other intervening features or layers (i.e., directly on something).

[0074] The ordinal numbers used in the specification and claims, such as "first" and "second", are used to modify claim elements. Unless otherwise specified, they do not imply or represent any previous ordinal number of the claimed element, nor do they represent the order of one claimed element and another claimed element, or the order in the manufacturing method. The use of these ordinal numbers is only used to clearly distinguish one claimed element with a certain name from another claimed element with the same name.

[0075] The term "etching" is generally used herein to describe a process for patterning a material so that at least a portion of the material remains after the etching is complete. When "etching" a material, at least a portion of the material may remain after the etching is complete. In contrast, when "removing" a material, substantially all of the material may be removed during the process. However, in some embodiments, "removing" may be considered a broad term to include etching.

[0076] The terms "forming" or "disposing" are used hereinafter to describe the act of applying a layer of material to a substrate. These terms are intended to describe any feasible layer formation technique, including but not limited to thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, etc.

[0077] See also Figures 1 to 9 . Figures 1 to 9 The diagram shows a method for manufacturing a memory device according to an embodiment of the present invention, wherein Figure 2 Draws Figure 1 Schematic diagram of the situation afterwards, Figure 3 Draws Figure 2 Schematic diagram of the situation afterwards, Figure 4 Draws Figure 3 Schematic diagram of the situation afterwards, Figure 5 Draws Figure 4 Schematic diagram of the situation afterwards, Figure 6 Draws Figure 5 Schematic diagram of the situation afterwards, Figure 7 Draws Figure 6 Schematic diagram of the situation afterwards, Figure 8 Draws Figure 7 The following diagram shows the situation: Figure 9 Draws Figure 8 Schematic diagram of the situation afterward. Figure 9 As shown, the manufacturing method of the memory device 100 of this embodiment may include the following steps. A plurality of memory cells 50 are formed on a substrate 10, each memory cell including a first electrode 51, a second electrode 53 and a memory material layer 52. The second electrode 53 is disposed in a vertical direction (e.g., Figure 9The first electrode 51 is disposed on the first electrode 51 in the first direction D1 shown in FIG, and the storage material layer 52 is disposed between the first electrode 51 and the second electrode 53 in the vertical direction. A conformal spacer layer (e.g., Figure 9 ), and forming a non-conformal spacer layer (e.g., a first spacer layer 62 shown in FIG. 5 ) on the conformal spacer layer. Figure 9 ). A first opening OP1 is then formed, vertically penetrating a sidewall portion of the non-conformal spacer layer (e.g., sidewall portion 64S of the second spacer layer 64) and a sidewall portion of the conformal spacer layer (e.g., sidewall portion 62S of the first spacer layer 62). Forming the non-conformal second spacer layer 64 on the conformal first spacer layer 62 increases the amount of spacer material located on the sidewalls of the memory cells 50 when forming the first opening OP1 between the memory cells 50. This enhances the protection of the memory cells 50 and improves the manufacturing yield of the memory device.

[0078] In some embodiments, the substrate 10 may have an upper surface TS and a bottom surface BS opposite to each other in its thickness direction (e.g., the first direction D1 mentioned above), and the memory cell 50, the first spacer layer 62, the second spacer layer 64, and the first opening OP1 may be formed on one side of the upper surface TS, but is not limited thereto. A horizontal direction substantially perpendicular to the first direction D1 (e.g., Figure 9 The second direction D2 shown in FIG2 may be substantially parallel to the top surface TS and / or the bottom surface BS of the substrate 10, but is not limited thereto. Furthermore, as described herein, the distance between a relatively higher position or / and component in the vertical direction (e.g., the first direction D1) and the bottom surface BS of the substrate 10 in the first direction D1 may be greater than the distance between a relatively lower position or / and component in the first direction D1 and the bottom surface BS of the substrate 10 in the first direction D1. The lower portion or bottom of each component may be closer to the bottom surface BS of the substrate 10 in the first direction D1 than the upper portion or top of the component. A component above a component may be considered to be relatively farther from the bottom surface BS of the substrate 10 in the first direction D1, while a component below a component may be considered to be relatively closer to the bottom surface BS of the substrate 10 in the first direction D1, but the present invention is not limited thereto.

[0079] To further illustrate, the manufacturing method of the storage device 100 of this embodiment may include but is not limited to the following steps. First, Figure 1As shown, a plurality of memory cells 50 may be formed on a substrate 10. In some embodiments, the first electrode 51 and the second electrode 53 in each memory cell 50 may each comprise a metal material such as titanium (Ti), tantalum (Ta), platinum (Pt), ruthenium (Ru), a composite layer, alloy, mixture of these materials, or other suitable metallic conductive materials or non-metallic conductive materials. The storage material layer 52 in each memory cell 50 may comprise a magnetic tunneling junction (MTJ) structure or other material layer suitable for providing a memory operation by changing state. In some embodiments, the magnetic tunneling junction structure may comprise, but is not limited to, a pinned layer, a first barrier layer, a free layer, and a second barrier layer stacked in sequence in a first direction. In some embodiments, the pinned layer may comprise an antiferromagnetic layer and a reference layer. The antiferromagnetic layer may include an antiferromagnetic material, such as iron manganese (FeMn), platinum manganese (PtMn), iridium manganese (IrMn), nickel oxide (NiO), a cobalt / platinum (Co / Pt) composite layer, or other suitable antiferromagnetic materials. The free layer and the reference layer in the pinned layer may include a ferromagnetic material, such as iron, cobalt, nickel, a cobalt-iron (CoFe) alloy, cobalt-iron-boron (CoFeB), or other suitable ferromagnetic materials. The first barrier layer and the second barrier layer may include an insulating material, such as magnesium oxide (MgO), aluminum oxide, or other suitable insulating materials. In some embodiments, the material layers in the above-mentioned magnetic tunnel junction structure and the material layers used to form the first electrode 51 and the second electrode 53 can be stacked in sequence using a deposition process such as a sputtering process, and a cap layer 54 can be formed on this material stack. Then, the cap layer 54 and / or a patterned photoresist layer (not shown) are used as an etching mask to perform an etching process 91 on the material stack to form the memory cell 50, and the cap layer 54 can be located on each memory cell 50 after the etching process 91.

[0080] In some embodiments, the capping layer 54 may include an oxide insulating material or other suitable insulating material, and the etching process 91 may include a reactive ion etching (RIE) process or other suitable etching method. The substrate 10 may include a semiconductor substrate or a non-semiconductor substrate. The semiconductor substrate may include, for example, a silicon substrate, a silicon-germanium semiconductor substrate, or a silicon-on-insulator (SOI) substrate, and the non-semiconductor substrate may include, but is not limited to, a glass substrate, a plastic substrate, or a ceramic substrate. For example, when the substrate 10 includes a semiconductor substrate, a plurality of silicon-based field effect transistors (not shown), a dielectric layer covering the silicon-based field effect transistors (for example, Figure 1 ), a dielectric layer 11 and a dielectric layer 21, a plurality of metal interconnections 22, a stop layer 23, an intermetallic dielectric layer 30, and a plurality of metal interconnections 40, and then the above-mentioned material stack is formed and an etching process is performed to form memory cells 50. Each memory cell 50 can be formed on a corresponding metal interconnection 40 and electrically connected thereto.

[0081] In some embodiments, the metal interconnects 40 may be electrically connected to portions of the metal interconnects 22 and may be electrically connected downward to the aforementioned silicon-based field-effect transistors through portions of the metal interconnects 22, but the present invention is not limited thereto. In some embodiments, each metal interconnect 22 may be considered a trench conductor and extend primarily in a horizontal direction (e.g., another horizontal direction perpendicular to the second direction D2), while each metal interconnect 40 may be considered a via conductor and extend primarily in a vertical direction (e.g., the first direction D1), but the present invention is not limited thereto. In some embodiments, each metal interconnect 40 may include a barrier layer 41 and a metal layer 42. The barrier layer 41 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or other suitable barrier materials, while the metal layer 42 may include tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), or other suitable metal materials. Furthermore, in some embodiments, the substrate 10 may include a first region R1 and a second region R2, wherein the first region R1 may be considered a memory cell region on which the memory cell 50 is disposed, and the second region R2 may be considered a logic region, but the present invention is not limited thereto. The aforementioned dielectric layer 11, dielectric layer 21, metal interconnect 22, stop layer 23, and intermetallic dielectric layer 30 may also be partially formed on the second region R2. In some embodiments, the region between adjacent memory cells 50 may be considered a region corresponding to a word line, and the metal interconnect 22 in this region may include a word line or be electrically connected to a word line, but the present invention is not limited thereto. Furthermore, the structure of the metal interconnect 22 may be similar to that of the metal interconnect 40 and include a barrier layer (not shown) and a metal layer (not shown), but the present invention is not limited thereto. The dielectric layer 11 , the dielectric layer 21 , and the intermetallic dielectric layer 30 may respectively include silicon oxide, a low-k dielectric material, or other suitable dielectric materials, and the stop layer 23 may include nitrogen doped carbide (NDC), silicon nitride, silicon carbon nitride (SiCN), or other suitable insulating materials.

[0082] Then, if Figure 2As shown, a first spacer layer 62 is conformally formed on the cap layer 54, the memory cell 50, and the intermetallic dielectric layer 30. The first spacer layer 62 formed on the sidewalls of the memory cell 50, the first spacer layer 62 formed on the cap layer 54, and the first spacer layer 62 formed on the intermetallic dielectric layer 30 may have substantially the same thickness, so the first spacer layer 62 may be considered a conformal spacer layer. In some embodiments, the first spacer layer 62 may include a first portion 62A, a second portion 62B, and a third portion 62C. The first portion 62A may be formed between adjacent memory cells 50 in a horizontal direction (e.g., the second direction D2), and the first portion 62A may be disposed on the intermetallic dielectric layer 30 in the first direction D1. The second portion 62B may be formed on the sidewalls of each memory cell 50 and on the sidewalls SW2 of the capping layer 54 on each memory cell 50, for example, on the sidewalls of the first electrode 51, on the sidewalls of the storage material layer 52, and on the sidewalls SW1 of the second electrode 53. The third portion 62C may be formed on the memory cell 50 and the capping layer 54 in the first direction D1. The first portion 62A may be directly connected to the second portion 62B, and the second portion 62B may be directly connected to the third portion 62C. The first portion 62A and the second portion 62B may be considered as the sidewall portion 62S of the first spacer layer 62.

[0083] In some embodiments, the first portion 62A, the second portion 62B, and the third portion 62C of the first spacer layer 62 may have substantially the same thickness. The thickness of the first portion 62A may be defined as the distance in the first direction D1 between the surface of the first portion 62A in contact with the intermetal dielectric layer 30 and the upper surface of the first portion 62A. The thickness of the second portion 62B may be defined as the distance in the horizontal direction (e.g., the second direction D2) between the surface of the second portion 62B in contact with the memory cell 50 and the surface of the second portion 62B away from the memory cell 50. The thickness of the third portion 62C may be defined as the distance in the first direction D1 between the surface of the third portion 62C in contact with the cap layer 54 and the upper surface of the third portion 62C, but is not limited thereto.

[0084] Then, if Figure 3As shown, a second spacer layer 64 is formed on the first spacer layer 62. The second spacer layer 64 may have a plurality of overhang structures OS, and each overhang structure OS may be formed on a memory cell 50, so the second spacer layer 64 may be considered a non-conformal spacer layer. In other words, the cap layer 54 on each memory cell 50 may be formed on the substrate 10 before the first spacer layer 62 and the second spacer layer 64 are formed. In some embodiments, the second spacer layer 64 may include a first portion 64A, a second portion 64B, and a third portion 64C. The first portion 64A may be formed on the first portion 62A of the first spacer layer 62, the second portion 64B may be formed on the second portion 62B of the first spacer layer 62 in a horizontal direction (e.g., the second direction D2), and the third portion 64C may be formed on the third portion 62C of the first spacer layer 62 in the first direction D1. The first portion 64A can be directly connected to the second portion 64B, and the second portion 64B can be directly connected to the third portion 64C. The first portion 64A and the second portion 64B can be regarded as the sidewall portion 64S of the second spacer layer 64, and the third portion 64C and a portion of the second portion 64B of the second spacer layer 64 on each storage unit 50 can form a protrusion structure OS.

[0085] In some embodiments, the width W1 of the third portion 64C of the second spacer layer 64 on each memory cell 50 may be greater than the width W2 of the second portion 64B of the second spacer layer 64 on each memory cell 50, and the thickness TK1 of the third portion 64C of the second spacer layer 64 on each memory cell 50 may be greater than the thickness of the second portion 64B of the second spacer layer 64 on each memory cell 50 (e.g., Figure 3 , and / or thickness TK3) are formed to form the protrusion structure OS. For example, the width W1 described above can be considered as the length of the third portion 64C of the second spacer layer 64 on each memory cell 50 in the second direction D2, and the width W2 described above can be considered as the distance in the second direction D2 between the two outer surfaces of the second portion 64B formed on opposite sides of each memory cell 50 in the second direction D2, but the present invention is not limited thereto. In addition, in some embodiments, the second portion 64B of the second spacer layer 64 can be formed in a horizontal direction (e.g., the second direction D2) on the second electrode 53, the memory material layer 52, and the first electrode 51 of each memory cell 50, and the thickness TK2 of the second spacer layer 64 on each second electrode 53 in the second direction D2 can be greater than the thickness TK3 of the second spacer layer 64 on each memory material layer 52 in the second direction D2. Therefore, at least a portion of the second spacer layer 64 on each second electrode 53 can be used to form the protrusion structure OS.

[0086] In some embodiments, thickness TK1 can be considered as the length of the third portion 64C of the second spacer layer 64 on each memory cell 50 in the first direction D1, thickness TK2 can be considered as the distance in the second direction D2 between the surface of the second portion 64B disposed on the second electrode 53 in contact with the first spacer layer 62 and the surface of the second portion 64B away from the memory cell 50, and thickness TK3 can be considered as the distance in the second direction D2 between the surface of the second portion 64B disposed on the memory material layer 52 in contact with the first spacer layer 62 and the surface of the second portion 64B away from the memory cell 50, but the present invention is not limited thereto. In some embodiments, the second spacer layer 64 having the protrusion structure OS can be formed by adjusting the process conditions (e.g., deposition direction, angle, etc.) of the film formation process (e.g., but not limited to chemical vapor deposition) used to form the second spacer layer 64. Furthermore, the material composition of the first spacer layer 62 may be different from the material composition of the second spacer layer 64, while the material composition of the cap layer 54 may be different from the material composition of the first spacer layer 62, thereby providing a desired etching selectivity in subsequent fabrication processes. For example, the cap layer 54 may include an oxide insulating material, the first spacer layer 62 may include silicon nitride or other insulating material different from the cap layer 54, and the second spacer layer 64 may include an oxide (e.g., silicon oxide), silicon carbide, or other insulating material different from the first spacer layer 62.

[0087] like Figure 4As shown, a third spacer layer 66 can be formed on the second spacer layer 64. Therefore, a portion of the third spacer layer 66 can be formed on each memory cell 50 in the first direction D1, and another portion of the third spacer layer 66 can be formed between adjacent memory cells 50 in the second direction D2. By forming the second spacer layer 64 with the protrusion structure OS, the distance between adjacent protrusions on the surface of the third spacer layer 66 can be shortened. Therefore, when the third spacer layer 66 and the second spacer layer 64 are subsequently etched back to form the spacer structure, more spacer material can be retained on the sidewalls of each memory cell 50, thereby enhancing the protection of the memory cell 50. In some embodiments, due to the second spacer layer 64 having the protrusion structure OS, a relatively small amount of third spacer layer 66 can be used to fill the space between adjacent memory cells 50. Furthermore, the third spacer layer 66 formed on each memory cell 50 in the first direction D1 can be relatively thin, thereby relatively shortening the etch-back time for the third spacer layer 66 and allowing more spacer material to remain on the sidewalls of each memory cell 50 after the etch-back process. In some embodiments, the third spacer layer 66 can include an oxide material (e.g., an oxide formed by an atomic layer deposition process) or other suitable insulating material. The material composition of the third spacer layer 66 can be different from that of the second spacer layer 64. Alternatively, the third spacer layer 66 and the second spacer layer 64 can have similar material compositions (e.g., both are silicon oxide), but due to their different film formation methods, they can still provide a desired etch selectivity in subsequent processing steps.

[0088] like Figures 4 and 5 As shown, an etching process 92 may be performed to etch the third spacer layer 66 and the second spacer layer 64 to form a spacer structure 66P and a second opening OP2. The second opening OP2 may penetrate the third spacer layer 66 and the first portion 64A of the second spacer layer 64 in the first direction D1 to expose the first portion 62A of the first spacer layer 62. In other words, the third spacer layer 66 may be formed before the second opening OP2. The second opening OP2 does not penetrate the first portion 62A of the first spacer layer 62. The remaining portion of the third spacer layer 66 after being etched by the etching process 92 may become the spacer structure 66P formed on the sidewall portion 64S of the second spacer layer 64. In some embodiments, the etching process 92 may be considered as an etch-back process performed on the third spacer layer 66 and the second spacer layer 64, and the second opening OP2 may be formed by this etch-back process. In addition, the third portion 64C of the second spacer layer 64 may be removed during the process of forming the second opening OP2 (eg, the etching process 92 ), and the third spacer layer 66 and the second spacer layer 64 on the second region R2 may be removed by the etching process 92 .

[0089] like Figures 5 to 7 As shown, a first opening OP1 can then be formed, and the first opening OP1 can penetrate the third spacer layer 66, the sidewall portion 64S (e.g., the first portion 64A) of the second spacer layer 64, and the sidewall portion 62S (e.g., the first portion 62A) of the first spacer layer 62 in the first direction D1 to expose a portion of the intermetallic dielectric layer 30. In other words, the second opening OP2 can be formed before the first opening OP1, and the first opening OP1 can be formed by performing an etching process on the second opening OP2. For example, a patterned mask layer 70 can be formed to cover the first spacer layer 62, the second spacer layer 64, and the third spacer layer 66 on each memory cell 50 to expose a portion of the second opening OP2 and the first spacer layer 62 on the second region R2. After the patterned mask layer 70 is formed, an etching process 93 is performed to form the first opening OP1 and remove the first spacer layer 62 on the second region R2 to expose the intermetallic dielectric layer 30 on the second region R2. In some embodiments, the patterned mask layer 70 may include a patterned photoresist layer, and the patterned mask layer 70 may be completely removed during or after the etching process 93. Through the above-described fabrication method, a relatively large amount of spacer material may remain on the sidewalls of each memory cell 50 after the second opening OP2 is formed. Therefore, after the etching process 93 and after the first opening OP1 is formed, the sidewall SW1 of the second electrode 53 of each memory cell 50 may be completely covered in the horizontal direction (e.g., the second direction D2) by the second portion 62B of the first spacer layer 62, and the second portion 62B of the first spacer layer 62 may be completely covered in the horizontal direction (e.g., the second direction D2) by the sidewall portion 64S (e.g., the second portion 64B) of the second spacer layer 64, thereby achieving the effect of protecting the memory cell 50. In addition, after the first opening OP1 is formed, the sidewall portion 62S (for example, the second portion 62B) of the first spacer layer 62 can still cover the sidewall SW1 of the second electrode 53 of each memory cell 50 and the sidewall SW2 of the cap layer 54 on each memory cell 50. Therefore, after the first opening OP1 is formed, the second electrode 53 can still be covered by the cap layer 54 and the first spacer layer 62 to achieve a protective effect.

[0090] Then, if Figure 8As shown, a low-k dielectric layer 72, a connection structure CS21, and a connection structure CS31 may be formed. The low-k dielectric layer 72 may be formed in the first opening OP1, on the third spacer layer 66, on the intermetallic dielectric layer 30, and on the intermetallic dielectric layer 30 in the second region R2. The connection structure CS21 may be formed between adjacent memory cells 50 and pass through the stop layer 23, the intermetallic dielectric layer 30, and the low-k dielectric layer 72 in the first opening OP1 in the first direction D1 to electrically connect to the metal interconnect 22 between the adjacent memory cells 50. The connection structure CS31 may be formed on the second region R2 and pass through the stop layer 23, the intermetallic dielectric layer 30, and the low-k dielectric layer 72 in the first direction D1 to electrically connect to the metal interconnect 22 on the second region R2. In some embodiments, a planarization process may be performed after the low-k dielectric layer 72 is formed and before the connection structure CS21 and the connection structure CS31 are formed to make the upper surface of the low-k dielectric layer 72, the upper surface of the second spacer layer 64, and the upper surface of the first spacer layer 62 substantially coplanar, but the present invention is not limited thereto.

[0091] like Figure 9 As shown, after the connection structure CS21 and the connection structure CS31 are formed, a stop layer 74, a low-k dielectric layer 76, a plurality of connection structures CS1, a connection structure CS22 and a connection structure CS32 may be formed, thereby forming Figure 1Memory device 100 shown. A stop layer 74 may be formed on the low-k dielectric layer 72, the second spacer layer 64, the first spacer layer 62, the connection structure CS21, and the connection structure CS31, and a low-k dielectric layer 76 may be formed on the stop layer 74. Each connection structure CS1 may penetrate the low-k dielectric layer 76, the stop layer 74, the first spacer layer 62, and the cap layer 54 on the memory cell 50 in the first direction D1 to contact and form an electrical connection with the second electrode 53. The connection structure CS22 may penetrate the low-k dielectric layer 76 and the stop layer 74 on the connection structure CS21 in the first direction D1 to contact and form an electrical connection with the connection structure CS21. The connection structure CS32 may penetrate the low-k dielectric layer 76 and the stop layer 74 on the connection structure CS31 in the first direction D1 to contact and form an electrical connection with the connection structure CS31. In some embodiments, each of the aforementioned connection structures (e.g., connection structure CS1, connection structure CS21, connection structure CS22, connection structure CS31, and / or connection structure CS32) may include a contact hole conductor and a trench conductor disposed on and connected to the contact hole conductor. Each connection structure may include a barrier layer (not shown) and a metal layer (not shown), similar to the structure of metal interconnect 40, but the present invention is not limited thereto. In some embodiments, low-k dielectric layer 72 and low-k dielectric layer 76 may each include a dielectric material having a dielectric constant less than 2.7, such as benzocyclobutene (BCB), hydrogen silsesquioxane (HSQ), methyl silesquioxane (MSQ), silicon oxycarbon hydride (SiOC-H), a porous dielectric material, or other suitable dielectric materials. The stop layer 74 may include nitrogen doped carbide (NDC), silicon nitride, silicon carbon nitride (SiCN), or other suitable insulating materials.

[0092] The following describes various embodiments of the present invention. To simplify the description, the following description focuses on the differences between the embodiments and does not repeat the similarities. In addition, the same elements in the various embodiments of the present invention are labeled with the same reference numerals to facilitate comparison between the various embodiments.

[0093] See also Figure 10 as well as Figure 6 . Figure 10 FIG. 1 is a schematic diagram of a method for manufacturing a storage device according to another embodiment of the present invention. Figure 10 can be considered as depicting Figure 6 Schematic diagram of the situation afterward. Figure 6 and Figure 10 As shown, in some embodiments, the third portion 62C of the first spacer layer 62 can be removed during the process of forming the first opening OP1 (e.g., the etching process 93), but the second electrode 53 in each memory cell 50 can still be covered by the capping layer 54 and the sidewall portion 62S of the first spacer layer 62 after the etching process 93 to achieve a protective effect, and the second portion 62B3 of the first spacer layer 62 can still be covered by the second portion 64B of the second spacer layer 64 in the horizontal direction (e.g., the second direction D2) after the etching process 93 to achieve a protective effect.

[0094] In summary, in the method for manufacturing a memory device of the present invention, a conformal spacer layer can be formed on the memory cells and a non-conformal spacer layer can be formed on the conformal spacer layer. The non-conformal spacer layer having a protrusion structure can ensure that more spacer material is retained on the sidewalls of each memory cell after the first opening is formed, thereby enhancing the protection effect of the memory cells and further improving the manufacturing yield of the memory device.

[0095] The above descriptions are merely preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A method for manufacturing a storage device, comprising: A plurality of memory cells are formed on a substrate, wherein each of the memory cells comprises: a first electrode; a second electrode disposed vertically above the first electrode; and a storage material layer, arranged between the first electrode and the second electrode in the vertical direction; forming a conformal spacer layer on the plurality of memory cells, wherein the conformal spacer layer comprises: A first portion is formed between adjacent memory cells in a horizontal direction; a second portion formed on a sidewall of the second electrode of each of the memory cells; and a third portion formed on the plurality of memory cells in the vertical direction; forming a non-conformal spacer layer on the conformal spacer layer, wherein the non-conformal spacer layer comprises: A first portion formed on the first portion of the conformal spacer layer; a second portion formed on the second portion of the conformal spacer layer in the horizontal direction; and a third portion formed on the plurality of memory cells in the vertical direction, wherein the third portion of the non-conformal spacer layer is formed on the third portion of the conformal spacer layer in the vertical direction, and the third portion of the non-conformal spacer layer on each of the memory cells and a portion of the second portion of the non-conformal spacer layer form a protrusion structure; and A first opening is formed, wherein the first opening penetrates the first portion of the non-conformal spacer layer and the first portion of the conformal spacer layer in the vertical direction. 2 . The method for manufacturing a memory device according to claim 1 , wherein after the first opening is formed, the second portion of the conformal spacer layer is covered by the second portion of the non-conformal spacer layer in the horizontal direction.

3. The method for manufacturing a memory device as claimed in claim 1 , wherein after the first opening is formed, the sidewall of the second electrode of each memory cell is completely covered by the second portion of the conformal spacer layer in the horizontal direction, and the second portion of the conformal spacer layer is completely covered by the second portion of the non-conformal spacer layer in the horizontal direction. 4 . The method for manufacturing a memory device according to claim 1 , wherein a width of the third portion of the non-conformal spacer layer on each memory cell is greater than a width of the second portion of the non-conformal spacer layer on each memory cell. 5 . The method for manufacturing a memory device according to claim 1 , wherein a thickness of the third portion of the non-conformal spacer layer on each memory cell is greater than a thickness of the second portion of the non-conformal spacer layer on each memory cell. 6 . The method for manufacturing a memory device as claimed in claim 1 , wherein the third portion of the conformal spacer layer is removed during the process of forming the first opening.

7. The method for manufacturing a storage device according to claim 1 , further comprising: Before forming the first opening, a second opening is formed. The second opening penetrates the first portion of the non-conformal spacer layer in the vertical direction to expose the first portion of the conformal spacer layer. 8 . The method for manufacturing a memory device as claimed in claim 7 , wherein the third portion of the non-conformal spacer layer is removed during the process of forming the second opening.

9. The method for manufacturing a storage device according to claim 7, further comprising: Before forming the second opening, a spacer layer is formed on the non-conformal spacer layer, wherein the second opening further penetrates the spacer layer in the vertical direction, and the first opening further penetrates the spacer layer in the vertical direction. 10 . The method for manufacturing a memory device as claimed in claim 9 , wherein the second opening is formed by performing an etch-back process on the spacer layer and the non-conformal spacer layer. 11 . The method for manufacturing a memory device according to claim 9 , wherein a material composition of the spacer layer is different from a material composition of the non-conformal spacer layer.

12. The method for manufacturing a memory device as claimed in claim 1 , wherein the second portion of the non-conformal spacer layer is formed on the second electrode of each memory cell and on the memory material layer of each memory cell in the horizontal direction, and the thickness of the non-conformal spacer layer on each second electrode in the horizontal direction is greater than the thickness of the non-conformal spacer layer on each memory material layer in the horizontal direction. 13 . The method for manufacturing a memory device as claimed in claim 1 , wherein a material composition of the conformal spacer layer is different from a material composition of the non-conformal spacer layer. 14 . The method for fabricating a memory device according to claim 1 , wherein the conformal spacer layer comprises silicon nitride, and the non-conformal spacer layer comprises oxide or silicon carbide.

15. The method for manufacturing a storage device according to claim 1, further comprising: A capping layer is formed on the substrate before the conformal spacer layer is formed, wherein the capping layer is located on each of the memory cells, and the second portion of the conformal spacer layer covers the sidewall of the second electrode of each of the memory cells and the sidewall of the capping layer on each of the memory cells after the first opening is formed. 16 . The method for manufacturing a memory device according to claim 15 , wherein a material composition of the cap layer is different from a material composition of the conformal spacer layer. 17 . The method for manufacturing a memory device as claimed in claim 1 , wherein the memory material layer in each of the memory cells comprises a magnetic tunneling junction structure.

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