Peak current control circuit for multiphase control circuit and multiphase control circuit

Abstract

The application discloses a peak current control circuit of a multiphase control circuit and the multiphase control circuit, which comprises a first comparator circuit configured to generate a first comparison signal according to an output sampling voltage of the multiphase control circuit and a first reference voltage; an amplifier circuit configured to generate an error amplification signal according to a feedback voltage of the multiphase control circuit and a second reference voltage; a second comparator circuit configured to generate a second comparison signal according to the error amplification signal and a third reference voltage; an AND gate configured to output a clamping trigger signal according to the first comparison signal and the second comparison signal; and a clamping signal control circuit configured to clamp the voltage value of the error amplification signal at a clamping reference voltage. By setting the clamping signal control circuit in the multiphase control circuit, the peak current in the multiphase control circuit is clamped, the large signal oscillation phenomenon of the output voltage during load switching is avoided, and the problem of circuit instability during small-range load switching of the multiphase power supply control circuit in the prior art is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuits, in particular, to a peak current control circuit of a multiphase control circuit and the multiphase control circuit. BACKGROUND

[0002] In the design of a multiphase power supply control circuit, not only the influence on the stability of the output voltage when switching the load in a large range should be considered, but also the stability of the circuit when switching the load in a small range should be considered. In the current scheme, the circuit will use a single phase to carry the load under a small current load, so as to save power consumption. However, when switching from a small current load to a heavy load for a single phase, the output voltage will decrease slightly, the circuit will perform a phase adding operation to supply power to the output voltage as soon as possible. When multiple phases start to work simultaneously to provide energy for the output, it will cause the output voltage to overshoot too much, and the circuit will trigger a phase reducing operation, entering the cycle of phase adding and phase reducing, and the output voltage will oscillate.

[0003] Therefore, there is a problem of instability of the circuit when the multiphase power supply control circuit in the prior art switches the load in a small range. SUMMARY

[0004] The main purpose of the present application is to provide a peak current control circuit of a multiphase control circuit and the multiphase control circuit, so as to solve the problem of instability of the circuit when the multiphase power supply control circuit in the prior art switches the load in a small range, and realize stable output voltage when switching the load in a small range in the multiphase control circuit.

[0005] In order to achieve the above-mentioned purpose, the first aspect of the present application provides a peak current control circuit of a multiphase control circuit, characterized in that it comprises: a first comparator circuit, an amplifier circuit, a second comparator circuit, an AND gate and a clamping signal control circuit,

[0006] The first comparator circuit is configured to generate a first comparison signal according to an output sampling voltage of the multiphase control circuit and a first reference voltage from a first reference voltage terminal, and transmit the first comparison signal to a first input terminal of the AND gate.

[0007] The amplifier circuit is configured to generate an error amplification signal according to a feedback voltage of the multiphase control circuit and a second reference voltage from a second reference voltage terminal, and transmit the error amplification signal to the second comparator circuit via a first node;

[0008] The second comparator circuit is configured to generate a second comparison signal according to the error amplification signal and a third reference voltage from a third reference voltage terminal, and transmit the second comparison signal to a second input terminal of the AND gate.

[0009] The AND gate is configured to receive a first comparison signal of the first comparator circuit and a second comparison signal of the second comparator circuit, and output a clamping trigger signal according to the first comparison signal and the second comparison signal;

[0010] The clamping signal control circuit is configured to clamp a voltage value of the error amplification signal at a clamping reference voltage when the clamping trigger signal is at an effective level.

[0011] In an optional embodiment of the present application, the first comparator circuit comprises a first voltage comparator and a first inverter,

[0012] The first input end of the first voltage comparator is coupled with a first reference voltage end to receive the first reference voltage, and an output sampling voltage of the multiphase control circuit is provided to a second input end of the first voltage comparator.

[0013] The output end of the first voltage comparator is coupled with the input end of the first inverter, and the output end of the first inverter is coupled with the first input end of the AND gate.

[0014] In an optional embodiment of the present application, the amplifier circuit comprises an error amplifier,

[0015] The first input end of the error amplifier is coupled with the second reference voltage end, and a feedback voltage of the multiphase control circuit is provided to a second input end of the error amplifier; and an output end of the error amplifier is coupled with the first node.

[0016] In an optional embodiment of the present application, the second comparator circuit comprises a second voltage comparator, a second inverter and a monostable trigger,

[0017] The first input end of the second voltage comparator is coupled with the third reference voltage end, the second input end of the second voltage comparator is coupled with the first node, and the output end of the second voltage comparator is coupled with the input end of the second inverter.

[0018] The output end of the second inverter is coupled with the input end of the monostable trigger.

[0019] The output end of the monostable trigger is coupled with the second input end of the AND gate, and the monostable trigger is configured to set a clamping duration of the clamping signal control circuit according to a pulse width of the monostable trigger.

[0020] In an optional embodiment of the present application, the clamping signal control circuit comprises a voltage-controlled switch and an operational amplifier,

[0021] The controlled end of the voltage-controlled switch is coupled to the output end of the AND gate, the first end of the voltage-controlled switch is coupled to the first node to receive the error amplification signal, and the second end of the voltage-controlled switch is coupled to the second input end of the operational amplifier and the output end of the operational amplifier.

[0022] The first input end of the operational amplifier is coupled to a clamping reference voltage end, and the clamping reference voltage is provided to the first input end of the operational amplifier.

[0023] In an optional embodiment of the present application, the peak current control circuit includes a third comparator circuit,

[0024] The third comparator circuit is configured to generate a third comparison signal according to an output sampling voltage of the multiphase control circuit and a fourth reference voltage from a fourth reference voltage end, and transmit the third comparison signal to a third input end of an AND gate.

[0025] In an optional embodiment of the present application, the third comparator circuit includes a third voltage comparator,

[0026] The first input end of the third voltage comparator receives the output sampling voltage of the multiphase control circuit, the second input end of the third voltage comparator is coupled to the fourth reference voltage end, and the output end of the third voltage comparator is coupled to the third input end of the AND gate.

[0027] In an optional embodiment of the present application,

[0028] When the first reference voltage is less than the output sampling voltage, the third reference voltage is less than the error amplification signal, and the fourth reference voltage is less than the output sampling voltage, the clamping trigger signal is at an active level, wherein the first reference voltage is greater than the fourth reference voltage.

[0029] According to a second aspect of the present application, a peak current control circuit of a multiphase control circuit is provided, including: a first voltage comparator, a first inverter, an error amplifier, a second voltage comparator, a second inverter, a monostable trigger, a voltage-controlled switch, an operational amplifier, a third voltage comparator, and an AND gate,

[0030] The first input end of the first voltage comparator is coupled to a first reference voltage end to receive a first reference voltage, and an output sampling voltage of the multiphase control circuit is provided to the second input end of the first voltage comparator.

[0031] The output end of the first voltage comparator is coupled to the input end of the first inverter, and the output end of the first inverter is coupled to the first input end of the AND gate.

[0032] The first input end of the error amplifier is coupled with a second reference voltage end, and a feedback voltage of the multiphase control circuit is provided to the second input end of the error amplifier; and the output end of the error amplifier is coupled with the first node.

[0033] The first input end of the second voltage comparator is coupled with a third reference voltage end, the second input end of the second voltage comparator is coupled with the first node, and the output end of the second voltage comparator is coupled with the input end of the second inverter.

[0034] The output end of the second inverter is coupled with the input end of the monostable trigger.

[0035] The output end of the monostable trigger is coupled with the second input end of the AND gate, and the monostable trigger is configured to set a clamping duration of an error amplification signal according to a pulse width setting of the monostable trigger.

[0036] The controlled end of the voltage-controlled switch is coupled with the output end of the AND gate, the first end of the voltage-controlled switch is coupled with the first node to receive the error amplification signal, and the second end of the voltage-controlled switch is coupled with the second input end of the operational amplifier and the output end of the operational amplifier.

[0037] The first input end of the operational amplifier is coupled with a clamping reference voltage end, and a clamping reference voltage is provided to the first input end of the operational amplifier.

[0038] The first input end of the third voltage comparator receives an output sampling voltage of the multiphase control circuit, the second input end of the third voltage comparator is coupled with the fourth reference voltage end, and the output end of the third voltage comparator is coupled with the third input end of the AND gate.

[0039] The first input end of the AND gate is coupled with the output end of the first inverter, the second input end of the AND gate is coupled with the output end of the monostable trigger, the third input end of the AND gate is coupled with the output end of the third voltage comparator, and the output end of the AND gate is coupled with the controlled end of the voltage-controlled switch.

[0040] According to a third aspect of the present application, a multiphase control circuit is provided, including the peak current control circuit as described above.

[0041] The technical solutions provided by the embodiments of the present application can have the following beneficial effects:

[0042] In the present application, a peak current control circuit of a multiphase control circuit is provided, comprising: a first comparator circuit, an amplifier circuit, a second comparator circuit, an AND gate, and a clamping signal control circuit, the first comparator circuit is configured to generate a first comparison signal according to an output sampling voltage of the multiphase control circuit and a first reference voltage from a first reference voltage terminal, and transmit the first comparison signal to a first input terminal of the AND gate; the amplifier circuit is configured to generate an error amplification signal according to a feedback voltage of the multiphase control circuit and a second reference voltage from a second reference voltage terminal, and transmit the error amplification signal to the second comparator circuit via a first node; the second comparator circuit is configured to generate a second comparison signal according to the error amplification signal and a third reference voltage from a third reference voltage terminal, and transmit the second comparison signal to a second input terminal of the AND gate; the AND gate is configured to receive the first comparison signal of the first comparator circuit and the second comparison signal of the second comparator circuit, and output a clamping trigger signal according to the first comparison signal and the second comparison signal; the clamping signal control circuit is configured to clamp the voltage value of the error amplification signal at a clamping reference voltage when the clamping trigger signal is at an effective level. By setting the first comparator circuit, the amplifier circuit, the second comparator, the AND gate and the clamping signal control circuit in the multiphase control circuit, when the generated clamping trigger signal is at an effective level, the peak current in the multiphase control circuit is clamped by the clamping signal control circuit, avoiding the output voltage rising rapidly when the load switching is in the phase adding, generating a large overshoot, triggering the phase reducing operation, causing the continuous repetition of the phase adding and phase reducing operation, and the output voltage appears large signal oscillation phenomenon, solving the problem of circuit instability in the prior art when the multiphase power control circuit is in a small range of load switching. BRIEF DESCRIPTION OF DRAWINGS

[0043] The accompanying drawings, which form a part of this application, are intended to provide further understanding of the application and are incorporated herein in their entirety. The schematic embodiment drawings of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation of the present application. In the drawings:

[0044] Figure 1 It is a circuit schematic diagram of an exemplary multiphase control circuit;

[0045] Figure 2 It is Figure 1 It is an exemplary timing diagram of some signals in the circuit;

[0046] Figure 3 It is a schematic diagram of a peak current control circuit of a multiphase control circuit provided in an optional embodiment of the present application;

[0047] Figure 4 It is a schematic circuit diagram of a peak current control circuit of a multiphase control circuit provided in an optional embodiment of the present application;

[0048] Figure 5 To Figure 4 Part of the signal timing diagram in the circuit. DETAILED DESCRIPTION

[0049] In order to make the purposes, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without any inventive effort shall also fall within the scope of protection of the present disclosure.

[0050] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this present subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, the statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or through one or more intermediate parts.

[0051] In all embodiments of the present disclosure, since the source and drain (emitter and collector) of the transistor are symmetrical, and the conduction current direction between the source and drain (emitter and collector) of the N-type transistor and the P-type transistor is opposite, in the embodiments of the present disclosure, the controlled middle end of the transistor is called the control electrode, and the remaining two ends of the transistor are called the first electrode and the second electrode, respectively. The transistor used in the embodiments of the present disclosure is mainly a switching transistor. In addition, terms such as "first" and "second" are only used to distinguish one component (or part of a component) from another component (or another part of a component).

[0052] In the design of a multi-phase control circuit, the circuit will use a single phase to carry a load under a small current load, in order to save power consumption. However, when switching from a small current load to a heavy load for a single phase, the output voltage will have a small amplitude drop, the circuit will perform a phase adding operation to supply power to the output voltage as soon as possible, and when multiple phases start to work simultaneously to provide energy to the output, it will cause the output voltage to overshoot too much, and the circuit will trigger a phase reducing operation, entering a cycle of phase adding and phase reducing, and the output voltage oscillates.

[0053] Figure 1 A circuit schematic diagram of an exemplary multi-phase control circuit is shown as Figure 1As shown, the circuit structure comprises: an error amplifier EA and a voltage comparator COMP, a first input terminal of the error amplifier EA is coupled to a first reference voltage terminal VERF1, a second input terminal of the error amplifier EA is coupled to a feedback voltage terminal VFB, an output terminal EAO of the error amplifier EA is coupled to a second input terminal of the voltage comparator COMP, and a first input terminal of the voltage comparator COMP is coupled to a second reference voltage terminal VERF2. The error amplifier EA amplifies the error between the feedback voltage VFB and the first reference voltage VERF1, outputs an error amplified voltage signal EAO, and the voltage comparator COMP is configured to compare the error amplified voltage signal EAO and the second reference voltage VERF2, and generate an EAO_LOW signal according to the comparison result, wherein the EAO_LOW signal is used to instruct the multiphase control circuit to perform phase addition or phase subtraction operation.

[0054] Figure 2 For Figure 1 An exemplary timing diagram of some signals in the circuit, Figure 2 An exemplary timing diagram of some signals in the multiphase control circuit when a small range load switching is performed is shown, wherein the signal VOUT represents the output voltage of the multiphase control circuit, the EAO signal is the signal obtained by performing error amplification on the output feedback voltage VFB of the multiphase control circuit and the first reference voltage VREF1 (the reference voltage of the output voltage), the EAO_LOW signal is the signal obtained by comparing the EAO signal with the second reference voltage, and the signals i L1-iLi represent the inductor currents of the first phase to the i-th phase, respectively.

[0055] When a small load is switched in, but the first phase cannot carry the load, the output voltage continues to drop, and the EAO voltage (the output voltage of the error transconductance amplifier) continues to rise. When the EAO rises to a certain threshold value, i.e., the value of the second reference voltage VREF2, the phase addition operation ADD PHASE is triggered. At this time, the enabled remaining phase currents quickly rise from 0A to provide large energy for the output. It can be seen that the output voltage quickly rises to produce a large overshoot. Subsequently, the EAO quickly drops, and when it drops to a certain threshold value, i.e., the value of the second reference voltage VREF2, the phase deletion operation DELETE PHASE is triggered. At this time, only one phase carries the load, and the first phase cannot carry the load, triggering the phase addition operation ADD PHASE again. The operations of phase addition and phase deletion are repeated continuously, and the output voltage appears large signal oscillation phenomenon.

[0056] In an optional embodiment of the present application, a peak current control circuit of a multiphase control circuit is provided, Figure 3 A schematic diagram of the peak current control circuit of the multiphase control circuit provided in the optional embodiment of the present application is shown in FIG. 4. Figure 3As shown, the peak current control circuit of the multiphase control circuit comprises a first comparator circuit 100, an amplifier circuit 200, a second comparator circuit 300, an AND gate A1, and a clamping signal control circuit 400.

[0057] The first comparator circuit 100 is configured to generate a first comparison signal VO_LOW according to an output sampling voltage VOUT of the multiphase control circuit and a first reference voltage VREF1 from a first reference voltage terminal VREF1, and deliver the first comparison signal VO_LOW to a first input terminal of the AND gate A1.

[0058] The amplifier circuit 200 is configured to generate an error amplification signal EAO according to a feedback voltage VFB of the multiphase control circuit and a second reference voltage VREF2 from a second reference voltage terminal, and deliver the error amplification signal EAO to the second comparator circuit 300 via a first node N1.

[0059] The second comparator circuit 300 is configured to generate a second comparison signal EAO_LOW according to the error amplification signal EAO and a third reference voltage VREF3 from a third reference voltage terminal, and deliver the second comparison signal EAO_LOW to a second input terminal of the AND gate A1.

[0060] The AND gate A1 is configured to receive the first comparison signal VO_LOW of the first comparator circuit 100 and the second comparison signal EAO_LOW of the second comparator circuit 300, and output a clamping trigger signal according to the first comparison signal VO_LOW and the second comparison signal EAO_LOW.

[0061] The clamping signal control circuit 400 is configured to clamp a voltage value of the error amplification signal EAO at a clamping reference voltage EAO_CLAMP when the clamping trigger signal is at an active level.

[0062] The peak current control circuit of the multiphase control circuit further comprises a third comparator circuit 500, which is configured to generate a third comparison signal SSEND according to the output sampling voltage VOUT of the multiphase control circuit and a fourth reference voltage VREF4 from a fourth reference voltage terminal, the third comparison signal SSEND being used to indicate whether the multiphase control circuit has completed a soft start stage, and deliver the third comparison signal SSEND to a third input terminal of the AND gate A1.

[0063] In the embodiment of the present application, when the first comparison signal VO_LOW, the second comparison signal EAO_LOW and the third comparison signal SSEND are all at the effective level, the clamping signal control circuit 400 clamps the error amplification signal EAO to clamp the error amplification signal EAO at the clamping reference voltage EAO_CLAMP, so that the instantaneous peak current added by the phase adding operation of the multi-phase control circuit is limited, the energy to the output end is limited, the overshoot of the output voltage is reduced, the undershoot of EAO is reduced, the phase reduction operation is not triggered again, and the output voltage is gradually adjusted from the multi-phase to stable, solving the problem of instability of the multi-phase power supply control circuit in the prior art when the small range load is cut, and realizing the stable output voltage when the small range load is cut in the multi-phase control circuit.

[0064] In an optional embodiment of the present application, a peak current control circuit of a multi-phase control circuit is provided, Figure 4 An optional peak current control circuit of a multi-phase control circuit provided in the embodiment of the present application is shown in a schematic circuit diagram as Figure 4 The peak current control circuit of the multi-phase control circuit includes a first comparator circuit 100, an amplifier circuit 200, a second comparator circuit 300, an AND gate A1, a clamping signal control circuit 400 and a third comparator circuit 500.

[0065] The first comparator circuit 100 includes a first voltage comparator COMP1 and a first inverter NG1, wherein the first input end of the first voltage comparator COMP1 is coupled to a first reference voltage end to receive a first reference voltage VREF1, and the output sampling voltage VOUT of the multi-phase control circuit is provided to the second input end of the first voltage comparator; the output end of the first voltage comparator COMP1 is coupled to the input end of the first inverter NG1, and the output end of the first inverter NG1 is coupled to the first input end of the AND gate A1.

[0066] The amplifier circuit 200 includes an error amplifier EA, wherein the first input end of the error amplifier EA is coupled to a second reference voltage end, and the feedback voltage VFB of the multi-phase control circuit is provided to the second input end of the error amplifier EA; the output end of the error amplifier EA is coupled to the first node N1.

[0067] The second comparator circuit 300 includes a second voltage comparator COMP2, a second inverter NG2, and a monostable multivibrator ONE SHOT. The first input terminal of the second voltage comparator COMP2 is coupled to a third reference voltage terminal, the second input terminal of the second voltage comparator COMP2 is coupled to a first node N1, and the output terminal of the second voltage comparator COMP2 is coupled to the input terminal of the second inverter NG2. The output terminal of the second inverter NG2 is coupled to the input terminal of the monostable multivibrator ONE SHOT. The output terminal of the monostable multivibrator ONE SHOT is coupled to the second input terminal of an AND gate A1. The monostable multivibrator ONE SHOT is configured to set the clamping duration of the clamping signal control circuit 400 according to the pulse width of the monostable multivibrator ONE SHOT.

[0068] The clamping signal control circuit 400 includes a voltage-controlled switch S1 and an operational amplifier AMP. The controlled terminal of the voltage-controlled switch S1 is coupled to the output terminal of the AND gate A1. The first terminal of the voltage-controlled switch S1 is coupled to the first node N1 to receive the error amplification signal EAO. The second terminal of the voltage-controlled switch S1 is coupled to the second input terminal and the output terminal of the operational amplifier AMP. The first input terminal of the operational amplifier AMP is coupled to the clamping reference voltage terminal. The clamping reference voltage EAO_CLAMP is provided to the first input terminal of the operational amplifier AMP.

[0069] The third comparator circuit 500 includes a third voltage comparator COMP3, wherein the first input terminal of the third voltage comparator COMP3 receives the output sampling voltage VOUT of the multiphase control circuit, the second input terminal of the third voltage comparator COMP3 is coupled to the fourth reference voltage terminal VERF4, and the output terminal of the third voltage comparator COMP3 is coupled to the third input terminal of the AND gate A1.

[0070] Figure 5 for Figure 4 Timing diagrams of some signals in the circuit, such as Figure 5 As shown in this embodiment, in the first comparison circuit 100, a first voltage comparator COMP1 is used to compare with a first reference voltage. If the load is a small range, the output voltage will not be less than the reference voltage, that is, the VO_LOW signal is low, indicating that the output voltage only drops slightly. However, for a single phase in a multiphase control circuit, this is a heavy load that cannot be driven, and EAO_LOW will go low, triggering phase addition. A monostable multivibrator is set in the second comparison circuit 200. The pulse width of the monostable multivibrator is the clamping time, which forces the EAO voltage to the clamping reference voltage, thereby limiting the instantaneous peak current added by the multiphase, limiting the energy supplied to the output terminal, reducing the output voltage overshoot, and reducing the EAO undershoot, so that the phase reduction operation will not be triggered again, and the output voltage gradually adjusts from multiphase to stable.

[0071] In an optional embodiment of the present application, the first reference voltage VREF1 is used to compare with the sampling voltage VOUT of the multiphase control circuit to indicate the current load of the multiphase control circuit as a small range load according to the comparison result, the second reference voltage VREF2 is used to error amplify the feedback voltage of the multiphase control circuit to obtain an error amplification signal EAO to indicate the load condition in the current multiphase control circuit, the third reference voltage VREF3 is compared with the error amplification signal EAO to indicate the current load of the multiphase control circuit as a single item unable to drive load to trigger the phase adding operation, and the fourth reference voltage VREF4 is compared with the sampling voltage VOUT of the multiphase control circuit to indicate whether the current multiphase control circuit completes the soft start process according to the comparison result to control the peak current control circuit in the present application to perform the peak current control when the multiphase control circuit enters the working stage after completing the soft start.

[0072] In another optional embodiment of the present application, a peak current control circuit of a multiphase control circuit is provided, which comprises a first voltage comparator COMP1, a first inverter NG1, an error amplifier EA, a second voltage comparator COMP2, a second inverter NG2, a monostable trigger ONE SHOT, a voltage-controlled switch S1, an operational amplifier AMP, a third voltage comparator COMP3 and an AND gate A1.

[0073] The first input terminal of the first voltage comparator COMP1 is coupled to a first reference voltage terminal to receive a first reference voltage VREF1, and an output sampling voltage VOUT of the multiphase control circuit is provided to a second input terminal of the first voltage comparator COMP1; an output terminal of the first voltage comparator COMP1 is coupled to an input terminal of a first inverter NG1, and an output terminal of the first inverter NG1 is coupled to a first input terminal of an AND gate A1; a first input terminal of an error amplifier EA is coupled to a second reference voltage terminal, and a feedback voltage VFB of the multiphase control circuit is provided to a second input terminal of the error amplifier EA; an output terminal of the error amplifier EA is coupled to a first node N1; a first input terminal of a second voltage comparator COMP2 is coupled to a third reference voltage terminal, a second input terminal of the second voltage comparator COMP2 is coupled to the first node N1, and an output terminal of the second voltage comparator COMP2 is coupled to an input terminal of a second inverter NG2; an output terminal of the second inverter NG2 is coupled to an input terminal of a monostable trigger ONE SHOT; an output terminal of the monostable trigger is coupled to a second input terminal of the AND gate, and the monostable trigger ONE SHOT is configured to set a clamping duration of an error amplifier signal EAO according to a pulse width setting of the monostable trigger; a controlled terminal of a voltage-controlled switch S1 is coupled to an output terminal of the AND gate A1, a first terminal of the voltage-controlled switch S1 is coupled to the first node N1 to receive the error amplifier signal EAO, and a second terminal of the voltage-controlled switch S1 is coupled to a second input terminal of an operational amplifier AMP and an output terminal of the operational amplifier AMP; a first input terminal of the operational amplifier AMP is coupled to a clamping reference voltage terminal, and a clamping reference voltage EAO_CLAMP is provided to the first input terminal of the operational amplifier AMP; a first input terminal of a third voltage comparator COMP3 receives the output sampling voltage VOUT of the multiphase control circuit, a second input terminal of the third voltage comparator COMP3 is coupled to a fourth reference voltage terminal, and an output terminal of the third voltage comparator COMP3 is coupled to a third input terminal of the AND gate A1; the first input terminal of the AND gate A1 is coupled to the output terminal of the first inverter NG1, the second input terminal of the AND gate A1 is coupled to the output terminal of the monostable trigger ONE SHOT, the third input terminal of the AND gate A1 is coupled to the output terminal of the third voltage comparator COMP3, and the output terminal of the AND gate A1 is coupled to the controlled terminal of the voltage-controlled switch S1.

[0074] In another optional embodiment of the present application, a multi-phase control circuit is provided, which comprises an output voltage sampling circuit, a peak current control circuit and a phase selection switching circuit. The output voltage sampling circuit is configured to sample an output voltage of the multi-phase control circuit to obtain an output sampling voltage, and deliver the output sampling voltage to the peak current control circuit. The phase selection switching circuit is configured to perform a phase switching operation of the multi-phase control circuit according to a comparison result of a feedback voltage of the multi-phase control circuit and a reference voltage, and output a phase switching signal. The peak current control circuit is configured to control a peak current in the phase switching process according to the output sampling voltage and the phase switching signal, so as to avoid oscillation of the output voltage caused by load switching during the phase switching of the multi-phase control circuit.

[0075] The specific manners of performing operations of the units in the above embodiments have been described in detail in the embodiments of the method, and thus will not be described in detail here.

[0076] In summary, in the present application, a peak current control circuit of a multi-phase control circuit is provided, which comprises a first comparator circuit, an amplifier circuit, a second comparator circuit, an AND gate and a clamping signal control circuit. The first comparator circuit is configured to generate a first comparison signal according to an output sampling voltage of the multi-phase control circuit and a first reference voltage from a first reference voltage terminal, and deliver the first comparison signal to a first input terminal of the AND gate. The amplifier circuit is configured to generate an error amplification signal according to a feedback voltage of the multi-phase control circuit and a second reference voltage from a second reference voltage terminal, and deliver the error amplification signal to the second comparator circuit via a first node. The second comparator circuit is configured to generate a second comparison signal according to the error amplification signal and a third reference voltage from a third reference voltage terminal, and deliver the second comparison signal to a second input terminal of the AND gate. The AND gate is configured to receive the first comparison signal of the first comparator circuit and the second comparison signal of the second comparator circuit, and output a clamping trigger signal according to the first comparison signal and the second comparison signal. The clamping signal control circuit is configured to clamp a voltage value of the error amplification signal at a clamping reference voltage when the clamping trigger signal is at an effective level. By providing the first comparator circuit, the amplifier circuit, the second comparator, the AND gate and the clamping signal control circuit in the multi-phase control circuit, the peak current in the multi-phase control circuit is clamped by the clamping signal control circuit when the generated clamping trigger signal is at the effective level, so as to avoid rapid rise of the output voltage and great overshoot when the load switching is performed to increase the phase, trigger the phase reduction operation, cause continuous repetition of the phase increase and phase reduction operations, and cause large signal oscillation of the output voltage, thereby solving the problem of instability of the circuit in the multi-phase power supply control circuit in the prior art when the load is switched in a small range.

[0077] It is noted that the steps illustrated in the flowchart of the figure can be performed in a computer system such as a set of computer executable instructions executed by a computer system and while the logical flow of the steps is shown in the order they are performed, in some cases, the steps shown or described can be performed in a different order than shown or described.

[0078] Obviously, a person skilled in the art should appreciate that the units or steps of the present application described above can be implemented by a universal computing device, which can be centralized on a single computing device or distributed on a network composed of a plurality of computing devices, and alternatively, they can be implemented by program codes executable by a computing device, so that they can be stored in a storage device and executed by a computing device, or they can be respectively manufactured into each integrated circuit module, or a plurality of modules or steps among them can be manufactured into a single integrated circuit module. Thus, the present application is not limited to any particular hardware and software combination.

[0079] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A peak current control circuit for a multiphase control circuit, characterized in that, include: The circuit consists of a first comparator circuit, an amplifier circuit, a second comparator circuit, an AND gate, and a clamping signal control circuit. The first comparator circuit is configured to generate a first comparison signal based on the output sampling voltage of the multiphase control circuit and the first reference voltage from the first reference voltage terminal, and to transmit the first comparison signal to the first input terminal of the AND gate. The amplifier circuit is configured to generate an error amplification signal based on the feedback voltage of the multiphase control circuit and the second reference voltage from the second reference voltage terminal, and to transmit the error amplification signal to the second comparator circuit via the first node; The second comparator circuit is configured to generate a second comparison signal based on the error amplification signal and a third reference voltage from the third reference voltage terminal, and to pass the second comparison signal to the second input terminal of the AND gate; The AND gate is configured to receive a first comparison signal from the first comparator circuit and a second comparison signal from the second comparator circuit, and to output a clamping trigger signal based on the first comparison signal and the second comparison signal. The clamping signal control circuit is configured to clamp the voltage value of the error amplification signal at the clamping reference voltage when the clamping trigger signal is at an active level, wherein when the first reference voltage is less than the output sampling voltage, the first comparison signal is at an active level; and when the third reference voltage is less than the error amplification signal, the second comparison signal is at an active level.

2. The peak current control circuit according to claim 1, characterized in that, The first comparator circuit includes a first voltage comparator and a first inverter. The first input terminal of the first voltage comparator is coupled to the first reference voltage terminal to receive the first reference voltage, and the output sampling voltage of the multiphase control circuit is provided to the second input terminal of the first voltage comparator. The output of the first voltage comparator is coupled to the input of the first inverter, and the output of the first inverter is coupled to the first input of the AND gate.

3. The peak current control circuit according to claim 1, characterized in that, The amplifier circuit includes an error amplifier. The error amplifier has a first input terminal coupled to the second reference voltage terminal, and the feedback voltage of the multiphase control circuit is provided to the second input terminal of the error amplifier; the output terminal of the error amplifier is coupled to the first node.

4. The peak current control circuit according to claim 1, characterized in that, The second comparator circuit includes a second voltage comparator, a second inverter, and a monostable multivibrator. Wherein, the first input terminal of the second voltage comparator is coupled to the third reference voltage terminal, the second input terminal of the second voltage comparator is coupled to the first node, and the output terminal of the second voltage comparator is coupled to the input terminal of the second inverter; The output of the second inverter is coupled to the input of the monostable multivibrator; The output of the monostable multivibrator is coupled to the second input of the AND gate, and the monostable multivibrator is configured to set the clamping duration of the clamping signal control circuit according to the pulse width of the monostable multivibrator.

5. The peak current control circuit according to claim 1, characterized in that, The clamping signal control circuit includes a voltage-controlled switch and an operational amplifier. Wherein, the controlled terminal of the voltage-controlled switch is coupled to the output terminal of the AND gate, the first terminal of the voltage-controlled switch is coupled to the first node to receive the error amplification signal, and the second terminal of the voltage-controlled switch is coupled to the second input terminal and the output terminal of the operational amplifier; The first input terminal of the operational amplifier is coupled to the clamping reference voltage terminal, and the clamping reference voltage is provided to the first input terminal of the operational amplifier.

6. The peak current control circuit according to any one of claims 1 to 5, characterized in that, The peak current control circuit includes a third comparator circuit. The third comparator circuit is configured to generate a third comparison signal based on the output sampling voltage of the multiphase control circuit and the fourth reference voltage from the fourth reference voltage terminal, and to pass the third comparison signal to the third input terminal of the AND gate. When the fourth reference voltage is less than the output sampling voltage, the third comparison signal is at an active level.

7. The peak current control circuit according to claim 6, characterized in that, The third comparator circuit includes a third voltage comparator. The first input terminal of the third voltage comparator receives the output sampling voltage of the multiphase control circuit, the second input terminal of the third voltage comparator is coupled to the fourth reference voltage terminal, and the output terminal of the third voltage comparator is coupled to the third input terminal of the AND gate.

8. The peak current control circuit according to claim 1, characterized in that, When the first reference voltage is less than the output sampling voltage, the third reference voltage is less than the error amplification signal, and the fourth reference voltage is less than the output sampling voltage, the clamping trigger signal is at an active level, wherein the first reference voltage is greater than the fourth reference voltage, and the fourth reference voltage is the voltage from the fourth reference voltage terminal.

9. A peak current control circuit for a multiphase control circuit, characterized in that, include: The circuit consists of a first voltage comparator, a first inverter, an error amplifier, a second voltage comparator, a second inverter, a monostable multivibrator, a voltage-controlled switch, an operational amplifier, a third voltage comparator, and an AND gate. The first input terminal of the first voltage comparator is coupled to the first reference voltage terminal to receive the first reference voltage, and the output sampling voltage of the multiphase control circuit is provided to the second input terminal of the first voltage comparator. The output of the first voltage comparator is coupled to the input of the first inverter, and the output of the first inverter is coupled to the first input of the AND gate. The first input terminal of the error amplifier is coupled to the second reference voltage terminal, and the feedback voltage of the multiphase control circuit is provided to the second input terminal of the error amplifier; the output terminal of the error amplifier is coupled to the first node. The first input terminal of the second voltage comparator is coupled to the third reference voltage terminal, the second input terminal of the second voltage comparator is coupled to the first node, and the output terminal of the second voltage comparator is coupled to the input terminal of the second inverter. The output of the second inverter is coupled to the input of the monostable multivibrator; The output of the monostable multivibrator is coupled to the second input of the AND gate, and the monostable multivibrator is configured to set the clamping duration of the error amplification signal according to the pulse width of the monostable multivibrator. The controlled terminal of the voltage-controlled switch is coupled to the output terminal of the AND gate, the first terminal of the voltage-controlled switch is coupled to the first node to receive the error amplification signal, and the second terminal of the voltage-controlled switch is coupled to the second input terminal and the output terminal of the operational amplifier. The first input terminal of the operational amplifier is coupled to the clamping reference voltage terminal, and the clamping reference voltage is provided to the first input terminal of the operational amplifier. The first input terminal of the third voltage comparator receives the output sampling voltage of the multiphase control circuit, the second input terminal of the third voltage comparator is coupled to the fourth reference voltage terminal, and the output terminal of the third voltage comparator is coupled to the third input terminal of the AND gate. The first input terminal of the AND gate is coupled to the output terminal of the first inverter, the second input terminal of the AND gate is coupled to the output terminal of the monostable multivibrator, the third input terminal of the AND gate is coupled to the output terminal of the third voltage comparator, and the output terminal of the AND gate is coupled to the controlled terminal of the voltage-controlled switch.

10. A multiphase control circuit, characterized in that, Includes the peak current control circuit as described in any one of claims 1 to 9.

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