An L-band monolithic integrated power amplifier

Abstract

The present invention belongs to the field of semiconductor technology, and particularly relates to an L-band monolithic integrated power amplifier. The power amplifier includes: an input matching network unit, a transistor unit, and an output matching network unit; through the unique circuit structures of the input matching network unit and the output matching network unit, impedance matching of the input and output of the transistor unit under the GAN process is achieved, without the need for off-chip inductors and off-chip capacitors for matching, solving the problems of high cost, low efficiency, small bandwidth, and large size in the prior art for L-band power amplifiers.

Description

Technical Field

[0001] The present invention relates to a power amplifier integrated circuit, and particularly to an L-band monolithic integrated power amplifier, belonging to the field of semiconductor technology. Background Art

[0002] With the continuous development of radar technology, phased array radars are increasingly widely used. There are many transceiver components integrated inside phased array radars, and each transceiver component contains several transceiver channels. As one of the most core devices in the transceiver component, the size and performance of the power amplifier have a huge impact on the performance improvement of the entire phased array radar, especially on miniaturization. Compared with hybrid integrated circuits, monolithic power amplifier circuits can provide smaller sizes and better chip consistency; power amplifiers consume most of the energy of the system, and high-efficiency power amplifiers can reduce the management requirements for the heat dissipation system while increasing the device life, making it of great significance to improve their efficiency. Therefore, the research on high-efficiency power amplifiers is very necessary.

[0003] In the current semiconductor process, due to its limitations in power density, efficiency, etc., the CMOS process is not suitable for application in power amplifiers with a power level of 5 - 10W. There are many products based on GaAs process and GaN process in the power level of 5 - 10W. However, due to the power density limitation of the GaAs process itself (about 0.8W / mm), if a power amplifier above 5W is to be realized in the L-band, it is necessary to perform power synthesis with 8 cells or even more than 16 cells of transistors. In the L-band, the inductors used on the chip often have large inductance values, and multiple synthesis networks will also increase losses, resulting in a very large chip size. Compared with the GaAs process and the CMOS process, the GaN process has a power density of more than 5W / mm, which is more convenient for monolithic integration. However, in actual applications, affected by the matching factors of the input and output impedances of the power amplifier transistors, the bandwidth of high-efficiency power amplifiers in the current industrial L-band is often between 200 - 600MHz. For example, the product WFPN012014-P48 of CETC 55th Research Institute has a working frequency of 1.2 - 1.4GHz and a bandwidth of 200MHz; the efficiency of monolithic integrated power amplifier products that can cover a working bandwidth of 1 - 2GHz is less than 50%. For example, the product WFDN008020-P48 of CETC 55th Research Institute has a working frequency of 0.8 - 2.0GHz, a bandwidth of 1.2GHz, but the efficiency is only 45%; and many broadband products require off-chip inductors and off-chip capacitors for matching, increasing the size of the transceiver channels. For example, the product BW1180 of CETC 13th Research Institute has a working frequency of 0.2 - 1.8GHz and an efficiency of 54%, but it needs an off-chip inductor at the drain to work, which is not conducive to miniaturization design. At the same time, due to the additional factors introduced by assembly, the consistency between channels will become worse, making it unable to adapt to the transceiver components of L-band broadband phased array radars.

[0004] Therefore, it is of positive significance to study an L-band high-efficiency monolithic integrated power amplifier based on GaN technology covering the 1-2 GHz frequency band. SUMMARY OF THE INVENTION

[0005] In view of the improvement requirements in the above-mentioned existing technologies, the present invention proposes an L-band monolithic integrated power amplifier, whose operating frequency range is 1-2 GHz, covering the entire L-band and realizing the integration of all semiconductor devices on-chip. It has the advantages of low cost, high efficiency, wide bandwidth, small size, etc. in the emission channel, and is suitable for L-band broadband phased array radar transceiver modules.

[0006] The technical solution adopted by the present invention is as follows:

[0007] An L-band monolithic integrated power amplifier, comprising: an input matching network unit, a transistor unit, and an output matching network unit;

[0008] The input matching network unit includes resistors R1, R2, R3, capacitors C1, C2, C3, C4, inductors L1, L2, and L3; the first end of resistor R1 is connected to the first end of capacitor C4 and then respectively connected to the first ends of inductors L2 and L3. The second end of resistor R1 is connected to the second end of capacitor C4 and then used as the output of the input matching network unit to connect the transistor unit. The second end of inductor L2 is connected to the RF input signal RFin through capacitor C2. The second end of inductor L3 is connected to the first ends of resistor R3 and capacitor C3 after passing through resistor R2; the second end of resistor R3 is connected to the external gate bias voltage signal VG, and the second end of capacitor C3 is grounded; the first end of inductor L1 is connected to the RF input signal RFin, and the second end is grounded; the first end of capacitor C1 is respectively connected to the first end of inductor L1 and the end of capacitor C2 connected to the RF input signal RFin, and the other end is grounded;

[0009] The crystal unit includes transistors DM1 and DM2. The gates of transistors DM1 and DM2 are both connected to the signal node N1 for receiving the RF signal provided by the input stage matching unit; the sources of transistors DM1 and DM2 are both grounded. The drain of transistor DM1 is used as the first output end of the crystal unit to connect the first input port of the output matching network unit, and the drain of transistor DM2 is used as the second output end of the crystal unit to connect the second input port of the output matching network unit;

[0010] The output matching network unit includes transmission line T1, transmission line T2, transmission line T3, transmission line T4, capacitor C5, capacitor C6, capacitor C7, inductor L6 and resistor R4; the first end of transmission line T1 serves as the first input port of the output matching network unit and is connected to the first output end of the crystal unit, the second end of transmission line T1 is connected to the second end of transmission line T2 and then connected to the first end of transmission line T3, the first end of transmission line T2 serves as the second input port of the output matching network unit and is connected to the second output end of the crystal unit, the second end of transmission line T3 is respectively connected to the first end of transmission line T4 and the first end of capacitor C7, the second port of transmission line T4 is respectively connected to the first end of capacitor C5 and the first end of inductor L6, the second end of capacitor C5 is grounded, the second end of inductor L6 is respectively connected to the external drain bias VD of the chip and the first end of capacitor C6, the second end of capacitor C6 is grounded, and the second end of capacitor C7 is the output port of the output matching network unit; resistor R4 serves as a balancing resistor, one end of which is connected to the first end of transmission line T1 and the other end is connected to the first end of transmission line T2.

[0011] Further, the input matching network unit, the transistor unit and the output matching network unit are integrated on-chip using GaN-HEMT technology.

[0012] Further, all components in the input matching network unit and the output matching network unit are passive semiconductor devices, and the transistor DM1 and the transistor DM2 are both depletion-mode high electron mobility transistors.

[0013] After adopting the above technical solution, the present invention has the following advantages:

[0014] 1. Through the unique circuit structures of the input matching network unit and the output matching network unit, the present invention realizes the impedance matching of the input and output of the transistor unit under the GAN process, without the need for off-chip inductors and off-chip capacitors for matching, and solves the problems of high cost, low efficiency, small bandwidth, large size, etc. in the prior art applied to L-band power amplifiers.

[0015] 2. In the output matching network unit, the additionally provided inductor L6 can not only be used as a load end, but also further improve the gain of the device.

[0016] 3. Under the synergistic action of the unique input matching network unit, crystal unit and output matching network unit of the present invention, its operating frequency covers 1 - 2 GHz, the operating bandwidth is 1 GHz, the typical linear gain reaches 17 dB in the case of only adopting a single-stage amplification structure, the saturated output power is greater than 6W (38 dBm), and the typical value of the saturated output additional efficiency reaches 60%. Description of the Drawings

[0017] Figure 1Shows the schematic circuit diagram of an L-band monolithic integrated power amplifier proposed in the present invention;

[0018] Figure 2 Shows the linear gain curve diagram of an L-band monolithic integrated power amplifier proposed in the present invention;

[0019] Figure 3 Shows the input port return loss curve diagram of an L-band monolithic integrated power amplifier proposed in the present invention;

[0020] Figure 4 Shows the saturated output power curve diagram of an L-band monolithic integrated power amplifier proposed in the present invention;

[0021] Figure 5 Shows the saturated output additional efficiency curve diagram of an L-band monolithic integrated power amplifier proposed in the present invention;

[0022] Reference numerals:

[0023] 1. Input matching network unit, 2. Transistor unit, 3. Output matching network unit. Detailed implementation manners

[0024] In order to more clearly express the advantages of the present invention, the present invention will be described in more detail below in conjunction with the detailed implementation manners and the drawings. Those skilled in the art of integrated circuits should understand that the content covered by the present invention is general rather than specific, and the application fields can also be expanded, and the protection scope is not limited only to the described circuit structure.

[0025] Figure 1 Shows the schematic circuit diagram of an L-band monolithic integrated power amplifier proposed by the present invention, as Figure 1 shown. The circuit of the L-band monolithic integrated power amplifier includes an input matching network unit, a transistor unit, and an output matching network unit. The input of the input matching network unit is connected to the RF input signal RFin, and the output is connected to the input of the transistor unit; it completes the 50-ohm input matching of the RF input signal Rfin and converts the input RF voltage signal into an RF current signal. The transistor unit is a signal amplification unit, and its output is connected to the input of the output matching network unit, and is used to amplify the received RF current signal and then output it. The output matching network unit performs impedance matching on the amplified RF current signal and outputs the RF signal Rfout.

[0026] The input matching network unit includes a resistor R1, a resistor R2, a resistor R3, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, an inductor L1, an inductor L2, and an inductor L3; the first end of the resistor R1 is connected to the first end of the capacitor C4 and then respectively connected to the first ends of the inductor L2 and the inductor L3, the second end of the resistor R1 is connected to the second end of the capacitor C4 and then serves as the output of the input matching network unit to connect to the transistor unit, the second end of the inductor L2 is connected to the radio frequency input signal RFin through the capacitor C2, the second end of the inductor L3 is connected to the first ends of the resistor R3 and the capacitor C3 after passing through the resistor R2; the second end of the resistor R3 is connected to the external gate bias voltage signal VG, and the second end of the capacitor C3 is grounded; the first end of the inductor L1 is connected to the radio frequency input signal RFin, and the second end is grounded; the first end of the capacitor C1 is respectively connected to the first end of the inductor L1 and the end of the capacitor C2 connected to the radio frequency input signal RFin, and the other end is grounded.

[0027] The crystal unit includes a transistor DM1 and a transistor DM2. The gates of the transistor DM1 and the transistor DM2 are both connected to the signal node N1 to receive the radio frequency signal provided by the input stage matching unit; the sources of the transistor DM1 and the transistor DM2 are both grounded, the drain of the transistor DM1 serves as the first output end of the crystal unit to connect to the first input port of the output matching network unit, and the drain of the transistor DM2 serves as the second output end of the crystal unit to connect to the second input port of the output matching network unit. The output matching network unit includes a transmission line T1, a transmission line T2, a transmission line T3, a transmission line T4, a capacitor C5, a capacitor C6, a capacitor C7, an inductor L6, and a resistor R4; the first end of the transmission line T1 serves as the first input port of the output matching network unit to connect to the first output end of the crystal unit, the second end of the transmission line T1 is connected to the second end of the transmission line T2 and then connected to the first end of the transmission line T3, the first end of the transmission line T2 serves as the second input port of the output matching network unit to connect to the second output end of the crystal unit, the second end of the transmission line T3 is respectively connected to the first end of the transmission line T4 and the first end of the capacitor C7, the second port of the transmission line T4 is respectively connected to the first end of the capacitor C5 and the first end of the inductor L6, the second end of the capacitor C5 is grounded, the second end of the inductor L6 is respectively connected to the external drain bias VD outside the chip and the first end of the capacitor C6, the second end of the capacitor C6 is grounded, and the second end of the capacitor C7 is the output port of the output matching network unit; the resistor R4 serves as a balancing resistor to prevent the power amplifier from generating odd-mode oscillation, one end of which is connected to the first end of the transmission line T1, and the other end is connected to the first end of the transmission line T2.

[0028] In use, each unit cooperates with each other to convert the input radio frequency signal Rfin into a radio frequency signal Rfout for output. In the input matching network unit, the capacitor C2 serves as a DC-blocking capacitor of the input matching unit and also participates in the 50-ohm impedance matching; the resistor R2 is used to reduce the Q value of the input matching network; the capacitor C3 serves as an on-chip filtering capacitor for the external gate bias port of the chip; the resistor R3 connected to the external gate bias voltage signal VG has a value of -2V; through the parallel combination of the resistor R1 and the capacitor C4 with the capacitor C2, the resistor R2, the capacitor C3, and the resistor R3, the stability of the entire device is improved. In the crystal unit, both transistors are GaN-HEMTs and their sizes are exactly the same, and they are connected in parallel to achieve power amplification. In the output matching network unit, according to the microwave network matching principle, the value ranges of the transmission line T4, the capacitor C5, and the inductor L6 are set, and impedance tuning is achieved through the set value ranges of the transmission line T4, the capacitor C5, and the inductor L6 to improve the drain emission efficiency; the second port of the inductor L6 is connected to the first port of the capacitor C6 and is also connected to the external drain bias VD of the chip, with VD having a value of 28V, and the second port of the capacitor C6 is grounded, which serves as a filtering function for the drain bias port of the chip. The capacitor C7 serves as a DC-blocking capacitor to enhance the stability of the device at the output end.

[0029] 2 Figure 2 Shows the linear gain curve of an L-band monolithic integrated power amplifier proposed in the present invention. As Figure 2 can be seen, the linear gain of the power amplifier in this embodiment is approximately 28 dB within the operating frequency band and exhibits a positive slope gain characteristic.

[0030] Figure 3 Shows the input port return loss curve of an L-band monolithic integrated power amplifier proposed in the present invention. As Figure 3 can be seen, the voltage standing wave ratio at the input port is approximately 1.1 within the operating frequency band, indicating good matching at the input port.

[0031] Figure 4 Shows the saturated output power curve of an L-band monolithic integrated power amplifier proposed in the present invention;. As Figure 4 can be seen, the saturated output power is greater than 27 dBm within the operating frequency band and exhibits a positive slope power output characteristic.

[0032] Figure 5 Shows the saturated output additional efficiency curve of an L-band monolithic integrated power amplifier proposed in the present invention. As Figure 5 can be seen, the saturated output additional efficiency is greater than 45% within the operating frequency band, which is suitable for application in most radar transmitting channels.

[0033] In summary, the present invention solves the application problems of multiple core indicators such as bandwidth, efficiency, and size of the L-band power amplifier. By integrating inductors on-chip and using a single-stage amplification structure, low cost and miniaturization are achieved. It is suitable for use as the final-stage power amplifier in the L-band broadband phased array radar transceiver module, and also suitable for use as the sub-final-stage power driver in the L-band broadband phased array radar transceiver module. Only drain voltage bias and gate voltage bias are required outside the chip, and the application in the transceiver module through monolithic integration is extremely simple and convenient.

[0034] The above embodiments are only specific examples for more clearly illustrating the present invention, rather than limitations on the embodiments of the present invention. For engineers and technicians in the semiconductor field, other different forms of extensions can be made based on the above description. It is impossible to enumerate all the embodiments here. Any obvious changes or variations derived from the technical solutions of the present invention fall within the protection scope of the present invention.

Claims

1. An L-band monolithic integrated power amplifier, comprising: An input matching network unit, a transistor unit, and an output matching network unit, characterized in that: The input matching network unit includes a resistor R1, a resistor R2, a resistor R3, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, an inductor L1, an inductor L2, and an inductor L3; the first end of the resistor R1 is connected to the first end of the capacitor C4 and then respectively connected to the first ends of the inductor L2 and the inductor L3, the second end of the resistor R1 is connected to the second end of the capacitor C4 and then serves as the output of the input matching network unit to connect to the transistor unit, the second end of the inductor L2 is connected to the radio frequency input signal RFin through the capacitor C2, the second end of the inductor L3 is connected to the first ends of the resistor R2, the resistor R3, and the capacitor C3 after passing through the resistor R2; the second end of the resistor R3 is connected to the external gate bias voltage signal VG, and the second end of the capacitor C3 is grounded; the first end of the inductor L1 is connected to the radio frequency input signal RFin, and the second end is grounded; the first end of the capacitor C1 is connected to the first end of the inductor L1 and the end of the capacitor C2 connected to the radio frequency input signal RFin, and the other end is grounded; The transistor unit includes a transistor DM1 and a transistor DM2. The gates of the transistor DM1 and the transistor DM2 are both connected to the signal node N1 for receiving the radio frequency signal provided by the input stage matching unit; the sources of the transistor DM1 and the transistor DM2 are both grounded, the drain of the transistor DM1 serves as the first output end of the crystal unit to connect to the first input port of the output matching network unit, and the drain of the transistor DM2 serves as the second output end of the crystal unit to connect to the second input port of the output matching network unit; The output matching network unit includes a transmission line T1, a transmission line T2, a transmission line T3, a transmission line T4, a capacitor C5, a capacitor C6, a capacitor C7, an inductor L6, and a resistor R4; the first end of the transmission line T1 serves as the first input port of the output matching network unit to connect to the first output end of the crystal unit, the second end of the transmission line T1 is connected to the second end of the transmission line T2 and then connected to the first end of the transmission line T3, the first end of the transmission line T2 serves as the second input port of the output matching network unit to connect to the second output end of the crystal unit, the second end of the transmission line T3 is respectively connected to the first end of the transmission line T4 and the first end of the capacitor C7, the second port of the transmission line T4 is respectively connected to the first end of the capacitor C5 and the first end of the inductor L6, the second end of the capacitor C5 is grounded, the second end of the inductor L6 is respectively connected to the external drain bias VD outside the chip and the first end of the capacitor C6, the second end of the capacitor C6 is grounded, and the second end of the capacitor C7 is the output port of the output matching network unit; the resistor R4 serves as a balancing resistor, one end of which is connected to the first end of the transmission line T1 and the other end is connected to the first end of the transmission line T2.

2. The L-band monolithic integrated power amplifier according to claim 1, characterized in that: The input matching network unit, the transistor unit, and the output matching network unit are integrated on-chip using GaN-HEMT technology.

3. The L-band monolithic integrated power amplifier according to claim 1, characterized in that: All components in the input matching network unit and the output matching network unit are passive semiconductor devices, and the transistors DM1 and DM2 are both depletion-mode high electron mobility transistors.

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