A three-level high-voltage drive conversion circuit for an electron-multiplying CCD

Abstract

The present invention relates to a three-level high-voltage drive conversion circuit for an electron multiplying CCD, which includes a host computer and a main control module connected in sequence. The main control module is respectively connected to a front-stage timing level conversion circuit, a high-level drive module, and a medium and low-level drive module. The front-stage timing level conversion circuit, the high-level drive module, and the medium and low-level drive module are respectively connected to a push-pull drive circuit. The three-level drive conversion circuit of the electron multiplying CCD of the present invention can arbitrarily adjust the high, medium, and low three-level values of the drive signal through the main control module, and the waveform establishment time reaches the nanosecond level. At the same time, the high-level drive voltage can exceed 35V, meeting the requirements of the high-voltage drive signal required for multiplication within the pixels of the electron multiplying CCD. It can conveniently set the three-level multiplication drive signal of any electron multiplying CCD circuit to achieve its best imaging effect.

Description

Technical Field:

[0001] The present invention relates to the technical field of electron multiplying CCD, and specifically to a three-level high-voltage drive conversion circuit for an electron multiplying CCD. Background Art:

[0002] The electron multiplying CCD technology belongs to the field of low-light imaging. The electron multiplying CCD circuit has advantages such as high sensitivity, low noise, and high quantum efficiency. When some electron multiplying CCD image sensors work, three-level signals need to be applied, namely low level, medium level, and high level, to provide a multiplication drive signal for the electron multiplying CCD. To achieve a better imaging effect, there are higher requirements for the amplitude of the input signal of the multiplication stage of the electron multiplying CCD, generally reaching 20V - 50V. When the amplitude of the input signal of the multiplication stage is lower than 20V, the impact ionization effect will not occur. When the pixel is in the multiplication operation, a high-level high-voltage drive signal is required, and when it is not in the multiplication operation, a medium-low level drive signal is required.

[0003] Currently, most of the CCD drive timing signal designs on the market use a main control module to generate TTL level signals, and then perform power drive on the timing signals to generate drive signals that meet the CCD timing. However, because the main control chips such as FPGA only have two logic states of "0" and "1", the drive signals generated in this way only have two states of high level and low level, and it is impossible to generate a third-level signal. Therefore, a dedicated three-level high-voltage drive conversion circuit for the electron multiplying CCD needs to be designed independently.

[0004] After searching existing patents, the Chinese utility model patent "A Special Three-Level Drive Circuit for CCD" (authorization number CN203563048U) realizes a special three-level drive circuit for a CCD image sensor circuit, but it cannot provide the high-voltage drive signal required for the operation of the electron multiplying CCD. The Chinese invention patent "A Numerical Control High-Voltage Multiplication Circuit for EMCCD" (patent number CN104735370B), including a DC level conversion circuit, a digital-to-analog conversion circuit, and a push-pull drive circuit, provides a numerical control high-voltage multiplication circuit for EMCCD, which meets the multiplication stability and has the characteristics of miniaturization and low power consumption. This patent provides a numerical control high-voltage multiplication circuit required for CCD multiplication, but it does not solve the three-level drive signal required for the operation of the electron multiplying CCD. The article "Design of a Three-Level Step Waveform CCD Timing Drive Circuit" in the 5th issue of the 33rd volume of the Optical Technology Journal introduces a three-level drive circuit required for driving a CCD chip, but it cannot provide the high-voltage drive signal required for the operation of the electron multiplying CCD. Summary of the Invention:

[0005] The purpose of the present invention is to solve the deficiencies existing in the prior art and provide a three-level high-voltage drive conversion circuit for an electron multiplying CCD.

[0006] The present invention adopts the following technical solutions:

[0007] A three-level high-voltage drive conversion circuit for an electron multiplying CCD, comprising a host computer and a main control module connected in sequence, the main control module is respectively connected to a front-stage timing level conversion circuit, a high-level drive module and a medium-low level drive module, and the front-stage timing level conversion circuit, the high-level drive module and the medium-low level drive module are respectively connected to a push-pull drive circuit.

[0008] The host computer converts the set high and low level values into digital signals and transmits them to the main control module, and then the main control module controls the high-level drive module and the medium-low level drive module to output corresponding high levels and medium-low levels as the drive signals of the push-pull drive circuit; the main control module outputs a path of timing control signal, which is converted into two paths of timing signals with opposite phases and increased level amplitudes through the front-stage timing level conversion circuit, as the timing signals of the subsequent push-pull drive circuit.

[0009] The push-pull drive circuit selects a pair of NMOS transistors and PMOS with matching parameters as the power drive chip.

[0010] Advantages of the invention

[0011] The three-level drive conversion circuit of the electron multiplying CCD can arbitrarily adjust the high, medium and low three-level values of the drive signal through the main control module, the waveform establishment time reaches the nanosecond level, and at the same time the high-level drive voltage can exceed 35V, meeting the requirements of the high-voltage drive signal required for multiplication inside the pixel of the electron multiplying CCD, and can conveniently and arbitrarily set the three-level multiplication drive signal of the electron multiplying CCD circuit to achieve its best imaging effect.

[0012] The three-level high-voltage drive conversion circuit for an electron multiplying CCD of the present invention can simultaneously output a three-level high-voltage drive signal with adjustable amplitude, providing a three-level clock pulse signal required for the multiplication operation of the electron multiplying CCD device. In order to enable the clock pulse signal to drive the high capacitive load of the input pin of the electron multiplying CCD, the pulse signal source needs to have a strong instantaneous large current driving ability, and the three levels (high level, medium level and low level) of the pulse signal source can be adjusted in real time according to needs. Description of the drawings:

[0013] Figure 1 is the principle block diagram of the present invention;

[0014] Figure 2 is the circuit schematic diagram of the present invention. Specific implementation manners:

[0015] The present invention will be further described below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention and cannot be used to limit the protection scope of the present invention.

[0016] As Figure 1 shown, a three-level high-voltage drive conversion circuit for an electron-multiplying CCD provided by the present invention includes a host computer and a main control module connected in sequence. The main control module is respectively connected to a front-stage timing level conversion circuit, a high-level drive module, and a medium-low level drive module. The front-stage timing level conversion circuit, the high-level drive module, and the medium-low level drive module are respectively connected to a push-pull drive circuit.

[0017] The host computer converts the set high and low level values into digital signals and transmits them to the main control module. Then, the main control module controls the high-level drive module and the medium-low level drive module to output corresponding high levels and medium-low levels as drive signals for the push-pull drive circuit. The main control module outputs a path of timing control signal, which is converted into two timing signals with opposite phases and increased level amplitudes by the front-stage timing level conversion circuit and used as the timing signals for the subsequent push-pull drive circuit.

[0018] The working timing of the three-level drive circuit can be split into two working states, namely high level -> low level and medium level -> low level. Among the high, medium, and low three-level states, the low level and the medium level are the two logic states of "0" and "1" of a conventional digital signal, and the high level is the high-voltage drive signal required for the multiplication stage of the electron-multiplying CCD, generally reaching 20V to 50V.

[0019] When the high level -> low level working state is selected, the medium-low level drive module outputs a low level, and the high-level drive module outputs a high level. The signal levels input to the gates of the N-type MOS transistor and the P-type MOS transistor are the same in amplitude and opposite in phase. The two MOS transistors conduct alternately to generate a high-low level clock drive signal.

[0020] When the medium level -> low level working state is selected, the N-type MOS transistor is continuously turned off, the P-type MOS transistor is continuously turned on, and the medium-low level drive module EL7156 outputs a medium-low level pulse drive signal, which is driven by the NMOS transistor and output to the electron-multiplying CCD. Through program control, the design of the three-level high-voltage drive module required for the electron-multiplying CCD is realized.

[0021] As Figure 2 shown, the main control module outputs two control signals. One control signal (i.e., the input signal of the medium-low level drive module of Figure 2 ) is output to the medium-low level drive module as an input signal and is connected to the 3rd pin of the operational amplifier U1 (EL7156) through the resistor R2.

[0022] The low and medium level conversion module consists of EL7156 and its peripheral circuits. The main function of the EL7156 module is to perform level conversion and current amplification on the control signal (input signal of the low and medium level drive module) sent by the main control module, provide a low and medium level drive signal for the push-pull drive circuit, and then output it to the multiplication signal terminal of the CCD through the push-pull drive circuit.

[0023] Since the output level of the conventional digital signal channel board can meet the requirements of the amplitude of the conventional drive signal level of the electron multiplying CCD, but because the input pins of the electron multiplying CCD are all high capacitive loads (reaching the nF level), the channel board cannot be directly used for driving. Otherwise, the rising edge of the waveform will become slow due to the too long charging time, which will further affect the working frequency.

[0024] Therefore, a high-speed integrated drive chip is selected for the low and medium level drive module of the electron multiplying CCD to provide driving ability. The EL7156 chip is selected to perform level conversion and current amplification on the drive signal sent by the main control module. EL7156 is a single-channel TTL drive chip with a peak drive current of 3.5A, which fully meets the drive requirements of the input end of the electron multiplying CCD.

[0025] Pin 1 and pin 5 of the EL7156 integrated chip are connected to the power supply terminals V+ and V- to provide fixed positive and negative power supplies for the circuit respectively, and pin 4 is grounded. Pins 8 and 6 of EL7156 are the medium level voltage input terminal and the low level voltage input terminal. Two capacitors C3, C5 and resistor R7 form a DC filter network for filtering the DC level input to pin 8. Two capacitors C4, C6 and resistor R8 form a DC filter network for filtering the DC level input to pin 6. The medium and low levels of the three-level drive circuit can be set as needed. For example, the medium level drive voltage and the low level drive voltage are set for pins 8 and 6 of EL7156 through a programmable digital-to-analog converter. The medium and low levels of the AC waveform are output through pin 7 of the EL7156 circuit, and resistor R1 is the current limiting resistor for outputting the medium and low levels. Pin 3 of the EL7156 circuit is the input waveform terminal, which is connected to the working waveform of the input signal of the main control module (i.e., the input signal of the low and medium level drive module). The working waveform of the input signal is converted into a medium and low level with an unchanged frequency and a programmable control output waveform by the drive chip EL7156, and the medium and low level drive waveform is connected to the source electrode of the push-pull drive circuit Q1. Pin 2 of the EL7156 circuit is the enable terminal, and the operation of the EL7156 chip is controlled by the main control module.

[0026] Figure 2 The high level drive module consists of resistor R14, capacitor C11 and capacitor C12. The input end of resistor R14 is connected to the high level drive voltage, and capacitor C11 is connected to the input end of resistor R14 with the other end grounded; the output end of resistor R14 is used as the output end of the high level drive module, and capacitor C12 is connected to this section with the other end grounded.

[0027] Figure 2 The medium-high level drive module is a programmable DC voltage, and the high-level drive voltage is directly set by a programmable power supply controlled by a host computer.

[0028] The push-pull drive circuit selects a pair of NMOS and PMOS transistors with matching parameters as the power drive chip, which has the characteristics of high drain-source breakdown voltage, small on-resistance, and strong driving ability. The PMOS transistor Q1, NMOS transistor Q2, and resistors R9, R10, R11, R12, and R13 form a push-pull drive circuit. Resistor R12 is connected to the source terminal of Q2, and resistor R13 is connected to the drain terminal of Q1. Their function is to limit the drain current of the MOS transistor and prevent abnormal current from damaging the MOS transistor, playing a protective role. The gates of Q1 and Q2 are respectively connected to one end of resistors R11 and R10. The other ends of resistors R10 and R11 are respectively connected to the 6th and 7th pins of the operational amplifier U2 (SI8271) of the pre-stage timing conversion circuit, and the other ends of resistors R10 and R11 are connected in parallel with resistor R9.

[0029] The medium-low level output by the medium-low level drive module is connected to the source of Q1, and the high level output by the high-level drive module is connected to the drain of Q2.

[0030] When the signal level input to the gate of the N-type MOS transistor Q2 changes from high to low, the signal input to the gate of the P-type MOS transistor Q1 remains low. The N-type MOS transistor conducts, and the P-type MOS transistor turns off, and the dynode signal outputs a high level. When the signal level input to the gate of the P-type MOS transistor changes from low to high, the signal input to the gate of the N-type MOS transistor remains high. The P-type MOS transistor conducts, and the N-type MOS transistor turns off, and the output of the dynode signal changes from high level to low level, avoiding the simultaneous conduction of the two transistors.

[0031] The push-pull drive circuit selects the high-level drive module and the medium-low level drive module as the high, medium, and low levels of the drive signal under the control of the timing signal.

[0032] The pre-stage timing conversion circuit consists of the operational amplifier U2 SI8271 and its peripheral circuits. Its main function is to convert a path of timing control signal input by the main control module into two drive signals with the same frequency and opposite phases. One path is connected from the 7th pin VO+ of SI8271 to R11 of the push-pull drive circuit, and the other path is connected from the 6th pin VO- of SI8271 to R10 of the push-pull drive circuit. At the same time, the 7th pin VO+ is connected to the 3rd pin of D1 BAT54S. BAT54S is a dual diode, with the 1st pin connected to -10V and the 2nd pin connected to +20V. BAT54S is used for output voltage clamping to clamp the output potential between -10.32V and 20.32V.

[0033] The 6-pin VO- terminal is connected to the 3-pin of D2 BAT54S. The 1-pin of D2 is connected to -10V, and the 2-pin is connected to +20V for output voltage clamping. The 8-pin of the circuit is connected to the +20V power supply voltage. At the same time, two voltage-regulating diodes D4 and D5 are connected to the ground. The functions of D4 and D5 are to regulate the positive power supply. At the same time, a 1u capacitor C8 is connected to the ground for filtering. The 5-pin of the circuit is connected to the -10V power supply voltage. At the same time, a voltage-regulating diode D3 is connected to the ground. The function of D3 is to regulate the negative power supply. At the same time, a 1u capacitor C9 is connected to the ground for filtering. The 2-pin VDDI and the 4-pin enable terminal of the circuit are short-circuited and connected to the 5V power supply terminal. At the same time, a 1u capacitor C7 is connected to the ground for filtering. The 3-pin GNDI is connected to the ground terminal. The 1-pin VI is connected to the timing output terminal of the main control module through a resistor R5 to receive the timing control signal input by the main control module. At the same time, a resistor R6 is connected to the ground.

Claims

1. A three-level high-voltage drive conversion circuit for an electron-multiplying CCD, comprising a host computer and a main control module connected in sequence. It is characterized in that: The main control module is respectively connected to a front-stage timing level conversion circuit, a high-level drive module, and a medium-low level drive module. The front-stage timing level conversion circuit, the high-level drive module, and the medium-low level drive module are respectively connected to a push-pull drive circuit; The host computer converts the set high and low level values into digital signals and transmits them to the main control module, and then the main control module controls the high-level drive module and the medium-low level drive module to output corresponding high levels and medium-low levels as drive signals for the push-pull drive circuit; The main control module outputs a path of timing control signal, which is converted into two timing signals with opposite phases and increased level amplitudes through the front-stage timing level conversion circuit, and serves as the timing signal for the subsequent push-pull drive circuit.

2. The three-level high-voltage drive conversion circuit for an electron-multiplying CCD according to claim 1, characterized in that: The front-stage timing conversion circuit is composed of an operational amplifier SI8271 chip and its peripheral circuits. The 1st pin VI of SI8271 is connected to the resistor R5 to the timing output terminal of the main control module to receive the timing control signal input by the main control module, and is simultaneously connected to the resistor R6 to ground; The 7th pin VO+ of SI8271 is connected to R11 of the push-pull drive circuit, and the 6th pin VO- of SI8271 is connected to R10 of the push-pull drive circuit. At the same time, the 7th pin VO+ is connected to the 3rd pin of D1 BAT54S. BAT54S is a double diode, the 1st pin is connected to -10V, the 2nd pin is connected to +20V. BAT54S is used for output voltage clamping to clamp the output potential between -10.32V and 20.32V; The 6th pin VO- is connected to the 3rd pin of D2 BAT54S. The 1st pin of D2 is connected to -10V, the 2nd pin is connected to +20V for output voltage clamping; the 8th pin of the circuit is connected to the +20V power supply voltage, and is simultaneously connected to two voltage-regulator diodes D4 and D5 to ground. The functions of D4 and D5 are positive power supply voltage regulation, and a 1u capacitor C8 is simultaneously connected to ground for filtering; the 5th pin of the circuit is connected to the -10V power supply voltage, and is simultaneously connected to the voltage-regulator diode D3 to ground. The function of D3 is negative power supply voltage regulation, and a 1u capacitor C9 is simultaneously connected to ground for filtering; The 2nd pin VDDI and the 4th pin EN enable terminal of the circuit are short-circuited and connected to the 5V power supply terminal, and a 1u capacitor C7 is simultaneously connected to ground for filtering.

3. The three-level high-voltage drive conversion circuit for an electron-multiplying CCD according to claim 1, characterized in that: The high-level drive module is composed of a resistor R14, a capacitor C11, and a capacitor C12. The input end of the resistor R14 is connected to the high-level drive voltage, and the capacitor C11 is connected between the input end of the resistor R14 and the other end grounded; the output end of the resistor R14 serves as the output end of the high-level drive module, and this end is connected to the capacitor C12, and the other end of the capacitor C12 is grounded. The high-level drive module is a programmable DC voltage, and the high-level drive voltage is directly set by the host computer controlling the programmable power supply.

4. The three-level high-voltage drive conversion circuit for an electron-multiplying CCD according to claim 1, 2 or 3, characterized in that: The low and medium level driving module consists of an EL7156 and its peripheral circuit. Pins 8 and 6 of the EL7156 are the medium level voltage input terminal and the low level voltage input terminal. Two capacitors C3, C5 and a resistor R7 form a DC filtering network for filtering the DC level input to pin 8; two capacitors C4, C6 and a resistor R8 form a DC filtering network for filtering the DC level input to pin 6. The medium and low level of the AC waveform is output from pin 7 of the EL7156 chip through a resistor R1. Pin 3 of the EL7156 circuit is the input waveform terminal, which is connected to the input signal of the low and medium level driving module of the main control module. The working waveform of the input signal is converted into a medium and low level with an unchanged frequency and a programmable control output waveform by the driving chip EL7156.

5. A three-level high-voltage driving conversion circuit for an electron multiplying CCD according to claim 1, 2 or 3, characterized in that: The push-pull driving circuit consists of a PMOS transistor Q1, an NMOS transistor Q2 and resistors R9, R10, R11, R12, R13. Resistor R12 is connected to the source terminal of Q2, and resistor R13 is connected to the drain terminal of Q1. The gates of Q1 and Q2 are respectively connected to one ends of resistors R11 and R10. The other ends of resistors R10 and R11 are respectively connected to pins 6 and 7 of the operational amplifier SI8271 of the previous stage timing conversion circuit. The other ends of the resistors R10 and R11 are connected in parallel with a resistor R9.

6. A three-level high-voltage driving conversion circuit for an electron multiplying CCD according to claim 4, characterized in that: The push-pull driving circuit consists of a PMOS transistor Q1, an NMOS transistor Q2 and resistors R9, R10, R11, R12, R13. Resistor R12 is connected to the source terminal of Q2, and resistor R13 is connected to the drain terminal of Q1. The gates of Q1 and Q2 are respectively connected to one ends of resistors R11 and R10. The other ends of resistors R10 and R11 are respectively connected to pins 6 and 7 of the operational amplifier SI8271 of the previous stage timing conversion circuit. The other ends of the resistors R10 and R11 are connected in parallel with a resistor R9.

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