Overvoltage protection scheme for connector ports

Abstract

Certain aspects of the present disclosure generally relate to methods and apparatus for providing overvoltage protection for circuitry coupled to a connector port such as a USB-C port. An example circuit for overvoltage protection between a connector port and a signal node corresponding to the connector port generally includes: a first switch having a first terminal for coupling to the connector port and a second terminal for coupling to the signal node; a first resistive element coupled in parallel with the first switch; a first transient protection circuit coupled between the signal node and a reference potential node; and a control circuit having an input coupled to the signal node and a first output having a control input coupled to the first switch.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to U.S. Application No. 17 / 325,463, filed on May 20, 2021, which claims the benefit and priority of U.S. Provisional Application No. 63 / 029,322, filed on May 22, 2020, the entire contents of both of which are hereby expressly incorporated herein by reference as if fully set forth below and for all applicable purposes. Technical Field

[0003] Certain aspects of the present disclosure generally relate to electronic circuits, and more particularly to overvoltage protection circuits and techniques. Background Art

[0004] Electronic circuits are designed to operate at certain maximum voltages at different nodes therein. When the voltage at a circuit node exceeds the maximum voltage limit, this condition is referred to as overvoltage and can be harmful to the circuit. Overvoltage events can be constant (e.g., direct current (DC) overvoltage) or transient (e.g., voltage spikes). Overvoltage protection devices can be used to protect circuits from overvoltage events. Summary of the Invention

[0005] The systems, methods, and devices of the present disclosure each have several aspects, no single one of which is solely responsible for its desirable attributes. Without limiting the scope of the present disclosure as expressed by the appended claims, some features will now be briefly discussed. After considering this discussion, and particularly after reading the section entitled "Detailed Description," one will understand how the features of the present disclosure provide advantages including circuits that provide overvoltage protection for connector ports and can be scaled as desired for multiple connector ports.

[0006] Certain aspects of the present disclosure generally relate to techniques and apparatus for providing overvoltage protection for circuits coupled to connector ports such as USB or USB-C ports.

[0007] Certain aspects of the present disclosure provide a circuit for overvoltage protection (OVP) between a connector port and a signal node corresponding to the connector port. The OVP circuit generally includes: a first switch having a first terminal for coupling to the connector port and a second terminal for coupling to the signal node; a first resistive element coupled in parallel with the first switch; a first transient protection circuit coupled between the signal node and a reference potential node; and a control circuit having an input coupled to the signal node and a first output coupled to a control input of the first switch.

[0008] Certain aspects of the present disclosure provide a method for providing overvoltage protection between a connector port and a signal node corresponding to the connector port. The method generally includes: in response to a first voltage exceeding a clamping voltage of a first transient protection circuit, suppressing the first voltage at the signal node to a second voltage using the first transient protection circuit, wherein the first transient protection circuit is coupled between the signal node and a reference potential node. The method further includes comparing the second voltage with a reference voltage using a control circuit having an input coupled to the signal node and having a first output coupled to a control input of a first switch, wherein the first switch has a first terminal coupled to the connector port, a second terminal coupled to the signal node, and is coupled in parallel with a first resistive element. The method further includes disconnecting the first switch using the control circuit based on the comparison.

[0009] To achieve the foregoing and related purposes, one or more aspects include the features that are fully described hereinafter and particularly pointed out in the claims. The following description and the drawings set forth in detail certain illustrative features of one or more aspects. However, these features are only some of the various ways in which the principles of the various aspects may be employed. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] For a more particular description of the features briefly summarized above, reference may be had to the aspects, some of which are illustrated in the drawings. It is to be noted, however, that the drawings illustrate only certain typical aspects of the present disclosure and are therefore not to be considered limiting of its scope, for the description may admit to other equally effective aspects.

[0011] Figure 1 A block diagram of an example device including an overvoltage protection (OVP) circuit in accordance with certain aspects of the present disclosure is illustrated.

[0012] Figure 2 is an example block diagram illustrating various components connected to a connector socket via an optional OVP for some connector pins.

[0013] Figure 3 is a circuit diagram of an example OVP circuit in accordance with certain aspects of the present disclosure.

[0014] Figure 4 is illustrated in accordance with certain aspects of the present disclosure Figure 3 An example timing diagram of various voltage waveforms of the OVP circuit before, during, and after an overvoltage event.

[0015] Figure 5 is a circuit diagram of another example OVP circuit in accordance with certain aspects of the present disclosure.

[0016] Figure 6 is a flowchart illustrating an example operation for providing OVP for a signal node corresponding to a connector port in accordance with certain aspects of the present disclosure.

[0017] For ease of understanding, wherever possible, the same reference numerals are used to denote the same elements common to the figures. It is contemplated that elements disclosed in one aspect may be beneficially utilized in other aspects without specific recitation. Detailed Description

[0018] Certain aspects of the present disclosure provide overvoltage protection circuits (OVP) and techniques for overvoltage protection. Certain devices having input-output (I / O) connectors (such as a Universal Serial Bus (USB) Type-C socket) may employ various OVP schemes to prevent electrical overstress (EOS) damage to integrated circuits (ICs) coupled to the I / O connector. Certain OVP schemes may be too complex and / or expensive to provide OVP for multiple pins on the I / O connector. Certain aspects of the present disclosure provide relatively less expensive OVP techniques and devices (in terms of cost and circuit board area) than other OVP schemes described herein, provide suitable transient and DC overvoltage protection, and provide fewer pin / trace counts.

[0019] Aspects of the present disclosure are described more fully hereinafter with reference to the accompanying drawings. However, the present disclosure may be embodied in many different forms and should not be construed as limited to any specific structure or function presented throughout this disclosure. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Based on the teachings herein, those skilled in the art should appreciate that the scope of the present disclosure is intended to cover any aspect of the present disclosure disclosed herein, whether implemented independently of any other aspect of the present disclosure or implemented in combination with any other aspect of the present disclosure. For example, any number of the aspects set forth herein may be used to implement a device or practice a method. In addition, the scope of the present disclosure is intended to cover such devices or methods that practice using other structures, functionality, or a combination of structures and functionality in addition to or different from the aspects of the present disclosure set forth herein. It should be understood that any aspect of the present disclosure disclosed herein may be embodied by one or more elements of a claim.

[0020] The word “exemplary” as used herein means “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0021] As used herein, the term "connected to" in various tenses of the verb "connect" can mean that element A is directly connected to element B, or that other elements can be connected between elements A and B (i.e., element A is indirectly connected to element B). In the case of electrical components, the term "connected to" can also be used herein to mean that element A and B are electrically connected using a wire, trace, or other conductive material (and any components electrically connected therebetween).

[0022] Example device

[0023] It should be understood that aspects of the present disclosure can be used in a variety of applications. Although the present invention is not limited thereto, the circuits disclosed herein can be used in many devices, such as computers, communication systems, televisions, audio devices such as music players and microphones, camera devices, and test devices. By way of example only, communication systems intended to be included within the scope of the present disclosure include cellular wireless telephone communication systems, satellite communication systems, two-way radio communication systems, one-way pagers, two-way pagers, personal communication systems (PCS), personal digital assistants (PDA), and the like.

[0024] Figure 1 An example device 100 in which aspects of the present disclosure can be implemented is illustrated. Device 100 can be a battery-powered device, such as a cellular phone, PDA, handheld device, wireless device, laptop computer, tablet computer, smart phone, wearable device, etc.

[0025] Device 100 can include a processor 104 that controls the operation of device 100. Processor 104 can also be referred to as a central processing unit (CPU). A memory 106 that can include both a read-only memory (ROM) and a random access memory (RAM) provides instructions and data to processor 104. A portion of memory 106 can also include a non-volatile random access memory (NVRAM). Processor 104 generally performs logical and arithmetic operations based on program instructions stored within memory 106.

[0026] In some aspects, device 100 can also include a housing 108 that can include a transmitter 110 and a receiver 112 to allow for the transmission and reception of data between device 100 and a remote location. For some aspects, transmitter 110 and receiver 112 can be combined into a transceiver 114. One or more antennas 116 can be attached or otherwise coupled to housing 108 and electrically connected to transceiver 114. Device 100 can also include (not shown) multiple transmitters, multiple receivers, and / or multiple transceivers.

[0027] Device 100 may also include a signal detector 118, which may be used to detect and quantify the level of signals received by transceiver 114. The signal detector 118 may detect signal parameters such as total energy, energy per symbol per subcarrier, and power spectral density, among others. Device 100 may also include a digital signal processor (DSP) 120 for use in processing signals.

[0028] Device 100 may also include a battery 122, which is used to power the various components of device 100. Device 100 may also include a power management integrated circuit (power management IC or PMIC) 124 for managing power from the battery to the various components of device 100. The PMIC 124 may perform various functions for the device, such as direct current (DC) - to - DC conversion, battery charging, power selection, voltage scaling, power sequencing, etc. In some aspects, the PMIC 124 may include a battery charging circuit (e.g., a master - slave battery charging circuit) or other switched - mode power supplies. The various components of device 100 may be coupled together via a bus system 126, which may include a power bus, a control signal bus, and / or a status signal bus attached to a data bus.

[0029] For some aspects, device 100 may have an input / output (I / O) module 128 for receiving and / or outputting data and / or power. In some aspects, the I / O module 128 may include a connector 130, such as a Universal Serial Bus (USB) type - A (USB - A) socket or a USB type - C (USB - C) socket. The pins of the connector 130 may be routed via the bus system 126 and / or signal lines of the I / O module 128 to the processor 104 and / or the PMIC 124, and at least some of these components may include over - voltage protection circuitry, as further described herein.

[0030] Examples of Over - voltage Protection Circuits

[0031] DC over - voltage and surge voltage fault conditions may occur at one or more pins of a connector (such as a USB - A or USB - C socket) of a device (e.g., device 100). As Figure 2As illustrated in the block diagram 200, an overvoltage protection (OVP) scheme can be employed to prevent electrical overstress (EOS) damage to a chipset integrated circuit (IC) having various signal nodes for coupling to connector pins. For example, an OVP scheme 202 can be implemented between certain pins of the USB-C port 204 and pins of an audio encoder / decoder (codec) 206 that is used for analog headphone audio output (e.g., headphone left (HPL) pin 208 or headphone right (HPR) pin 210) or input (e.g., sense pin 212 or microphone (MIC) pin 214). As an additional example, in addition to the bus power (V BUS ) pin, a customer may also expect differential pair positive (DP) pins 216 (e.g., Dp1 or Dp2), differential pair negative (DN) pins 218 (e.g., Dn1 or Dn2), and / or sideband use (SBU) pins (e.g., SBU1 220 or SBU2222) to withstand high voltages (e.g., ±20V) caused by various fault conditions such as V BUS short circuits, which may reach 20V in some cases). In some cases, an OVP scheme 202 can be implemented between the DP and DN pins 216, 218 of the USB-C port 204 and pins of an application processor 224 (e.g., corresponding DP and DN pins 226, 228) that is used to run applications in an operating system. Due to the relatively high number of pins to be protected and signal integrity issues, it may be desirable to minimize or at least reduce the number of control pins and traces involved in implementing the OVP scheme.

[0032] One example OVP scheme uses a separate external IC to implement USB data / audio switching between a connector (e.g., a USB-C receptacle) and the chipset IC. This external IC also provides built-in OVP on certain signal lines. However, this external IC is an expensive solution in terms of cost and circuit board area.

[0033] Another example OVP scheme is for surge protection (e.g., transient surges), where a limited amount of charge can be dissipated to prevent high voltages at IC pins. However, when the circuit attempts to clamp a DC voltage with a low resistance, the circuit implementing such a surge protection scheme cannot protect the IC from high DC voltages due to very high power consumption.

[0034] Yet another OVP solution provides protection based on an external field effect transistor (FET), where the external FET is used as a switch between a connector port and a signal line. In this solution, a control circuit senses the voltage at the connector port and controls the FET switch based on the sensed voltage. This is a much cheaper solution compared to an external protection IC. However, for each connector pin designated for overvoltage protection, this solution requires the use of two pins (e.g., OVP drive and OVP sense) and corresponding traces ("wires"). As mentioned above, due to the relatively large number of pins for protecting USB-C and signal integrity issues, it may be desirable to minimize or at least reduce the number of control pins and traces involved in implementing the OVP solution.

[0035] Certain aspects of the present disclosure provide relatively inexpensive (in terms of cost and circuit board area) OVP techniques and devices that, compared to the example OVP solutions described above, provide suitable transient and DC overvoltage protection and provide fewer pin / trace counts. The OVP techniques and devices described herein can implement OVP for multiple pins of a connector at a desired cost and area.

[0036] Figure 3 is a circuit diagram of an example OVP circuit 300 in accordance with certain aspects of the present disclosure. Although Figure 3 illustrates an OVP circuit for a single connector port 302 (such as a DP pin 216), it should be understood that the OVP circuit can be replicated for other ports of the connector (such as a DN pin 218, an SBU1 220, and / or an SBU2 222). The connector port 302 can be a USB-C port, such as a DP pin 216, a DN pin 218, an SBU1 220, and / or an SBU2 222.

[0037] The OVP circuit 300 may include a switch 304 that is connected between a connector port 302 (e.g., a DP, DN, or SBU port having a voltage labeled "Vconn") and a signal node 306 (labeled "CDC" which refers to the connector DC voltage). The switch 304 corresponds to or is intended to carry signals to or from the connector port. In some aspects, the switch 304 may have a first terminal (e.g., a drain) for coupling to the connector port 302 and a second terminal (e.g., a source) for coupling to the signal node 306. The OVP circuit 300 may lack a sense line coupled to the node between the first terminal of the switch 304 and the connector port 302. In the absence of a sense line, the OVP circuit 300 can provide a desired number of traces and area, which in turn can provide a desired manufacturing cost. The switch 304 may be implemented by a transistor, such as an n-type metal oxide semiconductor field effect transistor (n-MOSFET or NMOS transistor) M1. The switch 304 may be closed during normal operation (such as when the voltage of the signal node is within the normal operating voltage) and opened during an overvoltage event, as further described herein with respect to Figure 4 In some aspects, the NMOS transistor M1 may have a suitable breakdown voltage for providing overvoltage protection, such as a breakdown voltage of at least 20V. A resistor 308 (having a resistance "R1") may be connected in parallel with the switch 304. The resistor 308 may have a suitable resistance to provide a voltage drop between the connector port 302 and the signal node 306 during an overvoltage event, as further described herein with respect to Figure 4 As an example, the resistor 308 may have a resistance of 20 kΩ.

[0038] The OVP circuit 300 may further include a transient voltage suppressor (TVS) 310, which may be implemented by a transient voltage suppression diode (e.g., a unidirectional TVS diode having a clamping voltage of 28V). The TVS 310 may be coupled in parallel between the node coupled to the connector port 302 (and coupled to the switch 304) and a reference potential node 312 (e.g., electrical ground). When Vconn exceeds the breakdown voltage of the TVS 310, the TVS 310 may divert the transient overvoltage to ground.

[0039] The OVP circuit 300 may further include a first transient protection circuit 314 that is coupled between the signal node 306 of the circuit and a reference potential node 312 (e.g., electrical ground). The first transient protection circuit 314 may be implemented, for example, by a snap-back clamp SBC1, as Figure 3As illustrated, or implemented by other voltage clamping structures (such as voltage clamping structures used for electrostatic discharge (ESD) protection). For example, the first transient protection circuit 314 can be implemented by one or more diodes coupled in series with a resistive element, or by one or more diodes coupled in series with a resistive-capacitive (RC) clamp. The first transient protection circuit 314 can provide additional protection against transient overvoltage. When the voltage at the signal node 306 exceeds the breakdown voltage of the snap-back clamp (e.g., the n-MOSFET of a parasitic bipolar junction transistor (BJT)), the first transient protection circuit 314 can pull down (or pull up, depending on the polarity of the overvoltage) the overvoltage to a specific holding voltage.

[0040] The OVP circuit 300 can also include a control circuit 316. The control circuit 316 can have an input 323 and an output 324, the input 323 being coupled to the signal node 306 and the output 324 being coupled to the control input (e.g., the gate) of the switch 304. The control circuit 316 can include a comparator 318 (labeled "A1"), and the comparator 318 is used to compare the signal node 306 with the reference voltage (labeled "Vref") at the reference voltage node 320. Vref can be programmable or configurable. For example, before OVP triggering, Vref may be equal to 3.3V, and may be changed to 30mV after triggering. In some aspects, Vref can be lower than the holding voltage of the first transient protection circuit. For some aspects, the control circuit 316 can also include an inverter 322 (labeled "I1"), and the inverter 322 is coupled between the output 324 of the comparator (with an output voltage labeled "Vcomp") and the control input of the switch 304 (e.g., the gate of the transistor M1, with a voltage labeled "Vg_ovp"). In some aspects, the output of the inverter 322 can be considered as the first output of the control circuit 316. Since the comparator 318 may have a delay in detecting the overvoltage, the first transient protection circuit 314 can pull down the overvoltage to the holding voltage until the comparator 318 detects the overvoltage on the signal node 306 and turns off the switch 304 (e.g., turns off the transistor M1), as further described herein Figure 4 as described further.

[0041] For some aspects, the control circuit 316 can have a single output, such as the output of the comparator 318. In this case, the transistor M1 can be implemented as a depletion-type FET, the gate of which is coupled to the output of the comparator 318, and the inverter 322 does not need to be used (i.e., can be replaced by a short circuit).

[0042] For some aspects, the OVP circuit 300 may further include a second transient protection circuit 328 coupled between the control input of the switch 304 and the reference potential node 312. As described above, the second transient protection circuit 328 may be implemented, for example, by a snap-back clamp SBC2 (as shown in Figure 3 ), or by one or more diodes coupled in series with a resistive element. The second transient protection circuit 328 may limit the voltage at the control input of the switch 304 such that any overvoltage does not leak to the signal node 306.

[0043] For some aspects, the OVP circuit 300 may further include a resistor 330 (having a resistance "R2") coupled in series with another switch 332 between the signal node 306 and the reference potential node 312. As illustrated, the another switch 332 may be implemented by an NMOS transistor M2. The control input of the another switch 332 (e.g., the gate of the transistor M2) may be coupled to the output 324 of the comparator 318. In some aspects, the output 324 of the comparator 318 may be considered as the second output of the control circuit 316 such that the second output of the control circuit 316 is coupled to the control input of the another switch 332. In some aspects, the second output of the control circuit 316 may be the same as the first output of the control circuit 316. In other aspects, the second output of the control circuit 316 may be coupled to the first output of the control circuit 316, for example, via an inverter 322. In some aspects, the resistor 330 may have a resistance R2 of approximately 300 Ω and / or may be adjustable. In some cases, the resistor 308 may have a first resistance R1 that is at least one order of magnitude greater than the second resistance R2 of the resistor 330.

[0044] For some aspects, the switch 304, resistor 308, and TVS 310 can all be external to the integrated circuit (IC), while other components of the OVP circuit 300 can be internal to the IC. For example, the signal node 306 can include a pin of the IC. The OVP circuit 300 can include only a single additional pin 326 of the IC for overvoltage protection of the connector port 302, where the single additional pin 326 is coupled between the output of the control circuit 316 and the control input of the switch 304. That is, the IC can have two pins for overvoltage protection of the connector port 302: one pin for the signal node 306 and another pin 326 for the control input of the switch 304. These two pins can provide the desired number of traces and area of the IC, which in turn can provide the desired manufacturing cost of the IC. In some aspects, the IC can be a system-on-chip (SoC), such as including an application processor 224, an audio codec 206, and internal components of the OVP circuit 300 (such as the first transient protection circuit 314, the control circuit 316, the second transient protection circuit 328, the resistor 330, and / or another switch 332).

[0045] In operation, the FET M1 is used to prevent high voltage (e.g., 20V). Figure 4 is illustrated in accordance with certain aspects of the present disclosure Figure 3Example timing diagram 400 of the CDC, Vcomp, Vg_ovp, and Vconn voltage waveforms of the OVP circuit 300 before, during, and after an overvoltage event. As shown, the various voltage waveforms (CDC, Vcomp, Vg_ovp, and Vconn) are depicted as voltages varying over time. During phase 1 (402) that begins shortly after t1, when Vconn experiences an overvoltage event (e.g., the voltage suddenly increases to 20V), the snap-back clamps SBC1 and SBC2 kick in and limit the transient voltages on Vg_ovp and the IC pin CDC to their respective holding voltages (e.g., <~4.7V). During phase 2 (404) between t1 and t2, the high-impedance resistor 308 together with the snap-back clamp SBC1 limits the CDC pin voltage to the SBC holding voltage. After a control circuit delay (e.g., ~200 ns due to the comparator 318 and the inverter 322), phase 3 (406) begins at t2. During phase 3 (406) from t2 to t3, Vg_ovp is pulled to ground (0V) by Vcomp that transitions to a logic high signal and the inverter 322 that inverts it to a logic low signal, such that the NMOS transistor M1 is turned off and the CDC pin is disconnected from the connector port 302 to protect the CDC pin from the overvoltage condition of Vconn. Also due to Vcomp transitioning to a logic high signal, the NMOS transistor M2 is turned on and pulls the CDC pin voltage to ground. As long as Vconn*R2 / (R1+R2) > Vref, the control circuit 316 maintains this state. After the overvoltage event stops at t3, phase 4 (408) begins. After a control circuit delay during phase 4, the control circuit turns off the transistor M2 and turns on the transistor M1, ending phase 4 at t4.

[0046] In some aspects, the OVP circuit can provide overvoltage protection for positive and / or negative voltages. For example, Figure 5 is a circuit diagram of another example OVP circuit 500 according to certain aspects of the present disclosure. The OVP circuit 500 can be used to support connector pins for both positive and negative signal voltages and transient surge conditions. The OVP circuit 500 can include a bidirectional voltage clamping circuit 510 (e.g., two unidirectional TVS diodes in reverse series, as illustrated). When the magnitude of Vconn exceeds the breakdown voltage of either of the TVS diodes in the TVS diodes, the bidirectional voltage clamping circuit 510 can shunt an instantaneous positive or negative overvoltage to ground.

[0047] The OVP circuit 500 can also include a control circuit 516 having a first comparator 518A, a second comparator 518B, and a logic OR gate 534, and the control circuit 516 can effectively replace Figure 3Comparator 318 in. The logical OR gate 534 may have an output 536, and the output 536 is coupled to the output of the control circuit 516. The first comparator 518A may have a first input 523A coupled to the signal node 306, a second input 520A (also referred to as the "first reference voltage node") configured to receive a first reference voltage (e.g., Vr+, which may be a positive voltage), and an output 524A coupled to the first input 538 of the logical OR gate. The second comparator 518B may have a first input 523B coupled to the signal node 306, a second input 520B (also referred to as the "second reference voltage node") configured to receive a second reference voltage (e.g., Vr-, which may be a negative voltage), and an output 524B coupled to the second input 540 of the logical OR gate 534. The first comparator 518A may detect a positive overvoltage relative to the first reference voltage (e.g., > Vr+) and turn off the switch 304, while the second comparator 518B may detect a negative overvoltage relative to the second reference voltage (e.g., < Vr-) and turn off the switch 304. In this way, the control circuit can detect whether the voltage amplitude at the signal node 306 is greater than or equal to the amplitude of the first reference voltage or the amplitude of the second reference voltage.

[0048] Although the examples depicted in Figure 3 and Figure 5 are described herein with respect to providing OVP for positive voltages or for positive and negative voltages, aspects of the present disclosure may also be applied to OVP circuits that only prevent negative overvoltages.

[0049] Figure 6 is a flowchart illustrating an example operation 600 for providing OVP for a signal node (e.g., signal node 306) corresponding to a connector port (e.g., connector port 302) in accordance with certain aspects of the present disclosure. The operation 600 may be performed, for example, by an OVP circuit (e.g., OVP circuit 300 or OVP circuit 500).

[0050] Operation 600 may begin at block 602, where, in response to a first voltage exceeding the clamping voltage of a first transient protection circuit, the first transient protection circuit (e.g., first transient protection circuit 314) may suppress the first voltage at a signal node (e.g., signal node 306) to a second voltage. The first transient protection circuit may be coupled between the signal node and a reference potential node (e.g., reference potential node 312). At block 604, a control circuit (e.g., control circuit 316) may compare the second voltage to a reference voltage (e.g., Vref). The control circuit may have an input (e.g., input 323) coupled to the signal node and a first output (e.g., output 324) coupled to a control input of a first switch (e.g., switch 304). The first switch may have a first terminal coupled to a connector port and a second terminal coupled to the signal node, and the first switch may be coupled in parallel with a first resistive element (e.g., resistor 308). At block 606, the control circuit may open the first switch based on the comparison. For example, the comparison may involve detecting that the magnitude of the second voltage is greater than or equal to the magnitude of the reference voltage.

[0051] At optional block 608, the control circuit may close the first switch based on another comparison between the second voltage and the reference voltage. In this case, the second voltage for the another comparison may be sensed through the first resistive element coupled in parallel with the first switch. In other words, the first resistive element may be used to monitor the connector port until the overvoltage condition disappears, such that the first switch may then be closed.

[0052] Regarding block 602, the first transient protection circuit may initiate suppression of the first voltage in response to the first voltage exceeding the magnitude of the clamping voltage of the first transient protection circuit. For a positive or negative voltage, the first voltage may be suppressed at block 602. In some aspects, the clamping voltage may be the breakdown voltage of a snap-back clamp. The first transient protection circuit may pull down (or pull up) the overvoltage to some holding voltage associated with the first transient protection circuit.

[0053] In some aspects, a second transient protection circuit (e.g., second transient protection circuit 328) may be used to suppress transient voltages from imposing electrical stress on the first switch. For example, operation 600 may further include: in response to a third voltage exceeding the clamping voltage of the second transient protection circuit, the second transient protection circuit suppressing the third voltage at a control input of the first switch to a fourth voltage. The second transient protection circuit may be coupled between the control input of the first switch and the reference potential node.

[0054] In some aspects, a second switch (e.g., another switch 332) can be used to further suppress the voltage at the signal node. For example, operation 600 can further include: the control circuit closing the second switch based on a comparison (e.g., detecting that the magnitude of the second voltage is greater than or equal to the magnitude of the reference voltage). The second switch can be coupled in series with a second resistive element (e.g., resistor 330) between the signal node and the reference potential node. The output of the control circuit can be coupled to the control input of the second switch.

[0055] In some aspects, a comparator (e.g., comparator 318) can be utilized to perform the comparison. For example, the comparison at block 604 can include: the comparator comparing the second voltage with the reference voltage. In this case, the comparator can have a first input coupled to the signal node, a second input receiving the reference voltage, and an output with a first output coupled to the control circuit.

[0056] In some aspects, the control voltage output by the comparator can be inverted using an inverter (e.g., inverter 322). For example, opening the first switch at block 606 can include: applying the inverted output of the comparator to the control input of the first switch.

[0057] In some aspects, the reference voltage of the comparator can be different from the holding voltage of the first transient protection circuit. For example, the magnitude of the holding voltage can be greater than the reference voltage so that the control circuit can trigger the opening of the first switch.

[0058] In some aspects, a TVS (e.g., TVS 310, which can be implemented by a TVS diode) can be used to further suppress the transient voltage. For example, suppressing the first voltage at block 602 can further include: suppressing the first voltage to a second voltage using a TVS diode coupled between the first terminal of the first switch and the reference potential node.

[0059] In some aspects, the first resistive element can be used to monitor the voltage at the connector pin until the overvoltage condition ends. The control circuit can close the first switch based on another comparison between the second voltage and a reference voltage. For example, the second voltage for the another comparison can be sensed by a first resistive element coupled in parallel with the first switch and / or by a second resistive element coupled in series with the second switch. Regarding operation 600, comparing the second voltage at block 604 can include: comparing the second voltage and the reference voltage based at least in part on a first voltage drop across the first resistive element coupled in parallel with the first switch and, in some cases, based on a second voltage drop across the second resistive element coupled in series with the second switch. The control circuit can compare whether Vconn*R2 / (R1+R2) is greater than the reference voltage (Vref). When Vconn*R2 / (R1+R2) is greater than the reference voltage, the control circuit can open the first switch, and when Vconn*R2 / (R1+R2) is less than or equal to the reference voltage, the control circuit can close the first switch.

[0060] In some aspects, the control circuit can close the first switch when the overvoltage event stops. As an example, the control circuit can close the first switch based on a comparison, such as detecting that the magnitude of the second voltage is less than the magnitude of the reference voltage.

[0061] Regarding block 608, for example, as described herein with respect to Figure 4 After stage 4, if the second voltage is below a certain threshold based on the reference voltage, the control circuit can close the first switch. For example, if Vconn*R2 / (R1+R2) is less than or equal to Vref, the control circuit can close the first switch and, in some cases, the control circuit can open the second switch.

[0062] Example aspects

[0063] In addition to the various aspects described above, specific combinations of aspects are also within the scope of the present disclosure, some of which are detailed below:

[0064] Aspect 1: A circuit for overvoltage protection (OVP) between a connector port and a signal node corresponding to the connector port, the OVP circuit comprising: a first switch having a first terminal for coupling to the connector port and a second terminal for coupling to the signal node; a first resistive element coupled in parallel with the first switch; a first transient protection circuit coupled between the signal node and a reference potential node; and a control circuit having an input coupled to the signal node and a first output coupled to a control input of the first switch.

[0065] Aspect 2: The OVP circuit according to Aspect 1 further includes a second transient protection circuit between the control input of the first switch and the reference potential node.

[0066] Aspect 3: The OVP circuit according to Aspect 2, wherein at least one of the first transient protection circuit and the second transient protection circuit includes a snap-back clamp.

[0067] Aspect 4: The OVP circuit according to Aspect 2, wherein at least one of the first transient protection circuit and the second transient protection circuit includes at least one diode serially coupled with a resistor-capacitor (RC) clamp.

[0068] Aspect 5: The OVP circuit according to any one of Aspects 1-4 further includes a second resistor element and a second switch serially coupled between the signal node and the reference potential node, wherein a second output of the control circuit is coupled to a control input of the second switch.

[0069] Aspect 6: The OVP circuit according to Aspect 5, wherein the first resistor element has a first resistance that is at least one order of magnitude greater than a second resistance of the second resistor element.

[0070] Aspect 7: The OVP circuit according to any one of Aspects 1-6, wherein the control circuit includes a comparator having a first input coupled to the signal node, a second input coupled to a reference voltage node, and an output coupled to an output of the control circuit.

[0071] Aspect 8: The OVP circuit according to Aspect 7, wherein the control circuit further includes an inverter having an input coupled to the output of the comparator and an output coupled to the first output of the control circuit.

[0072] Aspect 9: The OVP circuit according to Aspect 7 or 8 further includes a second resistor element and a second switch serially coupled between the signal node and the reference potential node, wherein the output of the comparator is coupled to a control input of the second switch.

[0073] Aspect 10: The OVP circuit according to any one of Aspects 7-9, wherein an amplitude of the reference voltage at the reference voltage node is lower than an amplitude of a holding voltage of the first transient protection circuit.

[0074] Aspect 11: The OVP circuit according to any one of Aspects 1-10, wherein the connector port is a USB-C port.

[0075] Aspect 12: The OVP circuit according to aspect 11, wherein the USB-C port is a differential pair positive (DP) port, a differential pair negative (DN) port, or a sideband use (SBU) port.

[0076] Aspect 13: The OVP circuit according to any one of aspects 1-12, wherein the OVP circuit lacks a sense line that is coupled to a node between the first terminal of the first switch and the connector port.

[0077] Aspect 14: The OVP circuit according to any one of aspects 1-13, wherein the first switch includes an n-type metal oxide semiconductor (NMOS) transistor having a drain as the first terminal of the first switch, a source as the second terminal of the first switch, and a gate as the control input of the first switch.

[0078] Aspect 15: The OVP circuit according to aspect 14, wherein the breakdown voltage of the NMOS transistor is at least 20V.

[0079] Aspect 16: The OVP circuit according to any one of aspects 1-15, wherein: the control circuit is part of an integrated circuit (IC); the first switch is external to the IC; the signal node includes a pin of the IC; the OVP circuit includes only a single additional pin of the IC for overvoltage protection of the connector port; and the single additional pin is coupled between the first output of the control circuit and the control input of the first switch.

[0080] Aspect 17: The OVP circuit according to aspect 16, wherein the first resistive element is external to the IC.

[0081] Aspect 18: The OVP circuit according to aspect 16 or 17, wherein the first transient protection circuit is internal to the IC.

[0082] Aspect 19: The OVP circuit according to any one of aspects 1-18, further comprising a transient voltage suppression (TVS) diode coupled between the first terminal of the first switch and the reference potential node.

[0083] Aspect 20: The OVP circuit according to any one of Aspects 1-6 or 10-19, wherein the control circuit includes: a logical OR gate having an output coupled to the first output of the control circuit; a first comparator having a first input coupled to the signal node, a second input configured to receive a first reference voltage, and an output coupled to the first input of the logical OR gate; and a second comparator having a first input coupled to the signal node, a second input configured to receive a second reference voltage, and an output coupled to the second input of the logical OR gate.

[0084] Aspect 21: The OVP circuit according to Aspect 5 or 6, wherein the second output of the control circuit is the same as the first output of the control circuit.

[0085] Aspect 22: The OVP circuit according to Aspect 5 or 6, wherein the second output of the control circuit is coupled to the first output of the control circuit.

[0086] Aspect 23: A method for providing overvoltage protection between a connector port and a signal node corresponding to the connector port, the method including: in response to a first voltage exceeding a clamping voltage of a first transient protection circuit, suppressing the first voltage at the signal node to a second voltage using the first transient protection circuit, wherein the first transient protection circuit is coupled between the signal node and a reference potential node; comparing the second voltage with a reference voltage using a control circuit having an input coupled to the signal node and a first output coupled to a control input of a first switch, wherein the first switch has a first terminal coupled to the connector port, a second terminal coupled to the signal node, and is coupled in parallel with a first resistive element; and disconnecting the first switch using the control circuit based on the comparison.

[0087] Aspect 24: The method according to Aspect 23, further including: suppressing a third voltage at the control input of the first switch to a fourth voltage using a second transient protection circuit coupled between the control input of the first switch and the reference potential node in response to the third voltage exceeding a clamping voltage of the second transient protection circuit.

[0088] Aspect 25: The method according to Aspect 23 or 24, further including closing a second switch using the control circuit based on the comparison, wherein the second switch is coupled in series with a second resistive element between the signal node and the reference potential node, and wherein a second output of the control circuit is coupled to a control input of the second switch.

[0089] Aspect 26: The method according to aspect 25, wherein closing the second switch includes: closing the second switch based on detecting that the magnitude of the second voltage is greater than or equal to the magnitude of the reference voltage in the comparison.

[0090] Aspect 27: The method according to any one of aspects 23-26, wherein the comparison includes: comparing the second voltage with the reference voltage using a comparator having a first input coupled to the signal node, a second input receiving the reference voltage, and an output coupled to the first output of the control circuit.

[0091] Aspect 28: The method according to aspect 27, wherein opening the first switch includes applying the inverted output of the comparator to the control input of the first switch.

[0092] Aspect 29: The method according to any one of aspects 23-28, wherein the reference voltage is different from the holding voltage of the first transient protection circuit.

[0093] Aspect 30: The method according to any one of aspects 23-29, wherein suppressing the first voltage includes: suppressing the first voltage to the second voltage using a transient voltage suppression (TVS) diode coupled between the first terminal of the first switch and the reference potential node.

[0094] Aspect 31: The method according to any one of aspects 23-30, further comprising: closing the first switch by the control circuit based on another comparison between the second voltage and the reference voltage, wherein the second voltage for the another comparison is sensed through the first resistive element coupled in parallel with the first switch.

[0095] Aspect 32: The method according to any one of aspects 23-31, wherein opening the first switch includes: opening the first switch based on a comparison detecting that the magnitude of the second voltage is greater than or equal to the magnitude of the reference voltage.

[0096] The various operations of the above method can be performed by any suitable device capable of performing the corresponding functions. The device may include various hardware and / or software components and / or modules, including but not limited to circuits, application specific integrated circuits (ASICs) or processors. Generally, in cases where there are operations illustrated in the drawings, these operations may have corresponding means-plus-function components with similar numbers.

[0097] As used herein, the term "determine" encompasses a variety of actions. For example, "determine" can include calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, database, or other data structure), ascertaining, and the like. Additionally, "determine" can include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), and the like. Further, "determine" can include resolving, selecting, choosing, establishing, and the like.

[0098] As used herein, a phrase referring to "at least one" in a list of items means any combination of those items, including a single member. For example, "at least one of a, b, or c" is intended to cover: a, b, c, a - b, a - c, b - c, and a - b - c, as well as any combination having multiple identical elements (e.g., a - a, a - a - a, a - a - b, a - a - c, a - b - b, a - c - c, b - b, b - b - b, b - b - c, c - c, and c - c - c or any other order of a, b, and c).

[0099] The methods disclosed herein include one or more steps or actions for implementing the methods. Without departing from the scope of the claims, the method steps and / or actions can be interchanged with one another. In other words, unless a specific order of steps or actions is specified, the order and / or use of specific steps and / or actions can be modified without departing from the scope of the claims.

[0100] It should be understood that the claims are not limited to the exact configurations and components described above. Various modifications, alterations, and variations can be made to the arrangements, operations, and details of the above - described methods and apparatuses without departing from the scope of the claims.

Claims

1. An overvoltage protection (OVP) circuit for between a connector port and a signal node corresponding to the connector port, the OVP circuit comprising: A first switch having a first terminal for coupling to the connector port and a second terminal for coupling to the signal node; A first resistive element coupled in parallel with the first switch; A first transient protection circuit coupled between the signal node and a reference potential node; And A control circuit having an input coupled to the signal node and a first output coupled to a control input of the first switch, Wherein: The control circuit is part of an integrated circuit (IC); The first switch is external to the IC; The signal node includes a pin of the IC; The OVP circuit includes only a single additional pin of the IC for the overvoltage protection of the connector port; and The single additional pin is coupled between the first output of the control circuit and the control input of the first switch.

2. The OVP circuit according to claim 1, further comprising a second transient protection circuit coupled between the control input of the first switch and the reference potential node.

3. The OVP circuit according to claim 2, wherein at least one of the first transient protection circuit or the second transient protection circuit includes a snapback clamp.

4. The OVP circuit according to claim 2, wherein at least one of the first transient protection circuit or the second transient protection circuit includes at least one diode coupled in series with a resistor-capacitor (RC) clamp.

5. The OVP circuit according to claim 1, further comprising a second resistive element and a second switch coupled in series between the signal node and the reference potential node, wherein a second output of the control circuit is coupled to a control input of the second switch.

6. The OVP circuit according to claim 5, wherein the first resistive element has a first resistance that is at least one order of magnitude greater than a second resistance of the second resistive element.

7. The OVP circuit according to claim 1, wherein the control circuit includes a comparator having a first input coupled to the signal node, a second input coupled to a reference voltage node, and an output coupled to the first output of the control circuit.

8. The OVP circuit according to claim 7, wherein the control circuit further includes an inverter having an input coupled to the output of the comparator and an output coupled to the first output of the control circuit.

9. The OVP circuit according to claim 8, further comprising a second resistive element and a second switch coupled in series between the signal node and the reference potential node, wherein the output of the comparator is coupled to the control input of the second switch.

10. The OVP circuit according to claim 7, wherein an amplitude of a reference voltage at the reference voltage node is lower than an amplitude of a holding voltage of the first transient protection circuit.

11. The OVP circuit according to claim 1, wherein the connector port is a USB-C port.

12. The OVP circuit according to claim 11, wherein the USB-C port is a differential pair positive DP port, a differential pair negative DN port, or a sideband use SBU port.

13. The OVP circuit according to claim 1, wherein the OVP circuit lacks a sense line coupled to a node between the first terminal of the first switch and the connector port.

14. The OVP circuit according to claim 1, wherein the first switch includes an n-type metal oxide semiconductor NMOS transistor, the NMOS transistor having a drain as the first terminal of the first switch, a source as the second terminal of the first switch, and a gate as the control input of the first switch.

15. The OVP circuit according to claim 14, wherein the breakdown voltage of the NMOS transistor is at least 20V.

16. The OVP circuit according to claim 1, wherein the first resistive element is external to the IC.

17. The OVP circuit according to claim 1, wherein the first transient protection circuit is internal to the IC.

18. The OVP circuit according to claim 1, further comprising a transient voltage suppression TVS diode coupled between the first terminal of the first switch and the reference potential node.

19. The OVP circuit according to claim 1, wherein the control circuit includes: a logic OR gate, the output of the logic OR gate being coupled to the first output of the control circuit; a first comparator having a first input coupled to the signal node, a second input coupled to a first reference voltage node, and an output coupled to the first input of the logic OR gate; and a second comparator having a first input coupled to the signal node, a second input coupled to a second reference voltage node, and an output coupled to the second input of the logic OR gate.

20. A method for providing overvoltage protection between a connector port and a signal node corresponding to the connector port, the method comprising: in response to a first voltage exceeding a clamping voltage of a first transient protection circuit, suppressing the first voltage at the signal node to a second voltage by using the first transient protection circuit, wherein the first transient protection circuit is coupled between the signal node and a reference potential node; comparing the second voltage with a reference voltage by using a control circuit having an input coupled to the signal node and a first output coupled to a control input of a first switch, wherein the first switch has a first terminal coupled to the connector port, a second terminal coupled to the signal node, and is coupled in parallel with a first resistive element; and based on the comparison, opening the first switch by using the control circuit, wherein: the control circuit is part of an integrated circuit IC; the first switch is external to the IC; The signal node includes a pin of the IC; The method of providing overvoltage protection uses only a single additional pin of the IC for overvoltage protection of the connector port; and The single additional pin is coupled between the first output of the control circuit and the control input of the first switch.

21. The method according to claim 20, further comprising: Using a second transient protection circuit coupled between the control input of the first switch and the reference potential node, in response to a third voltage exceeding the clamping voltage of the second transient protection circuit, suppressing the third voltage at the control input of the first switch to a fourth voltage.

22. The method according to claim 20, further comprising closing a second switch using the control circuit based on the comparison, wherein the second switch is serially coupled with a second resistive element between the signal node and the reference potential node, and wherein a second output of the control circuit is coupled to the control input of the second switch.

23. The method according to claim 22, wherein closing the second switch comprises: Closing the second switch based on detecting that the magnitude of the second voltage is greater than or equal to the magnitude of the reference voltage.

24. The method according to claim 20, wherein said comparison comprises: Comparing the second voltage with the reference voltage using a comparator having a first input coupled to the signal node, a second input receiving the reference voltage, and an output coupled to the first output of the control circuit.

25. The method according to claim 24, wherein opening the first switch includes applying the inverted output of the comparator to the control input of the first switch.

26. The method according to claim 20, wherein the reference voltage is different from the holding voltage of the first transient protection circuit.

27. The method according to claim 20, wherein suppressing the first voltage comprises: Suppressing the first voltage to the second voltage using a transient voltage suppression TVS diode coupled between the first terminal of the first switch and the reference potential node.

28. The method according to claim 20 further comprises: Closing the first switch using the control circuit based on another comparison between the second voltage and the reference voltage, wherein the second voltage for the another comparison is sensed through the first resistive element coupled in parallel with the first switch.

29. The method according to claim 20, wherein opening the first switch comprises: Opening the first switch based on a comparison detecting that the magnitude of the second voltage is greater than or equal to the magnitude of the reference voltage.

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