Electronic device, method of accessing joint test action group interface, and storage medium

Abstract

The application discloses an electronic device, a JTAG interface access method and a storage medium, and belongs to the technical field of communication. The electronic device comprises an SPI interface, a GPIO interface and a processor. The SPI interface comprises an SCK pin, an MISO pin and an MOSI pin. The GPIO interface comprises a first GPIO pin. A target JTAG interface comprises a TCK pin, a TDI pin, a TDO pin and a TMS pin. The processor controls the SCK pin to send a TCK signal to the TCK pin, controls the MISO pin to receive a TDO signal output from the TDO pin, and controls the MOSI pin and the first GPIO pin to output a TMS signal to the TMS pin and output a TDI signal to the TDI pin. The electronic device can simulate the JTAG interface by using the SPI interface and the GPIO interface, and access the target JTAG interface.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication, in particular to an electronic device, a JTAG interface access method and a storage medium. BACKGROUND

[0002] The JTAG protocol is an international standard test protocol, mainly used for chip testing.

[0003] The JTAG interface based on the JTAG protocol is divided into a master JTAG interface and a slave JTAG interface, and only the master JTAG interface can initiate access to the slave JTAG interface. For some electronic devices without a master JTAG interface, a general purpose input / output (GPIO) interface is used to simulate a master JTAG interface to realize access to the slave JTAG interface. The GPIO interface used to simulate the master JTAG interface includes four GPIO pins, and the four GPIO pins respectively perform signal transmission with a test clock (TCK) pin, a test data input (TDI) pin, a test data output (TDO) pin and a test mode selection (TMS) pin of the slave JTAG interface.

[0004] Since four GPIO pins are needed to realize access to the slave JTAG interface, and the number of GPIO pins of many electronic devices is insufficient, the application of this mode is limited. SUMMARY

[0005] The present application provides an electronic device, a JTAG interface access method and a storage medium, which can realize access to a target JTAG interface based on a serial peripheral interface (SPI) and a GPIO interface, and the number of required GPIO pins is less.

[0006] In a first aspect, an electronic device is provided. The electronic device is configured to access a target JTAG interface. The target JTAG interface includes a TCK pin, a TDI pin, a TDO pin and a TMS pin. The electronic device includes an SPI interface, a GPIO interface and a processor. The SPI interface includes a serial clock (SCK) pin, a Master Input Slave Output (MISO) pin and a Master Output Slave Input (MOSI) pin. The GPIO interface includes a first GPIO pin. The processor is connected to the SPI interface and the GPIO interface respectively. The processor is configured to control the SCK pin to send a TCK signal to the TCK pin, control the MISO pin to receive a TDO signal output from the TDO pin, and control the MOSI pin and the first GPIO pin to output a TMS signal to the TMS pin and a TDI signal to the TDI pin.

[0007] In the present application, the SPI interface and the GPIO interface are used to simulate the JTAG interface, and the access to the target JTAG interface is realized. Since the three pins of the SPI interface are used to simulate the pins of the JTAG interface in the present application, the remaining required pins are simulated by the GPIO pins, and compared with the case where all the pins of the JTAG interface are simulated by the GPIO pins, the number of GPIO pins required for simulating the JTAG interface is smaller, which is conducive to the popularization and application of the present application.

[0008] In the present application, the processor is configured to control the MOSI pin to send at least a part of the TDI signal, and the at least a part of the TDI signal carries other data except the last 1 bit of the test data, so that most of the test data is sent through the MOSI pin. Since the data transmission rate supported by the SPI interface is higher than that supported by the GPIO interface, compared with sending the test data by the GPIO pin, sending the test data by the MISO pin can improve the data transmission efficiency, and further improve the efficiency of chip testing.

[0009] In a possible implementation, the processor is configured to: control the MOSI pin to send a first part of the TDI signal to the TDI pin in a first time period; control the MOSI pin to send a first part of the TMS signal to the TMS pin in a second time period, and control the first GPIO pin to send a second part of the TDI signal to the TDI pin in the second time period; wherein the second time period is after the first time period and continuous with the first time period. In this application, the first part of the TDI signal carries data except the last 1 bit of the test data, and the second part of the TDI signal carries the last 1 bit of the test data. The first part of the TMS signal carries the first bit of the mode selection data.

[0010] Since the JTAG standard requires that the second part of the TDI signal (for example, the last 1 bit of the TDI signal) and the first part of the TMS signal (that is, the first bit of the TMS signal) are effective at the same time, the second part of the TDI signal and the first part of the TMS signal need to be sent at the same time. In this application, by controlling the MOSI pin to send the first part of the TMS signal to the TMS pin and controlling the first GPIO pin to send the second part of the TDI signal to the TDI pin in the second time period, the requirement of the JTAG standard can be met.

[0011] In this application, the processor is further configured to: control the MOSI pin to send a second part of the TMS signal to the TMS pin in a third time period. That is, the TMS signal is sent to the TMS pin through the MOSI pin. Wherein the third time period is after the second time period and continuous with the second time period.

[0012] In some examples, the first GPIO pin is connected with the TDI pin. The GPIO interface further includes a second GPIO pin. The electronic device further includes an interface control circuit, the interface control circuit includes a first multiplexer, the first multiplexer has one input end, one control end and two output ends, the input end of the first multiplexer is connected with the MOSI pin, the control end of the first multiplexer is connected with the second GPIO pin, one output end of the first multiplexer is connected with the TMS pin, and the other output end of the first multiplexer is connected with the TDI pin.

[0013] The first multiplexer is configured to, under the action of a first level output by the second GPIO pin, connect the MOSI pin and the TMS pin to each other to transmit the TMS signal from the MOSI pin to the TMS pin, or, under the action of a second level output by the second GPIO pin, connect the MOSI pin and the TDI pin to each other to transmit the first part of the TDI signal from the MOSI pin to the TDI pin.

[0014] The processor is further configured to control the second GPIO pin to output the second level in the first time period, and control the second GPIO pin to output the first level in the second time period.

[0015] In this example, one first multiplexer and one second GPIO pin are used to control the MOSI pin to transmit signals to the TDI pin in the first time period and control the MOSI pin to transmit signals to the TMS pin in the second time period, and the circuit structure is simple and easy to implement.

[0016] Optionally, the interface control circuit further comprises a first pull-down resistor and a second pull-down resistor, one end of the first pull-down resistor is connected with one output end of the first multiplexer, the other end of the first pull-down resistor is grounded, one end of the second pull-down resistor is connected with the other output end of the first multiplexer, and the other end of the second pull-down resistor is grounded.

[0017] Through the first pull-down resistor and the second pull-down resistor, it can be ensured that the pin connected to the channel that is closed after the channel switching in the first multiplexer maintains a low level, avoiding noise interference.

[0018] In other examples, the GPIO interface further comprises a third GPIO pin and a fourth GPIO pin. The electronic device further comprises an interface control circuit, and the interface control circuit comprises a second multiplexer and a third multiplexer.

[0019] The second multiplexer has an input end, a control end and two output ends, the input end of the second multiplexer is connected with the MOSI pin, the control end of the second multiplexer is connected with the third GPIO pin, and one output end of the second multiplexer is connected with the TMS pin. The second multiplexer is configured to, under the action of the first level output by the third GPIO pin, connect the MOSI pin with the TMS pin to send a TMS signal to the TMS pin through the MOSI pin, or, under the action of the second level output by the third GPIO pin, connect the MOSI pin with the input end of the third multiplexer to send a first part of a TDI signal to the third multiplexer through the MOSI pin.

[0020] The third multiplexer has two input ends, a control end and an output end, one input end of the third multiplexer is connected with the other output end of the second multiplexer, the other input end of the third multiplexer is connected with the first GPIO pin, the control end of the third multiplexer is connected with the fourth GPIO pin, and the output end of the third multiplexer is connected with the TDI pin. The third multiplexer is configured to, when the fourth GPIO pin outputs a third level, connect the first GPIO pin with the TDI pin to send a second part of the TDI signal to the TDI pin through the first GPIO pin, or, when the fourth GPIO pin outputs a fourth level, connect the other output end of the second multiplexer with the TDI pin to send the first part of the TDI signal output by the other output end of the second multiplexer to the TDI pin.

[0021] The processor is further configured to control the third GPIO pin to output the second level and control the fourth GPIO pin to output the fourth level in the first time period, and control the third GPIO pin to output the first level and control the fourth GPIO pin to output the third level in the second time period.

[0022] In some examples, the third GPIO pin and the fourth GPIO pin are the same pin. In the case that the third GPIO pin and the fourth GPIO pin are the same pin, the second multiplexer and the third multiplexer can be controlled synchronously. Moreover, the third GPIO pin and the fourth GPIO pin sharing the same pin can reduce the number of GPIO pins required and simplify the circuit structure.

[0023] In other examples, the third GPIO pin and the fourth GPIO pin are two different pins.

[0024] In the example, two multiplexers and one or two GPIO pins are adopted to control the MOSI pin to send signals to the TDI pin in a first time period and to send signals to the TMS pin in a second time period, so that the circuit structure is simple and the implementation is convenient.

[0025] Optionally, the interface control circuit further comprises a third pull-down resistor, one end of the third pull-down resistor is connected with an input end of the second multiplexer connected with the TMS pin, and the other end of the third pull-down resistor is grounded.

[0026] When the channel of the third multiplexer connected with the first GPIO pin and the TDI pin is closed, the channel of the second multiplexer connected with the MOSI pin and the input end of the third multiplexer is also closed, so that the level of the TDI pin can be maintained as low, and thus it is not necessary to connect a pull-down resistor at the TDI pin. The third pull-down resistor connected with the TMS pin can maintain the low level of the TMS pin when the channel of the second multiplexer connected with the MOSI pin and the TMS pin is closed, so that noise interference is avoided.

[0027] In another possible implementation, the processor is configured to control the MOSI pin to send a first part of the TDI signal to the TDI pin in a first time period; control the MOSI pin to send a second part of the TDI signal to the TDI pin in a second time period; and control the first GPIO pin to send a first part of the TMS signal to the TMS pin in the second time period. The second time period is after and continuous with the first time period.

[0028] In the implementation, the TDI signal is always sent through the MOSI pin, so that switching of the pin corresponding to the TDI signal is avoided, and the control logic of the processor is facilitated to be simplified.

[0029] Optionally, the GPIO interface further comprises a fifth GPIO pin and a sixth GPIO pin. The electronic device further comprises an interface control circuit, and the interface control circuit comprises a fourth multiplexer. The fourth multiplexer has two input ends, a control end and an output end, one input end of the fourth multiplexer is connected with the SCK pin, the other input end of the fourth multiplexer is connected with the fifth GPIO pin, the control end of the fourth multiplexer is connected with the sixth GPIO pin, and the output end of the fourth multiplexer is connected with the TCK pin.

[0030] The fourth multiplexer is configured to, under the action of a fifth level output by the sixth GPIO pin, turn on the SCK pin and the TCK pin to transmit the SCK signal output by the SCK pin to the TCK pin as the TCK signal, or, under the action of a sixth level output by the sixth GPIO pin, transmit the clock signal output by the fifth GPIO pin to the TCK pin as the TCK signal.

[0031] The processor is further configured to control the sixth GPIO pin to output the fifth level in the first time period, and control the SCK pin to send the SCK signal to the TCK pin; and control the sixth GPIO pin to output the sixth level in the second time period, and control the fifth GPIO pin to send the clock signal to the TCK pin.

[0032] By controlling the fourth multiplexer, when the MOSI pin transmits the TDI signal, the SCK pin can provide a higher-frequency SCK signal as a clock signal to the TCK pin, so that the transmission efficiency of test data is higher. When the first GPIO pin transmits the TMS signal, the fifth GPIO pin provides a lower-frequency clock signal to the TCK pin, so that the frequencies of the TMS signal and the TCK signal remain consistent.

[0033] Optionally, the target JTAG interface further includes a test reset (TRST), and the GPIO interface further includes a seventh GPIO pin, and the processor is further configured to control the seventh GPIO pin to send a TRST signal to the TRST pin.

[0034] The SPI interface has a requirement on the unit length of data transmission when transmitting data through the MOSI pin. In some examples, the unit length of data transmission supported by the SPI interface is fixed. The JTAG interface has no requirement on the length of data transmission, but the JTAG protocol requires that the second part of the TDI signal and the first part of the TMS signal are effective at the same time. In order to meet both requirements at the same time, the processor needs to first determine whether the total length of the test data satisfies that the total length minus X is an integer multiple of Y, and then generate the TDI signal according to the determination result. If the processor determines that the total length of the test data minus X is an integer multiple of Y, the first part of the TDI signal is generated according to the data in the test data except for the last X bits, and the second part of the TDI signal is generated according to the last X bits of the test data. If the processor determines that the total length of the test data minus X is not an integer multiple of Y, 0 needs to be padded to the high bits of the test data until the total length of the test data after padding 0 minus X is not an integer multiple of Y, the first part of the TDI signal is generated according to the data in the test data after padding 0 except for the last X bits, and the second part of the TDI signal is generated according to the last X bits of the test data after padding 0. Wherein, X is the data length corresponding to the second part of the TDI signal and the first part of the TMS signal required by the JTAG protocol, Y is the unit length of data transmission supported by the SPI interface, and X and Y are integers.

[0035] In some examples, X is equal to 1, and Y is equal to 8 or 16.

[0036] In other examples, the unit length of data transmission supported by the SPI interface can be adjusted within a set range. The processor is further configured to divide the data in the test data except for the last X bits into N data sets, generate the first part of the TDI signal according to the data in the N data sets, and generate the second part of the TDI signal according to the last X bits of data. Wherein, N is an integer greater than 1, and N is not greater than the number of unit lengths of data transmission supported by the SPI interface. Each data set in the N data sets includes at least one data, the length of the data in any data set in the N data sets is the same, the length of the data in different data sets in the N data sets is different, and the length of the data in each data set is within a set range, i.e. the length of the data in each data set is one of the unit lengths of data transmission supported by the SPI interface.

[0037] For example, the set range is 4 bits to 8 bits. There are 5 unit lengths of data transmission supported by the SPI interface, so the number of unit lengths of data transmission supported by the SPI interface is 5.

[0038] Some electronic devices support sending data of variable length through an SPI interface, by grouping test data according to the length of the test data to obtain N data sets, and the length of data in each data set is the length supported by the SPI interface, so that the processor can realize switching of the data length by internal adjustment, and then generate a corresponding TDI signal according to the length of the data in each data set, without padding 0 to the test data.

[0039] Optionally, the processor is further configured to pad mode selection data according to a unit length of data transmission supported by the SPI interface to obtain padded mode selection data, and generate the TMS signal according to the padded mode selection data.

[0040] Optionally, the processor is configured to pad the mode selection data according to at least one of the following: padding 0 to high bits of first mode selection data according to the unit length, the first mode selection data being used to control a test access port (TAP) controller to switch from an idle state to a selected data register scan state or a selected instruction register scan state; and padding 0 to low bits of second mode selection data according to the unit length, the second mode selection data being used to control the TAP controller to switch from an update data register state or an update instruction register state to the idle state.

[0041] In a second aspect, a JTAG interface access method is provided, which is used to access a target JTAG interface. The target JTAG interface includes a TCK pin, a TDI pin, a TDO pin and a TMS pin. The method is applied to an electronic device, which includes an SPI interface, a GPIO interface and a processor. The SPI interface includes an SCK pin, a MISO pin and a MOSI pin. The GPIO interface includes a first GPIO pin. The method includes: controlling the SCK pin to send a TCK signal to the TCK pin; controlling the MISO pin to receive a TDO signal output from the TDO pin; and controlling the MOSI pin and the first GPIO pin to send a TMS signal to the TMS pin and a TDI signal to the TDI pin.

[0042] In a possible implementation, the controlling the MOSI pin and the first GPIO pin to send a TMS signal to the TMS pin and to send a TDI signal to the TDI pin comprises: controlling the MOSI pin to send a first part of the TDI signal to the TDI pin in a first time period; controlling the MOSI pin to send a first part of the TMS signal to the TMS pin in a second time period; and controlling the first GPIO pin to send a second part of the TDI signal to the TDI pin in the second time period, where the second time period is after and continuous with the first time period.

[0043] In another possible implementation, the controlling the MOSI pin and the first GPIO pin to send a TMS signal to the TMS pin and to send a TDI signal to the TDI pin comprises: controlling the MOSI pin to send a first part of the TDI signal to the TDI pin in a first time period; controlling the MOSI pin to send a second part of the TDI signal to the TDI pin in a second time period; and controlling the first GPIO pin to send a first part of the TMS signal to the TMS pin in the second time period; where the second time period is after and continuous with the first time period.

[0044] Optionally, the controlling the SCK pin to send a TCK signal to the TCK pin comprises: in the first time period, controlling the SCK pin to send the TCK signal to the TCK pin. The method further comprises: in the second time period, controlling a second GPIO pin to send the TCK signal to the TCK pin.

[0045] Optionally, before the controlling the MOSI pin and the first GPIO pin to send a TMS signal to the TMS pin and to send a TDI signal to the TDI pin, the method further comprises: in response to determining that a total length of test data minus X is equal to an integer multiple of Y, generating the first part of the TDI signal according to data in the test data except for last X bits, and generating the second part of the TDI signal according to the last X bits in the test data, where Y is a unit length of data transmission supported by the SPI interface; or in response to determining that the total length of test data minus X is not equal to an integer multiple of Y, padding 0 to high bits of the test data until a total length of the test data after padding 0 minus X is equal to an integer multiple of Y, generating the first part of the TDI signal according to data in the test data after padding 0 except for last X bits, and generating the second part of the TDI signal according to the last X bits in the test data after padding 0, where Y is a unit length of data transmission supported by the SPI interface.

[0046] Optionally, before the MOSI pin and the first GPIO pin are controlled to send the TMS signal to the TMS pin and the TDI signal to the TDI pin, the method further comprises: dividing data in the test data except for the last X bits into N data sets, N being an integer greater than 1 and N not greater than a number of unit lengths of data transmission supported by the SPI interface, each of the N data sets including at least one data, the data in any data set of the N data sets being of the same length, the data in different data sets of the N data sets being of different lengths, the length of the data in the any data set being one of the unit lengths of data transmission supported by the SPI interface; generating a first part of the TDI signal according to the data in the N data sets, and generating a second part of the TDI signal according to the last X bits of data.

[0047] Optionally, before the MOSI pin and the first GPIO pin are controlled to send the TMS signal to the TMS pin and the TDI signal to the TDI pin, the method further comprises: performing a padding operation on mode selection data according to a unit length of data transmission supported by the SPI interface to obtain padded mode selection data; and generating the TMS signal according to the padded mode selection data.

[0048] Optionally, the padding operation on the TMS data according to the state of the test access port (TAP) controller comprises at least one of: padding 0 at a high bit of first mode selection data according to the unit length, the first mode selection data being used to control the test access port (TAP) controller to transition from an idle state to a selected data register scan state or a selected instruction register scan state; and padding 0 at a low bit of second mode selection data according to the unit length, the second mode selection data being used to control the TAP controller to transition from an updated data register state or an updated instruction register state to the idle state.

[0049] In a third aspect, a computer-readable storage medium is provided, and the computer-readable storage medium stores computer instructions. When the computer instructions in the computer-readable storage medium are executed by a computer device, the computer device performs the method in the second aspect and possible implementation manners thereof.

[0050] In a fourth aspect, a computer program product containing instructions, which, when run on a computer device, causes the computer device to perform the method in the second aspect and possible implementation manners thereof. BRIEF DESCRIPTION OF DRAWINGS

[0051] Figure 1is a network architecture diagram of an application scenario provided by an example embodiment of the present application;

[0052] Figure 2 is a structural diagram of an electronic device provided by an example embodiment of the present application;

[0053] Figure 3 is a structural diagram of another electronic device provided by an example embodiment of the present application;

[0054] Figure 4 is a structural diagram of another electronic device provided by an example embodiment of the present application;

[0055] Figure 5 is a structural diagram of another electronic device provided by an example embodiment of the present application;

[0056] Figure 6 is a structural diagram of another electronic device provided by an example embodiment of the present application;

[0057] Figure 7 is a flow chart of an access method of a JTAG interface provided by an example embodiment of the present application;

[0058] Figure 8 is a sending process diagram of a TDI signal and a TMS signal provided by an example embodiment of the present application;

[0059] Figure 9 is a sending process diagram of another TDI signal and TMS signal provided by an example embodiment of the present application;

[0060] Figure 10 is a state change diagram of a TAP controller;

[0061] Figure 11 is a timing diagram of an instruction for controlling data register shift provided by an example embodiment of the present application;

[0062] Figure 12 is a timing diagram of an instruction for controlling instruction register shift provided by an example embodiment of the present application;

[0063] Figure 13 is a structural diagram of an access device of a JTAG interface provided by an example embodiment of the present application. DETAILED DESCRIPTION

[0064] In order to make the purpose, technical solutions and advantages of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the drawings.

[0065] Figure 1This is a schematic diagram of the network architecture of an application scenario provided by an exemplary embodiment of the present application. Figure 1 As shown, the first electronic device 11 includes a first JTAG interface 11a, and the second electronic device 12 includes a second JTAG interface 12a. The first JTAG interface 11a is connected to the second JTAG interface 12a. The first electronic device 11 accesses the second JTAG interface 12a of the second electronic device 12 through the first JTAG interface 11a to implement testing of the second electronic device 12.

[0066] The first JTAG interface that initiates the access is the master JTAG interface, and the second JTAG interface that is accessed is the slave JTAG interface.

[0067] Exemplarily, the first electronic device 11 and the second electronic device 12 are both selected from the following electronic devices: a central processing unit (CPU), a microcontroller unit (MCU) (also known as a single-chip microcomputer), a digital signal processor (DSP), a field programmable gate array (FPGA), etc. In some examples, the first electronic device 11 and the second electronic device 12 are of the same type. In other examples, the first electronic device 11 and the second electronic device 12 are of different types.

[0068] In the embodiment of the present application, the JTAG interface includes at least a TCK pin, a TMS pin, a TDI pin, and a TDO pin.

[0069] Optionally, in addition to the TCK, TMS, TDI, and TDO pins, the JTAG interface may also include a TRST pin. This pin is used to receive a TRST signal to reset (also known as initialize) the TAP controller. Because the TMS signal can also be used to reset the TAP controller, the TRST pin is optional.

[0070] For some electronic devices that do not have a JTAG interface but need to access the target JTAG interface, it is necessary to simulate the JTAG interface through other interfaces to access the target JTAG interface. In the embodiment of the present application, the electronic device simulates the JTAG interface through the SPI interface and the GPIO interface to access the target JTAG interface. Since most electronic devices have an SPI interface and a GPIO interface, the application value of the embodiment of the present application is relatively high.

[0071] The SPI interface includes an SCK pin, an MISO pin, an MOSI pin, and a slave select (SS) pin.

[0072] The SCK pin, the MISO pin, and the MOSI pin of the SPI interface are mainly used as pins of the analog JTAG interface in the embodiment of the present application. The SCK pin is used to send a clock signal, which is generated by an electronic device to which the SPI belongs. Different electronic devices support different clock frequencies. The MOSI pin is used to output data of a master device to a slave device, that is, the transmission direction of data on the pin is from the master device to the slave device. The MISO pin is used to receive data sent by the slave device to the master device, that is, the master device reads data from the signal line, and the data of the slave device is output from the signal line, that is, the transmission direction of data on the MISO pin is from the slave device to the master device.

[0073] Exemplarily, the electronic device provided by the embodiment of the present application includes but is not limited to a CPU, an MCU, a DSP, an FPGA, and the like.

[0074] Figure 2 is a structural schematic diagram of an electronic device provided by an exemplary embodiment of the present application. The electronic device is used to access a target JTAG interface. As shown in Figure 2 The electronic device 200 includes an SPI interface 210, a GPIO interface 220, and a processor 230. The SPI interface 210 includes an SCK pin 211, an MISO pin 212, and an MOSI pin 213. The GPIO interface 220 includes a first GPIO pin 221. The processor 230 is configured to control the SCK pin 211 to send a TCK signal to a TCK pin, control the MISO pin 212 to receive a TDO signal output from a TDO pin, and control the MOSI pin 213 and the first GPIO pin 221 to output a TMS signal to a TMS pin and send a TDI signal to a TDI pin.

[0075] In the embodiment of the present application, the JTAG interface is simulated by using part of the pins of the SPI interface and at least part of the pins of the GPIO interface, so that the access to the target JTAG interface is realized. Compared with the case where all the pins of the JTAG interface are simulated by using GPIO pins, since three pins of the SPI interface are used to simulate the pins of the JTAG interface in the embodiment of the present application, and the remaining required pins are simulated by using GPIO pins, the number of required GPIO pins is small, which is conducive to the popularization and application of the embodiment of the present application.

[0076] In the embodiment of the present application, the processor 230 is configured to control the MOSI pin to send at least part of the TDI signal, which carries other data except for the last 1 bit of test data, for example, so that most of the test data is sent through the MOSI pin. Since the data transmission rate supported by the SPI interface is higher than that of the GPIO interface, compared with sending test data by using the GPIO pin, the embodiment of the present application can improve the data transmission efficiency, and thus improve the efficiency of chip testing.

[0077] In some examples, the processor is configured to: control the MOSI pin to send a first part of the TDI signal to the TDI pin in a first time period; control the MOSI pin to send the TMS signal to the TMS pin in a second time period, and control the first GPIO pin to send a second part of the TDI signal to the TDI pin in the second time period; wherein the second time period is after and continuous with the first time period.

[0078] In this example, the processor is further configured to: control the MOSI pin to send a second part of the TMS signal to the TMS pin in a third time period. That is, the TMS signal is sent to the TMS pin through the MOSI pin. Wherein the third time period is after and continuous with the second time period.

[0079] The above will be described in detail below. Figure 3 and Figure 4 The above will be described in detail below.

[0080] Figure 3 is a structural schematic diagram of an electronic device provided by an example embodiment of the present application. As shown in Figure 3 , the electronic device includes an SPI interface 310, a GPIO interface 320, a processor 330 and an interface control circuit 340. Wherein, the SPI interface 310 includes an SCK pin 311, an MISO pin 312 and a MOSI pin 313. The GPIO interface 320 includes a first GPIO pin 321 and a second GPIO pin 322.

[0081] The interface control circuit 340 includes a first multiplexer 341, which has an input end, a control end and two output ends. The input end of the first multiplexer 341 is connected with the MOSI pin, the control end of the first multiplexer 341 is connected with the second GPIO pin 322, one output end of the first multiplexer 341 is connected with the TMS pin of the target JTAG interface, and the other output end of the first multiplexer 341 is connected with the TDI pin of the target JTAG interface. The first GPIO pin 321 is connected with the TDI pin.

[0082] The first multiplexer 341 is configured to, under the action of the first level output by the second GPIO pin 322, connect the MOSI pin 313 with the TMS pin to transmit the first part of the TMS signal from the MOSI pin 313 to the TMS pin, or, under the action of the second level output by the second GPIO pin 322, connect the MOSI pin 313 with the TDI pin to transmit the first part of the TDI signal from the MOSI pin 313 to the TDI pin.

[0083] The first level and the second level are one of high level and low level, respectively. For example, the first level is high level, and the second level is low level. For another example, the first level is low level, and the second level is high level. The embodiments of the present application do not limit the level values of the first level and the second level, as long as the first multiplexer can be controlled to switch the channel.

[0084] The processor 330 is further configured to control the second GPIO pin to output the second level in the first time period, and control the second GPIO pin to output the first level in the second time period.

[0085] The first multiplexer and the second GPIO pin can be used to control the MOSI pin to output signals to the TDI pin in the first time period, and control the MOSI pin to output signals to the TMS pin in the second time period, so that the circuit structure is simple and the implementation is convenient.

[0086] Optionally, the interface control circuit 340 further includes a first pull-down resistor 342 and a second pull-down resistor 343. One end of the first pull-down resistor 342 is connected with one output end of the first multiplexer 341, and the other end of the first pull-down resistor 342 is grounded. One end of the second pull-down resistor 343 is connected with the other output end of the first multiplexer 341, and the other end of the second pull-down resistor 343 is grounded.

[0087] The first pull-down resistor and the second pull-down resistor can ensure that the pin connected with the channel which is closed after the channel switching in the first multiplexer maintains low level, so that the pin is prevented from being disturbed by noise.

[0088] Figure 4 is a structural schematic diagram of an electronic device provided by an exemplary embodiment of the present application. As shown in Figure 4 The electronic device includes an SPI interface 410, a GPIO interface 420, a processor 430 and an interface control circuit 440. The SPI interface 410 includes an SCK pin 411, an MISO pin 412 and a MOSI pin 413. The GPIO interface 420 includes a first GPIO pin 421, a third GPIO pin 422 and a fourth GPIO pin 423. The interface control circuit 440 includes a second multiplexer 441 and a third multiplexer 442.

[0089] The second multiplexer 441 has one input terminal, one control terminal and two output terminals, the input terminal of the second multiplexer 441 is connected with the MOSI pin 413, the control terminal of the second multiplexer 441 is connected with the third GPIO pin 422, and one output terminal of the second multiplexer 441 is connected with the TMS pin.

[0090] The third multiplexer 442 has two input terminals, one control terminal and one output terminal, one input terminal of the third multiplexer 442 is connected with the other output terminal of the second multiplexer 441, the other input terminal of the third multiplexer 442 is connected with the first GPIO pin 421, the control terminal of the third multiplexer 442 is connected with the fourth GPIO pin 423, and the output terminal of the third multiplexer 442 is connected with the TDI pin.

[0091] The second multiplexer 441 is configured to, under the action of the first level output by the third GPIO pin 422, connect the MOSI pin 413 with the TMS pin to transmit the first part of the TMS signal to the TMS pin through the MOSI pin 413, or, under the action of the second level output by the third GPIO pin 422, connect the MOSI pin 413 with the input terminal of the third multiplexer 442 to transmit the first part of the TDI signal to the input terminal of the third multiplexer 442 through the MOSI pin 413.

[0092] The third multiplexer 442 is configured to, when the fourth GPIO pin 423 outputs the third level, connect the first GPIO pin 421 with the TDI pin to transmit the second part of the TDI signal to the TDI pin through the first GPIO pin 421, or, when the fourth GPIO pin 423 outputs the fourth level, connect the other output terminal of the second multiplexer 441 with the TDI pin to transmit the first part of the TDI signal output by the other output terminal of the second multiplexer 441 to the TDI pin.

[0093] The processor 430 is further configured to control the third GPIO pin 422 to output the second level and control the fourth GPIO pin 423 to output the fourth level in the first time period, and control the third GPIO pin 422 to output the first level and control the fourth GPIO pin 423 to output the third level in the second time period.

[0094] Optionally, the interface control circuit 440 further comprises a third pull-down resistor 443, one end of the third pull-down resistor 443 is connected with the input terminal of the second multiplexer 441 connected with the TMS pin, and the other end of the third pull-down resistor 443 is grounded.

[0095] When the channel of the third multiplexer connecting the first GPIO pin and the TDI pin is closed, the channel of the second multiplexer connecting the MOSI pin and the input end of the third multiplexer is also closed, so that the level of the TDI pin can be maintained as low, and thus a pull-down resistor does not need to be connected at the TDI pin. The third pull-down resistor connected at the TMS pin can maintain the low level of the TMS pin when the channel of the second multiplexer connecting the MOSI pin and the TMS pin is closed, thereby avoiding noise interference.

[0096] It should be noted that, in the embodiments shown in Figure 4 In the embodiments shown in FIG. 1, the third GPIO pin and the fourth GPIO pin are the same pin. In the case where the third GPIO pin and the fourth GPIO pin are the same pin, the second multiplexer and the third multiplexer can be controlled synchronously. Moreover, the third GPIO pin and the fourth GPIO pin sharing the same pin can reduce the number of GPIO pins required and simplify the circuit structure. In other embodiments, the third GPIO pin and the fourth GPIO pin can also be implemented by two pins.

[0097] In the embodiments shown in FIG. 1, the test data is basically transmitted by the MOSI pin, so that the data transmission rate can basically reach the highest rate supported by the SPI interface. Figure 3 Figure 4 In the embodiments shown in FIG. 1, the test data is basically transmitted by the MOSI pin, so that the data transmission rate can basically reach the highest rate supported by the SPI interface.

[0098] In other embodiments, the processor is configured to control the MOSI pin to send a first part of the TDI signal to the TDI pin in a first time period; control the MOSI pin to send a second part of the TDI signal to the TDI pin in a second time period; and control the first GPIO pin to send a first part of the TMS signal to the TMS pin in the second time period. The second time period is after the first time period and continuous with the first time period.

[0099] In this example, the processor is further configured to control the first GPIO pin to send a second part of the TMS signal to the TMS pin in a third time period. That is, the TMS signal is sent to the TMS pin by the MOSI pin. The third time period is after the second time period and continuous with the second time period.

[0100] Figure 5 is a structural schematic diagram of an electronic device provided by an exemplary embodiment of the present application. As shown in Figure 5 ​As shown, the electronic device includes an SPI interface 510, a GPIO interface 520, a processor 530, and an interface control circuit 540. The SPI interface 510 includes an SCK pin 511, an MISO pin 512, and an MOSI pin 513. The GPIO interface 420 includes a first GPIO pin 521, a fifth GPIO pin 522, and a sixth GPIO pin 523. The interface control circuit 540 includes a fourth multiplexer 541.

[0101] The fourth multiplexer 541 has two input terminals, a control terminal, and an output terminal. One input terminal of the fourth multiplexer 541 is connected to the SCK pin, another input terminal of the fourth multiplexer 541 is connected to the fifth GPIO pin, the control terminal of the fourth multiplexer 541 is connected to the sixth GPIO pin, and the output terminal of the fourth multiplexer 541 is connected to the TCK pin. The fourth multiplexer 541 is configured to output, as a TCK signal, the SCK signal output by the SCK pin 511 to the TCK pin under the action of the fifth level output by the sixth GPIO pin 523, or output, as a TCK signal, the clock signal output by the fifth GPIO pin 522 to the TCK pin under the action of the sixth level output by the sixth GPIO pin 523.

[0102] The processor 530 is further configured to control the sixth GPIO pin to output the fifth level and control the SCK pin to send the SCK signal to the TCK pin in a first time period, and control the sixth GPIO pin to output the sixth level and control the fifth GPIO pin to send the clock signal to the TCK pin in a second time period. In this embodiment, the processor 530 is further configured to control the sixth GPIO pin to output the sixth level and control the fifth GPIO pin to send the clock signal to the TCK pin in a third time period.

[0103] By controlling the fourth multiplexer, when the MOSI pin outputs the TDI signal, the SCK pin can provide a higher-frequency SCK signal as a clock signal to the TCK pin, so that the transmission efficiency of the test data is higher. When the first GPIO pin outputs the TMS signal, the fifth GPIO pin provides a lower-frequency clock signal to the TCK pin, so that the frequencies of the TMS signal and the TCK signal remain consistent. Since the TMS signal is mainly used to control the state change of the TAP controller, the amount of data transmitted is small, so the use of the first GPIO pin to transmit the TMS signal has little effect on the overall data transmission efficiency.

[0104] Alternatively, in some examples, the target JTAG interface further includes a TRST pin. For this purpose, the present embodiment also provides an electronic device suitable for this type of target JTAG interface, and the GPIO interface of the electronic device further includes a seventh GPIO pin for the TRST pin.

[0105] Figure 6 is a structural schematic diagram of another electronic device provided by an example embodiment of the present application. Figure 6 The electronic device shown in Figure 3 The electronic device shown in

[0106] It should be noted that Figure 6 The seventh GPIO pin 323 in Figure 4 or Figure 5 The electronic device shown in

[0107] In Figures 2 to 6 In the embodiment shown in

[0108] Optionally, in Figures 2 to 6 the processor is further configured to perform a bit complement operation on the mode selection data according to the state of the TAP controller, see the method embodiments below.

[0109] The embodiments of the present application also provide a JTAG interface access method. The method is used for accessing a target JTAG interface. The method is executed by an electronic device, for example, any of the electronic devices shown. Figures 2 to 6 The electronic device has an SPI interface and a GPIO interface, the SPI interface includes an SCK pin, an MISO pin and an MOSI pin, and the GPIO interface includes a first GPIO pin. The method can be executed by a processor of the electronic device. Figure 7 is a flowchart of a JTAG interface access method according to an example embodiment of the present application. As Figure 7 shown, the method includes the following processes.

[0110] 701: control the SCK pin to send a TCK signal to the TCK pin;

[0111] 702: control the MISO pin to receive a TDO signal output from the TDO pin;

[0112] 703: control the MOSI pin and the first GPIO pin to send a TMS signal to the TMS pin and a TDI signal to the TDI pin.

[0113] In the embodiment of the present application, some pins of the SPI interface and at least some pins of the GPIO interface are used to simulate the JTAG interface, so that the target JTAG interface is accessed. Compared with the case where all pins of the JTAG interface are simulated by GPIO pins, in the embodiment of the present application, three pins of the SPI interface are used to simulate the pins of the JTAG interface, and the remaining required pins are simulated by GPIO pins, so that the number of required GPIO pins is smaller, which is conducive to the popularization and application of the embodiment of the present application.

[0114] In the embodiment of the present application, the processor 230 is configured to control the MOSI pin to send at least a part of the TDI signal, which carries other data except for the last 1 bit of the test data, for example, so that most of the test data is sent through the MOSI pin. Since the data transmission rate supported by the SPI interface is higher than that of the GPIO interface, compared with sending the test data by using the GPIO pin, the embodiment of the present application can improve the data transmission efficiency, and further improve the efficiency of chip testing.

[0115] Figure 8 FIG. 7 is a schematic diagram of a sending process of a TDI signal and a TMS signal according to an example embodiment of the present application.

[0116] As shown in Figure 8 In some examples, 703 includes:

[0117] 7031a: controlling the MOSI pin to send a first part of the TDI signal to the TDI pin in a first time period;

[0118] 7032a: controlling the MOSI pin to send a first part of the TMS signal to the TMS pin in a second time period; and

[0119] 7033a: controlling the first GPIO pin to send a second part of the TDI signal to the TDI pin in the second time period.

[0120] In 703, the second time period is after and continuous with the first time period.

[0121] For example, for the electronic device shown in Figure 3

[0122] ​7031a comprises: controlling the second GPIO pin 322 to output a second level in the first time period such that the MOSI pin 313 is conductive with the TDI pin, and controlling the MOSI pin to output a first portion of the TDI signal in the first time period. 7032a and 7033a comprise: controlling the second GPIO pin 322 to output a first level in the second time period such that the MOSI pin 313 is conductive with the TMS pin, and controlling the MOSI pin to output a first portion of the TMS signal to the TMS pin in the second time period, and controlling the first GPIO pin to output a second portion of the TDI signal to the TDI pin in the second time period.

[0123] For example, for the electronic device shown in Figure 4

[0124] 7031a comprises: in the first time period, controlling the third GPIO pin 422 to output a second level such that the MOSI pin 413 is conductive with the TDI pin, and controlling the fourth GPIO pin 423 to output a fourth level to make the first GPIO pin 421 conductive with the TMS pin, and controlling the MOSI pin 413 to output a first portion of the TDI signal. 7032a and 7033a comprise: in the second time period, controlling the third GPIO pin 422 to output a first level such that the MOSI pin 413 is conductive with the TMS pin, and controlling the fourth GPIO pin 423 to output a third level to make the first GPIO pin 421 conductive with the TDI pin, and controlling the MOSI pin 413 to output a first portion of the TMS signal, and controlling the MOSI pin to output a second portion of the TDI signal.

[0125] Figure 9 is a schematic diagram of a transmission process of a TDI signal and a TMS signal provided by an exemplary embodiment of the present application.

[0126] As shown in Figure 9 In other examples, 703 comprises:

[0127] 7031b: controlling the MOSI pin to transmit a first portion of the TDI signal to the TDI pin in the first time period;

[0128] 7032b: controlling the MOSI pin to transmit a second portion of the TDI signal to the TDI pin in the second time period; and

[0129] 7033b: controlling the first GPIO pin to transmit a first portion of the TMS signal to the TMS pin in the second time period.

[0130] In Figure 9 ​In a corresponding embodiment, the method of controlling the SCK pin to send the TCK signal to the TCK pin includes: controlling the SCK pin to send the TCK signal to the TCK pin in a first time period. The method further includes controlling the second GPIO pin to send the TCK signal to the TCK pin in a second time period.

[0131] Optionally, before 703, the method further includes: generating a first part and a second part of the TDI signal according to the test data. The first part is used to be sent through the MOSI pin. The second part is used to be sent through the MOSI pin or the first GPIO pin.

[0132] The TDI signal can be generated in the following two ways:

[0133] In the first way, in response to determining that the total length of the test data minus X is equal to an integer multiple of Y, the first part of the TDI signal is generated according to the data in the test data except for the last X bits, and the second part of the TDI signal is generated according to the last X bits of the test data, where Y is the unit length of data transmission supported by the SPI interface. Alternatively, in response to determining that the total length of the test data minus X is not equal to an integer multiple of Y, 0s are padded to the high bits of the test data until the total length of the test data after padding 0s minus X is equal to an integer multiple of Y, the first part of the TDI signal is generated according to the data in the test data after padding 0s except for the last X bits, and the second part of the TDI signal is generated according to the last X bits of the test data after padding 0s.

[0134] In the first way, X is the data length corresponding to the second part of the TDI signal and the first part of the TMS signal required by the JTAG protocol, and Y is the unit length of data transmission supported by the SPI interface, and both X and Y are integers.

[0135] The JTAG interface does not limit the length of the test data and the mode selection data transmitted. At the same time, the JTAG standard requires that the data carried by the second part of the TDI signal and the data carried by the first part of the TMS signal take effect at the same time. That is, the second part of the TDI signal and the first part of the TMS signal need to be sent at the same time.

[0136] In some embodiments, the data format supported by the electronic device with the SPI interface is fixed, that is, the unit length of data transmission is fixed and does not change. In order to meet the data transmission requirements of the JTAG interface and the SPI interface at the same time, it is necessary to ensure that the length of the data sent through the MOSI pin minus X is equal to an integer multiple of Y. Therefore, when the total length of the test data minus X is equal to an integer multiple of Y, 0s need to be padded to the high bits of the test data. Since the TDI signal is serially shifted data, only the last shifted data takes effect, so padding 0s to the high bits of the test data will not affect the actual test data.

[0137] Exemplarily, X equals 1, and Y equals 8 or 16.

[0138] For example, assuming that the total length of the test data minus 1 is not equal to an integer multiple of 8, 0 is added in front of the test data to be sent until the total length of the test data minus 1 is not equal to an integer multiple of 8. The added 0 is sent by using the TDI signal first, and then the actual test data is sent.

[0139] Secondly, data in the test data except for the last X bits is divided into N data sets; a first part of the TDI signal is generated according to data in the N data sets, and a second part of the TDI signal is generated according to the last X bits of data. N is an integer greater than 1, and N is not greater than the number of unit lengths of data transmission supported by the SPI interface. Each data set in the N data sets includes at least one data, the data in any data set in the N data sets has the same length, the data in different data sets in the N data sets has different lengths, and the length of the data in each data set is within a set range, that is, the length of the data in each data set is one of the unit lengths of data transmission supported by the SPI interface.

[0140] Exemplarily, X equals 1, and the set range is 4 bits to 8 bits. The unit lengths of data transmission supported by the SPI interface include 5 types, that is, 4 bits, 5 bits, 6 bits, 7 bits or 8 bits, and the number of the unit lengths of data transmission supported by the SPI interface is 5.

[0141] Assuming that the total length of the test data to be sent minus 1 is equal to 8M+5+4 bits, where M is a positive integer, the test data can be divided into 3 data sets, one data set includes M data with a length of 8, one data set includes one data with a length of 5, and another data set includes one data with a length of 4.

[0142] The SPI interface can generate the TDI signal for sending the data in the first data set in units of 8 bits, generate the TDI signal for sending the data in the second data set in units of 5 bits, and generate the TDI signal for sending the data in the third data set in units of 4 bits.

[0143] The TAP controller is a state machine inside the JTAG interface. By controlling the state transition of the TAP controller, various functions of the JTAG interface can be realized. The state transition mechanism of the TAP controller is briefly introduced as follows. Figure 10 The state transition mechanism of the TAP controller is briefly introduced as follows.

[0144] As Figure 10As shown, the TAP controller has 16 states, the next state of the TAP controller is determined by the TMS signal, which is sampled on the rising edge of TCK.

[0145] The 16 states are as follows:

[0146] 1. Test-Logic-Reset state:

[0147] In the Test-Logic-Reset state, the test logic is disabled to allow normal operation of the chip, reading the IDCODE register will disable the test logic. The TAP controller will enter the Test-Logic-Reset state if the TMS signal is held high for 5 consecutive rising edges of TCK, regardless of the state of the TAP controller. If the TMS signal is always high, the TAP controller will remain in the Test-Logic-Reset state. In addition, the TRST signal can also force the TAP to enter the Test-Logic-Reset state. For the TAP controller in the Test-Logic-Reset state, if the TMS signal is low at the rising edge of the next TCK, the TAP controller will be switched to the Run-Test-Idle state.

[0148] 2. Run-Test-Idle state:

[0149] The Run-Test-Idle state is the idle state of the TAP controller scan operation. If the TMS signal is always low, the TAP controller will remain in the Run-Test-Idle state. When the TMS signal is high at the rising edge of TCK, the TAP controller will enter the Select-DR-Scan state.

[0150] 3. Select-DR-Scan state:

[0151] The Select-DR-Scan state is a temporary state of the TAP controller, the boundary scan register BSR keeps their previous state. When the TMS signal is low at the next rising edge of TCK, the TAP controller enters the Capture-DR state, and the scan operation of a BSR is initialized at the same time. If the TMS signal is high at the next rising edge of TCK, the TAP controller will enter the Select-IR-Scan state.

[0152] 4. Capture-DR state:

[0153] If the TAP controller is in the Capture-DR state and the current instruction is a SAMPLE / PRELOAD instruction, the BSRs capture the data on the TDI pin on the rising edge of the TCK signal. If this is not a SAMPLE / PRELOAD instruction, the BSRs hold their previous values, otherwise the values of the BSRs are put into the shift register connected between the TDI and TDO pins. While in the Capture-DR state, the instruction is not changed. If the TMS signal is high at the next TCK rising edge, the TAP controller enters the Exitl-DR state. If the TMS signal is low at the next TCK rising edge, the TAP controller enters the Shift-DR state.

[0154] 5. Shift Data Register Shift-DR state:

[0155] In the Shift-DR state, the TDI-shift register-TDO serial path is shifted one bit to the right on each rising edge of TCK, the data on TDI is shifted into the shift register and the bit of the shift register closest to TDO is shifted onto the TDO pin. While in the Shift-DR state, the instruction is not changed. If the TMS signal is high at the next TCK rising edge, the TAP enters the Exitl-DR state. If the TMS signal is low, the TAP continues to shift.

[0156] 6. Exit Data Register Exitl-DR state 1:

[0157] The Exitl-DR state is a temporary state of the TAP controller. If the TMS signal is high at the next TCK rising edge, the TAP enters the Update-DR state; if the TMS signal is low at the next TCK rising edge, the TAP enters the Pause-DR state. While in the Exitl-DR state, the instruction is not changed.

[0158] 7. Pause Data Register state Pause-DR:

[0159] The Pause-DR state allows the TAP controller to temporarily stop the shifting of the TDI-shift register-TDO serial path. While in the Pause-DR state, the instruction is not changed. If the TMS signal is high at the next TCK rising edge, the TAP enters the Exit2-DR state; if the TMS signal is low, the TAP remains in the pause state.

[0160] 8. Exit Data Register Exit2-DR state 2:

[0161] Exit2-DR is also a temporary state of the TAP controller. If the TMS signal is high at the next TCK rising edge, the TAP enters the Update-DR state, ending the scan operation. If the TMS signal is low at the next TCK rising edge, the TAP re-enters the Shift-DR state. No instruction is changed while in the Exit2-DR state.

[0162] 9. Update Data Register Update-DR state:

[0163] Under normal circumstances, the value of the boundary scan register BSR is latched into the parallel output pins so as not to change the value of the BSR when the shift operation is performed under the EXTEST or SAMPLE / PRELOAD command. When the BSR register is selected while in the Update-DR state, the value in the shift register will be latched into the parallel output pins of the BSR register at the falling edge of the TCK. No instruction is changed while in the Update-DR state. If the TMS signal is high at the next TCK rising edge, the TAP enters the Select-DR-Scan state. If the TMS signal is low at the next TCK rising edge, the TAP enters the Run-Test-Idle state.

[0164] 10. Select Instruction Register Scan Select-IR-Scan state:

[0165] Select-IR-Scan is a temporary state of the TAP controller.

[0166] If the TMS signal is low at the next TCK rising edge, the TAP controller enters the Capture-IR state, and a scan operation on the instruction register is simultaneously initialized. If the TMS signal is high at the next TCK rising edge, the TAP controller enters the Test-Logic-Reset state. No instruction is changed while in the Select-IR-Scan state.

[0167] 11. Capture Instruction Register Capture-IR state:

[0168] While in the Capture-IR state, the value in the instruction register is fixedly set to 0b0000001, and it is placed into the shift register connected between TDI and TDO. No instruction is changed while in the Capture-DR state. If the TMS signal is high at the next TCK rising edge, the TAP controller enters the Exitl-IR state. If the TMS signal is low at the next TCK rising edge, the TAP controller enters the Shift-IR state.

[0169] 12. Shift-IR state of instruction register:

[0170] In the Shift-IR state, at the rising edge of each TCK signal, the TDI-shift register-TDO serial channel is shifted one bit to the right, the JTAG instruction is shifted into the shift register from the TDI pin bit by bit, and 0b0000001 in the shift register is shifted out from the TDO pin bit by bit. In the Shift-IR state, the instruction is not changed. If the TMS signal is at high level at the next TCK rising edge, the TAP controller enters the Exitl-IR state; if the TMS signal is at low level, the TAP controller continues the shift operation.

[0171] 13. Exitl-IR state 1 of instruction register:

[0172] The Exitl-IR state is a temporary state of the TAP controller. If the TMS signal is at high level at the next TCK rising edge, the TAP controller enters the Update-IR state; if the TMS signal is at low level at the next TCK rising edge, the TAP controller enters the Pause-IR state. In the Exitl-IR state, the instruction is not changed.

[0173] 14. Pause-IR state of instruction register:

[0174] The Pause-IR state allows the TAP controller to temporarily stop the shift operation of the TDI-shift register-TDO serial channel. In the Pause-IR state, the instruction is not changed. If the TMS signal is at high level at the next TCK rising edge, the TAP controller enters the Exit2-IR state; if the TMS signal is at low level, the TAP controller is in the pause state.

[0175] 15. Exit2-IR state 2 of instruction register:

[0176] The Exit2-IR is also a temporary state of the TAP controller. If the TMS signal is at high level at the next TCK rising edge, the TAP controller enters the Update-IR state to end the scan operation; if the TMS signal is at low level at the next TCK rising edge, the TAP controller reenters the Shift-IR state. In the Exit2-D state, the instruction is not changed.

[0177] 16. Update-IR state of instruction register:

[0178] When in the Update-IR state, the values in the shift register are latched into the instruction register on the falling edge of TCK, and once latched successfully, the new instruction becomes the current instruction. If the TMS signal is at high level at the next TCK rising edge, the TAP enters the Select-DR-Scan state; if the TMS signal is at low level at the next TCK rising edge, the TAP enters the Run-Test-Idle state.

[0179] As described above, since the SPI interface has a requirement on the unit length of data transmitted through the MOSI pin, when mode selection data is transmitted by using the MOSI pin, whether the length of the mode selection data meets the requirement of the SPI interface also needs to be considered. The method further includes: performing a padding operation on the mode selection data according to a unit length of data transmission supported by the SPI interface, to obtain padded mode selection data; and generating the TMS signal according to the padded mode selection data.

[0180] In the embodiments of the present application, the mode selection data is used to control the state transition of the TAP controller. Exemplarily, the mode selection data includes first mode selection data and second mode selection data. The first mode selection data is used to control the TAP controller to transition from the idle state to the select data register scan state or the select instruction register scan state. The second mode selection data is used to control the TAP controller to transition from the update data register state or the update instruction register state to the idle state.

[0181] Optionally, the padding operation on the mode selection data according to the unit length of data transmission supported by the SPI interface includes at least one of the following: padding 0 at high bits of the first mode selection data according to the unit length; and padding 0 at low bits of the second mode selection data according to the unit length.

[0182] In some embodiments, the padding 0 at high bits of the first mode selection data according to the unit length includes: padding 0 at high bits of the first mode selection data until the length of the first mode selection data after padding 0 is the unit length supported by the SPI interface.

[0183] From Figure 10 It can be seen that when the TAP controller needs to jump from the idle state to the select DR scan state or the select IR scan state, 0 is padded at high bits of the first mode selection data, and the TAP controller still remains in the idle state, and therefore, padding 0 at high bits of the first mode selection data does not affect the state transition of the TAP controller.

[0184] For example, it is assumed that the unit length of data transmission supported by the SPI interface is 8 bits, and the first mode selection data is used to control the TAP controller to transition from the idle state to the select instruction register scan state. As described above, the length of the first mode selection data is 8 bits, which meets the requirement of the SPI interface. Therefore, the TAP controller can transition from the idle state to the select instruction register scan state. Figure 10As shown, it takes 2 1s to make the TAP controller transit from the idle state to the select instruction register scan state, so the first mode selection data is 11. The first mode selection data is padded with 0s in the high bits, and the padded first mode selection data is 00000011. The generated TMS signal sends 6 0s first, and the TAP controller stays in the idle state, and then the TMS signal sends 2 1s, so that the TAP controller transits from the idle state to the select instruction register scan state.

[0185] Optionally, the first mode selection data is also used to control the TAP controller to transit from the select data register scan state to at least one data register related state after the select data register scan state, such as the shift data register state, or to control the TAP controller to transit from the select instruction register scan state to at least one instruction register related state after the select instruction register scan state, such as the shift instruction register state. For example, the first mode selection data is 1100, and the padded first mode selection data is 00001100.

[0186] In the embodiments of the present application, the final state of the TAP controller corresponding to the first mode selection data is determined by the actual flow.

[0187] In some embodiments, the low bits of the second mode selection data are padded with 0s according to the unit length, including: the low bits of the second mode selection data are padded with 0s until the length of the padded second mode selection data is the unit length supported by the SPI interface.

[0188] Optionally, the second mode selection data is also used to control the TAP controller to transit from at least one data register related state (such as the shift data register state) before the update data register state to the update data register state, or to control the TAP controller to transit from at least one instruction register related state (such as the shift instruction register state) before the update instruction register state to the update instruction register state.

[0189] From Figure 10 As can be seen, when the TAP controller is in the update DR state or the update IR state, if the data carried by the received TMS signal is 0, the TAP controller will transit to the idle state. Therefore, padding the low bits of the second mode selection data with 0s can ensure that the TAP controller transits to the idle state before each DR related flow or IR related flow is performed, so as to ensure the reliable operation of the JTAG interface.

[0190] In some examples, a TMS signal is generated directly based on the padded mode selection data. In other embodiments, for the consecutively transmitted second mode selection data and first mode selection data, after the upper bits of the first mode selection data are padded with 0s and the lower bits of the second mode selection data are padded with 0s, and before the TMS signal is generated, the method further includes: determining whether to merge and reduce the first mode selection data padded with 0s and the second mode selection data padded with 0s based on the sum of the number of 0s padded with the upper bits and the number of 0s padded with the lower bits.

[0191] For example, if the sum of the number of high-order zeros and the number of low-order zeros padded is greater than or equal to the length of the data transmission unit supported by the SPI interface, the first mode selection data after the high-order zeros are padded is spliced ​​after the second mode selection data after the low-order zeros are padded, and then the eight consecutive zeros are removed, and the TMS signal is generated based on the mode selection data after the zeros are removed. If the sum of the number of high-order zeros and the number of low-order zeros padded is less than the length of the data transmission unit supported by the SPI interface, the TMS signal is directly generated based on the padded mode selection data.

[0192] For example, assuming the SPI interface supports an 8-bit unit length, when the second mode selection data is used to control the TAP controller to switch from the shift instruction register state to the idle state, the second mode selection data is 110, and the second mode selection data after the low-order bits are padded with zeros is 11000000. Next, the first mode selection data is used to control the TAP controller to switch from the idle state to the shift data register state. The first mode selection data is 1100, and the first mode selection data after the high-order bits are padded with zeros is 000011000. The number of 0s padded with the high-order bits is 5, and the number of 0s padded with the low-order bits is 4, and the sum of the two is greater than 8. In this case, the first mode selection data after the high-order bits are padded with zeros is concatenated after the second mode selection data after the low-order bits are padded with zeros, and then the eight consecutive zeros are removed to obtain 11011000. A TMS signal is then generated based on 11011000.

[0193] Figure 11 1 is a timing diagram of an instruction for controlling data register shifting provided by an exemplary embodiment of the present application. Figure 11 The upper part is the SPI access timing and GPIO access timing, and the lower part is the JTAG SDR instruction timing. Figure 3 The electronic device shown.

[0194] like Figure 11 As shown, the signal waveform sent by the TCK pin is the same as the signal waveform received by the CLK pin, that is, the TCK signal output by the CLK pin is provided to the TCK pin as a clock signal.

[0195] The GPIO signal waveform output by the second GPIO pin is as followsFigure 11 The third waveform shows that when the GPIO signal output by the second GPIO pin is high, the MOSI pin sends the TMS signal to the TMS pin. When the GPIO signal output by the second GPIO pin is low, the MOSI pin sends the TDI signal to the TDI pin. The rising edge and the falling edge are both instruction switching times.

[0196] When the first high level is output by the second GPIO pin, the signal sent by the MOSI pin is 00000100, as the TMS signal. In combination with the TMS signal, the TAP controller state is switched from TLR to RTI and remains in the RTI state until the TMS signal sends 1, and the TAP controller is switched to the SDR state. Then when the TMS signal sends 0, the TAP controller state is switched to the CDR state. Then when the TMS signal sends 0, it is switched to the SDR state. After the TAP controller is switched to the SDR state, the second GPIO pin outputs a low level, and the MOSI pin is switched to output the TDI signal to the TDI pin. At this time, the TMS signal remains low, indicating that the TMS signal sends 0 all the time, and the TAP controller remains in the SDR state until the second GPIO pin outputs a high level again, and the MOSI pin is switched to output the TMS signal to the TMS pin and the TMS signal is 11000000. When the TMS signal sends the first 1, the TAP controller is switched to the EDR state, and when the TMS signal sends the second 1, the TAP controller is switched to the UDR state. Finally, the TMS signal sends a string of 0, and the TAP controller is switched to the RTI state and remains in the RTI state. Figure 10

[0197] When the second GPIO pin outputs a low level, the TDI signal sent by the MOSI pin is 10011111. Then, the signal output by the second GPIO pin is switched from low to high, and at the same time, the last 1 bit TDI signal output by the first GPIO pin, i.e., 0, takes effect at the same time as the first bit of the TMS signal. That is, the complete TDI signal output by the electronic device is 100111110.

[0198] The signal waveform received by the MOSI pin is the same as the signal waveform sent by the TDO pin, that is, the TDO signal output by the TDO pin is provided to the MOSI pin.

[0199] Figure 12 is a timing diagram of the instruction for controlling the bit shift of the instruction register provided by an exemplary embodiment of the present application. Figure 12 In the figure, the upper half is the SPI access timing and the GPIO access timing, and the lower half is the JTAG SIR instruction timing. The timing is used to control the electronic device shown in the figure. Figure 3 In the figure, the upper half is the SPI access timing and the GPIO access timing, and the lower half is the JTAG SIR instruction timing. The timing is used to control the electronic device shown in the figure.​

[0200] As shown in FIG. 3, the signal waveform sent by the TCK pin is the same as the signal waveform received by the CLK pin, i.e. the TCK signal output by the CLK pin is provided as a clock signal to the TCK pin. Figure 12

[0201] The GPIO signal waveform output by the second GPIO pin is shown in the third waveform in FIG. 4. When the GPIO signal output by the second GPIO pin is high, the MOSI pin sends a TMS signal to the TMS pin. When the GPIO signal output by the second GPIO pin is low, the MOSI pin sends a TDI signal to the TDI pin. The rising edge and the falling edge are both instruction switching times. Figure 12 When the second GPIO pin outputs the first high level, the signal sent by the MOSI pin is 00001100 as a TMS signal. In combination with the indication of 0000 in the TMS signal, the TAP controller state is converted from TLR to RTI and remains in the RTI state until the TMS signal sends 1, the TAP controller is converted to the SDR state. Then, the TMS signal sends another 1, the TAP controller is switched to the SIR state. Then the TMS signal sends 0, the TAP controller is switched to the CIR state. Then the TMS signal sends 0, the TAP controller is switched to the SIR state. After the TAP controller is switched to the SIR state, the second GPIO pin outputs a low level, the MOSI pin is switched to output a TDI signal to the TDI pin. At this time, the TMS signal remains low, indicating that the TMS signal sends 0 all the time, the TAP controller remains in the SIR state until the second GPIO pin outputs a high level again, the MOSI pin is switched to output a TMS signal to the TMS pin and the TMS signal is 11000000. When the TMS signal sends the first 1, the TAP controller is switched to the EIR state, and when the TMS signal sends the second 1, the TAP controller is switched to the UIR state. Finally, the TMS signal sends a string of 0, the TAP controller is switched to the RTI state and remains in the RTI state.

[0202] Figure 10 When the second GPIO pin outputs a low level, the TDI signal sent by the MOSI pin is 10011111. Then, the signal output by the second GPIO pin is switched from low to high, and at the same time, the last 1 bit TDI signal output by the first GPIO pin, i.e. 0, takes effect at the same time as the first bit of the TMS signal. That is, the complete TDI signal output by the electronic device is 100111110.

[0203] When the second GPIO pin outputs a low level, the TDI signal sent by the MOSI pin is 10011111. Then, the signal output by the second GPIO pin is switched from low to high, and at the same time, the last 1 bit TDI signal output by the first GPIO pin, i.e. 0, takes effect at the same time as the first bit of the TMS signal. That is, the complete TDI signal output by the electronic device is 100111110.

[0204] ​​The signal waveform received by the MOSI pin is the same as the signal waveform sent by the TDO pin, that is, the TDO signal output by the TDO pin is provided to the MOSI pin.

[0205] From Figure 11 And Figure 12 It can be seen that the embodiment of the present application can simulate the JTAG interface by using the SPI interface and the GPIO interface, and access the target JTAG interface.

[0206] In the embodiment of the present application, a computer device is also provided, for example, the electronic chip described above. Figure 13 An exemplary possible architecture diagram of the computer device 1300 is provided.

[0207] The computer device 1300 includes a memory 1301, a processor 1302, a communication interface 1303 and a bus 1304. The memory 1301, the processor 1302 and the communication interface 1303 are communicatively connected to each other through the bus 1304.

[0208] The memory 1301 can be a read-only memory (ROM), a static storage device, a dynamic storage device or a random access memory (RAM). The memory 1301 can store a program, and when the program stored in the memory 1301 is executed by the processor 1302, the processor 1302 and the communication interface 1303 are used to execute the access method of the JTAG interface. The memory 1301 can also store a data set, for example: a part of the storage resource in the memory 1301 is divided into a data set storage module for storing test data, etc.

[0209] The processor 1302 can be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), a graphics processing unit (GPU) or one or more integrated circuits.

[0210] The processor 1302 can also be an integrated circuit chip having signal processing capability. In implementation, part or all of the functions of the JTAG interface access device of the present application can be completed by integrated logic circuits of hardware in the processor 1302 or instructions in the form of software. The processor 1302 described above can also be a general processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic, discrete gate or transistor logic, discrete hardware components. The disclosed methods in the above embodiments of the present application can be implemented or executed. The general processor can be a microprocessor or the processor can also be any conventional processor. The steps of the method disclosed in combination with the embodiments of the present application can be directly embodied as hardware code processor execution or executed by a combination of hardware and software modules in the code processor. The software module can be located in a random access memory, a flash memory, a read only memory, a programmable read only memory or an electrically erasable programmable memory, a register or other mature storage medium in the art. The storage medium is located in the memory 1301, and the processor 1302 reads the information in the memory 1301 and combines the hardware to complete part of the functions of the JTAG interface access device of the embodiments of the present application.

[0211] The communication interface 1303 at least includes an SPI interface and a GPIO interface. The communication interface 1303 uses a transceiving module such as but not limited to a transceiver to realize the communication between the computer device 1300 and other devices or communication networks. For example, the TDI signal, the TMS signal and the TCK signal can be transmitted through the communication interface 1303, the TDO signal can be received through the communication interface 1303, and the like.

[0212] The bus 1304 can include a path for transmitting information between various components (for example, the memory 1301, the processor 1302, the communication interface 1303) of the computer device 1300.

[0213] The description of the flow corresponding to each of the above figures has its own emphasis, and the part not described in detail in a certain flow can refer to the related description of other flows.

[0214] In the embodiments of the present application, a computer readable storage medium is also provided, and the computer readable storage medium stores computer instructions. When the computer instructions stored in the computer readable storage medium are executed by a computer device, the computer device executes the JTAG interface access method provided above.

[0215] In the embodiments of the present application, a computer program product including instructions is also provided, which, when running on a computer device, causes the computer device to perform the method for accessing the JTAG interface provided above.

[0216] In the embodiments described above, the implementation can be achieved wholly or partially by software, hardware, firmware, or any combination thereof, and when implemented by software, the implementation can be in the form of a computer program product. The computer program product includes one or more computer instructions, which, when loaded and executed on a server or terminal, generates the processes or functions described in the embodiments of the present application wholly or partially. The computer instructions can be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center through wired (such as coaxial cable, optical fiber, digital subscriber line) or wireless (such as infrared, wireless, microwave, etc.) mode. The computer readable storage medium can be any available medium accessible by the server or terminal or a data storage device such as a server, data center, etc. integrated with one or more available media. The available medium can be a magnetic medium (such as floppy disk, hard disk and magnetic tape, etc.), an optical medium (such as Digital Video Disk (DVD), etc.), or a semiconductor medium (such as solid state disk, etc.).

Claims

1. An electronic device, characterized by comprising: The electronic device is used for accessing a target Joint Test Action Group (JTAG) interface, the target JTAG interface comprising a test clock (TCK) pin, a test data input (TDI) pin, a test data output (TDO) pin and a test mode select (TMS) pin, the electronic device comprising: a serial peripheral interface (SPI) interface, a general-purpose input / output (GPIO) interface and a processor; The SPI interface comprises a serial clock (SCK) pin, a master input / slave output (MISO) pin and a master output / slave input (MOSI) pin; The GPIO interface comprises a first GPIO pin; The processor is configured to: control the SCK pin to send a TCK signal to the TCK pin, control the MISO pin to receive a TDO signal output from the TDO pin, and control the MOSI pin and the first GPIO pin to output a TMS signal to the TMS pin and output a TDI signal to the TDI pin.

2. Electronic device according to claim 1, characterized in that The processor is configured to: control the MOSI pin to send a first part of the TDI signal to the TDI pin in a first time period; control the MOSI pin to send a first part of the TMS signal to the TMS pin in a second time period, and control the first GPIO pin to send a second part of the TDI signal to the TDI pin in the second time period; The first GPIO pin is connected with the TDI pin, the GPIO interface further comprises a second GPIO pin, and the electronic device further comprises an interface control circuit, the interface control circuit comprising a first multiplexer having one input end, one control end and two output ends, the input end of the first multiplexer being connected with the MOSI pin, the control end of the first multiplexer being connected with the second GPIO pin, one output end of the first multiplexer being connected with the TMS pin, and the other output end of the first multiplexer being connected with the TDI pin; 3. Electronic device according to claim 2, characterized in that The first multiplexer is configured to, under the action of a first level output by the second GPIO pin, conduct the MOSI pin and the TMS pin to send the first part of the TMS signal to the TMS pin through the MOSI pin, or, under the action of a second level output by the second GPIO pin, conduct the MOSI pin and the TDI pin to send the first part of the TDI signal to the TDI pin through the MOSI pin; The processor is further configured to control the second GPIO pin to output the second level in the first time period, and control the second GPIO pin to output the first level in the second time period. ​ 4. Electronic device according to claim 3, characterized in that The interface control circuit further comprises a first pull-down resistor and a second pull-down resistor, one end of the first pull-down resistor is connected with one output end of the first multiplexer, the other end of the first pull-down resistor is grounded, one end of the second pull-down resistor is connected with the other output end of the first multiplexer, the other end of the second pull-down resistor is grounded.

5. Electronic device according to claim 2, characterized in that The GPIO interface further comprises a third GPIO pin and a fourth GPIO pin, and the electronic device further comprises an interface control circuit, the interface control circuit comprises a second multiplexer and a third multiplexer, The second multiplexer has one input end, one control end and two output ends, the input end of the second multiplexer is connected with the MOSI pin, the control end of the second multiplexer is connected with the third GPIO pin, one output end of the second multiplexer is connected with the TMS pin; The second multiplexer is configured to, under the action of a first level output by the third GPIO pin, turn on the MOSI pin and the TMS pin to send a first part of a TMS signal to the TMS pin through the MOSI pin, or, under the action of a second level output by the third GPIO pin, turn on the MOSI pin and the input end of the third multiplexer to send a first part of a TDI signal to the third multiplexer through the MOSI pin; The third multiplexer has two input ends, one control end and one output end, one input end of the third multiplexer is connected with the other output end of the second multiplexer, the other input end of the third multiplexer is connected with the first GPIO pin, the control end of the third multiplexer is connected with the fourth GPIO pin, and the output end of the third multiplexer is connected with the TDI pin; The third multiplexer is configured to, when the fourth GPIO pin outputs a third level, turn on the first GPIO pin and the TDI pin to send a second part of the TDI signal to the TDI pin through the first GPIO pin, or, when the fourth GPIO pin outputs a fourth level, turn on the other output end of the second multiplexer and the TDI pin to send the first part of the TDI signal output by the other output end of the second multiplexer to the TDI pin; The processor is further configured to control the third GPIO pin to output the second level and control the fourth GPIO pin to output the fourth level in the first time period, and control the third GPIO pin to output the first level and control the fourth GPIO pin to output the third level in the second time period.

6. Electronic device according to claim 5, characterized in that The interface control circuit further comprises a third pull-down resistor, one end of the third pull-down resistor is connected with the input end of the second multiplexer connected with the TMS pin, and the other end of the third pull-down resistor is grounded.

7. The electronic device of claim 1, wherein, The processor is configured to: control the MOSI pin to send the first part of the TDI signal to the TDI pin in a first time period; control the MOSI pin to send a second part of the TDI signal to the TDI pin in a second time period; and control the first GPIO pin to send a first part of the TMS signal to the TMS pin in the second time period; wherein the second time period is after and continuous with the first time period.

8. Electronic device according to claim 7, characterized in that The GPIO interface further includes a fifth GPIO pin and a sixth GPIO pin, and the electronic device further includes an interface control circuit, the interface control circuit including a fourth multiplexer, the fourth multiplexer having two input terminals, a control terminal and an output terminal, one input terminal of the fourth multiplexer being connected with the SCK pin, the other input terminal of the fourth multiplexer being connected with the fifth GPIO pin, the control terminal of the fourth multiplexer being connected with the sixth GPIO pin, and the output terminal of the fourth multiplexer being connected with the TCK pin; the fourth multiplexer being configured to, under the action of a fifth level output by the sixth GPIO pin, turn on the SCK pin and the TCK pin to transmit an SCK signal output by the SCK pin to the TCK pin as the TCK signal, or, under the action of a sixth level output by the sixth GPIO pin, output a clock signal output by the fifth GPIO pin to the TCK pin as the TCK signal; the processor being further configured to control the sixth GPIO pin to output the fifth level and control the SCK pin to send the SCK signal to the TCK pin in the first time period, and control the sixth GPIO pin to output the sixth level and control the fifth GPIO pin to send the clock signal to the TCK pin in the second time period.

9. Electronic device according to any one of claims 1 to 8, characterized in that The target JTAG interface further includes a TRST pin, and the GPIO interface further includes a seventh GPIO pin, the processor being further configured to control the seventh GPIO pin to send a TRST signal to the TRST pin.

10. Electronic device according to any one of claims 2 to 9, characterized in that, The processor is further configured to: in response to determining that the total length of the test data minus X is equal to an integer multiple of Y, generate the first part of the TDI signal according to data in the test data except for the last X bits and generate the second part of the TDI signal according to the last X bits in the test data, wherein Y is a unit length of data transmission supported by the SPI interface; or in response to determining that the total length of the test data minus X is not equal to an integer multiple of Y, pad 0 to the high bits of the test data until the total length of the test data after padding 0 minus X is equal to an integer multiple of Y, generate the first part of the TDI signal according to data in the test data after padding 0 except for the last X bits and generate the second part of the TDI signal according to the last X bits in the test data after padding 0, wherein Y is a unit length of data transmission supported by the SPI interface.

11. Electronic device according to any one of claims 2 to 9, characterized in that the processor being further configured to: divide data in the test data except for the last X bits into N data sets, N being an integer greater than 1 and N not being greater than a number of unit lengths of data transmission supported by the SPI interface, each of the N data sets including at least one data, data in any of the N data sets being of a same length, data in different ones of the N data sets being of different lengths, the length of the data in the any of the N data sets being one of the unit lengths of data transmission supported by the SPI interface; generate a first part of the TDI signal according to the data in the N data sets, and generate a second part of the TDI signal according to the last X bits of data.

12. Electronic device according to any one of claims 1 to 11, characterized in that The processor is further configured to: pad mode selection data according to the unit length of data transmission supported by the SPI interface to obtain padded mode selection data; generate the TMS signal according to the padded mode selection data.

13. Electronic device according to claim 12, characterized in that The processor is configured to pad the mode selection data according to at least one of: pad 0s in high bits of first mode selection data according to the unit length, the first mode selection data being used to control a test access port (TAP) controller to transition from an idle state to a selected data register scan state or a selected instruction register scan state; and pad 0s in low bits of second mode selection data according to the unit length, the second mode selection data being used to control the TAP controller to transition from an updated data register state or an updated instruction register state to the idle state.

14. A method of accessing a JTAG interface, characterized by, The method is used for accessing a target JTAG interface, the target JTAG interface including a TCK pin, a TDI pin, a TDO pin, and a TMS pin, the method being applied to an electronic device, the electronic device including a serial peripheral interface (SPI) interface, a general-purpose input / output (GPIO) interface, and a processor, the SPI interface including an SCK pin, a MISO pin, and a MOSI pin, the GPIO interface including a first GPIO pin, and the method including: controlling, by the processor, the SCK pin to send a TCK signal to the TCK pin; controlling, by the processor, the MISO pin to receive a TDO signal output from the TDO pin; and controlling, by the processor, the MOSI pin and the first GPIO pin to send a TMS signal to the TMS pin and to send a TDI signal to the TDI pin.

15. The method of claim 14, wherein, The controlling the MOSI pin and the first GPIO pin to send the TMS signal to the TMS pin and to send the TDI signal to the TDI pin includes: controlling the MOSI pin to send a first part of the TDI signal to the TDI pin in a first time period; controlling the MOSI pin to send a first part of the TMS signal to the TMS pin in a second time period; and controlling the first GPIO pin to send a second part of the TDI signal to the TDI pin in the second time period. The second time period is after the first time period and continuous with the first time period.

16. The method of claim 14, wherein, The control of the MOSI pin and the first GPIO pin to send the TMS signal to the TMS pin and the TDI signal to the TDI pin comprises: controlling the MOSI pin to send a first part of the TDI signal to the TDI pin in a first time period; controlling the MOSI pin to send a second part of the TDI signal to the TDI pin in a second time period; and controlling the first GPIO pin to send a first part of the TMS signal to the TMS pin in the second time period; The second time period is after the first time period and continuous with the first time period.

17. The method of claim 16, wherein, The control of the SCK pin to send the TCK signal to the TCK pin comprises: controlling the SCK pin to send the TCK signal to the TCK pin in the first time period; The method further comprises: controlling a second GPIO pin to send the TCK signal to the TCK pin in the second time period.

18. The method according to any one of claims 15 to 17, characterized in that Before the control of the MOSI pin and the first GPIO pin to send the TMS signal to the TMS pin and the TDI signal to the TDI pin, the method further comprises: in response to determining that the total length of the test data minus X is equal to an integer multiple of Y, generating the first part of the TDI signal according to the data in the test data except for the last X bits and generating the second part of the TDI signal according to the last X bits in the test data, wherein Y is the unit length of data transmission supported by the SPI interface; or in response to determining that the total length of the test data minus X is not equal to an integer multiple of Y, padding 0 to the high bits of the test data until the total length of the test data after padding 0 minus X is equal to an integer multiple of Y, generating the first part of the TDI signal according to the data in the test data after padding 0 except for the last X bits and generating the second part of the TDI signal according to the last X bits in the test data after padding 0, wherein Y is the unit length of data transmission supported by the SPI interface.

19. The method according to any one of claims 15 to 17, characterized in that, Before the control of the MOSI pin and the first GPIO pin to send the TMS signal to the TMS pin and the TDI signal to the TDI pin, the method further comprises: dividing the data in the test data except for the last X bits into N data sets, N being an integer greater than 1 and N not greater than the number of unit lengths of data transmission supported by the SPI interface, each data set in the N data sets comprising at least one data, the data in any data set in the N data sets having the same length, the data in different data sets in the N data sets having different lengths, the length of the data in the any data set being one of the unit lengths of data transmission supported by the SPI interface; The first part of the TDI signal is generated according to data in the N data sets, and the second part of the TDI signal is generated according to the last X bits of data.

20. The method according to any one of claims 14 to 19, characterized in that, Before the control MOSI pin and the first GPIO pin send a TMS signal to the TMS pin and a TDI signal to the TDI pin, the method further comprises: According to the unit length of data transmission supported by the SPI interface, the mode selection data is padded to obtain padded mode selection data; The TMS signal is generated according to the padded mode selection data.

21. The method of claim 20, wherein, The padding operation on the TMS data according to the state of the test access port (TAP) controller comprises at least one of the following: According to the unit length, 0 is padded at the high bit of first mode selection data, and the first mode selection data is used to control the test access port (TAP) controller to switch from an idle state to a selected data register scan state or a selected instruction register scan state; and According to the unit length, 0 is padded at the low bit of second mode selection data, and the second mode selection data is used to control the TAP controller to switch from an updated data register state or an updated instruction register state to an idle state.

22. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer instructions, when the computer instructions in the computer readable storage medium are executed by a computer device, the computer device executes the method in any one of claims 14 to 21.

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