Integer multiplication device based on Karatsuba algorithm

Abstract

The present application provides an integer multiplication device based on the Karatsuba algorithm, which is used to implement the multiplication operation of two input data that are evenly divided into N items. The device includes a reordering module, a pre-calculation module, a multiplication module, a post-processing module, and an addition and merging module. The reordering module is used to reorder the N coefficients, the pre-calculation module calculates the cross-core input coefficients, and the multiplication module includes N / 2-point Karatsuba multiplication submodules. Furthermore, the multiplication module does not merge the output results during the recursive process. Instead, it uses the post-processing module to obtain the zeroth output data, the odd-numbered output data, and the even-numbered output data. The addition and merging module then splits, splices, and merges the output data to obtain the final multiplication result, thus saving hardware resources and reducing latency.

Description

Technical Field

[0001] The present application relates to the technical field of cryptography, and in particular to an integer multiplication device. Background Art

[0002] Integer multiplication has important applications in cryptography. The Karatsuba algorithm is an important fast integer multiplication algorithm used when the integer digits are small.

[0003] The first-order Karatsuba algorithm splits each of the two input multipliers into two terms, then performs three decimal multiplications, along with a small number of additions and shifts: a1, a0 and b1, b0. When the multiplier is L bits, the original multiplication requires four L / 2-bit multiplications and three L-bit additions. However, the first-order Karatsuba algorithm reduces this complexity to three L / 2-bit multiplications, four L-bit additions, and two L / 2-bit additions. The specific multiplication process of the first-order Karatsuba algorithm is as follows:

[0004] (a12 L / 2 +a0)(b12 L / 2 +b0)=a1b12 L +(a1b0+a0b1)2 L / 2 +a0b0

[0005] =a1b12 L +((a1+a0)(b1+b0)-a1b1-a0b0)2 L / 2 +a0b0

[0006] According to the first-order Karatsuba algorithm, the second-order Karatsuba algorithm can be derived, that is, the multiplier is divided into four terms. The specific multiplication process is as follows:

[0007] (a32 3L / 2 +a22 L +a12 L / 2 +a0)(b32 3L / 2 +b22 L +b12 L / 2 +b0)

[0008] =(a1 * 2 L / 2 +a0 * )b1 * 2 L / 2 +b0 * )

[0009] =a1 * b1 * 2 L +((a1 * +a0* )(b1 * +b0 * )-a1 * b1 * -a0 * b0 * )2 L / 2 +a0 * b0 *

[0010] Among them, a0 * =a22 L +a0,a1 * =a32 L +a1,b0 * =b22 L +b0,b1 * =b32 L +b1. For a1 * b1 * ,(a1 * +a0 * )(b1 * +b0 * ) and a0 * b0 * The first-order Karatsuba algorithm can be used to calculate each one. For algorithms with a larger number of input items, a higher-order Karatsuba algorithm can be used. For example, when the number of items is N, a recursive Karatsuba algorithm of order k = log2N is required. Similar to the above method, the k-1 order Karatsuba algorithm is used three times and iterates back to the first-order Karatsuba algorithm. The recursive Karatsuba algorithm (KOA, Karatsuba-Ofman Algorithms) is shown below:

[0011] AlgorithmKOA(X,Y)

[0012] If(Size(X)=1)then

[0013] Result:OneBitMultiplier(X,Y)

[0014] Else

[0015] SumX:=High(X)+Low(X);

[0016] SumY:=High(X)+Low(Y);

[0017] KOA1:KOA(High(X),High(Y),Product1);

[0018] KOA2:KOA(Low(X),Low(Y),Product2);

[0019] KOA3:KOA(SumX,SumY,Product3);

[0020] RightShiftadd1:Result:=RightShiftadd(Product1,Size(X))+RightShift(Product3–

[0021] Product1–Product2,Size(X) / 2)+Product2;

[0022] Endalgorithm.

[0023] Current integer multiplication devices, based on the recursive Karatsuba algorithm, split large number multiplication into three partial product operations. Each partial product operation is recursively calculated using the same algorithm until the large number is split into two product multiplications. However, each recursive operation requires combining the results of the previous recursion through shifting and adding. These operations consume significant resources and result in significant latency. Summary of the Invention

[0024] In order to solve the problem that the current integer multiplication device needs to merge the results of the previous recursion through shift operations and addition operations during each recursion, and the merging operation uses shift and addition operations, which consumes a lot of resources and has a long delay, the present application provides an integer multiplication device based on the Karatsuba algorithm through the following aspects.

[0025] In a first aspect of the present application, an integer multiplication device based on the Karatsuba algorithm is provided for multiplying two input data, wherein the two input data are divided into N items respectively. The integer multiplication device includes: a reordering module, a pre-calculation module, a multiplication module, a post-processing module, and an addition and merging module;

[0026] The reordering module is used to reorder the N coefficients of the input data based on a preset model to obtain the reordered coefficients and output them to the multiplication module and the pre-calculation module;

[0027] The pre-calculation module is used to perform pre-calculation based on the rearrangement coefficients to obtain the cross-core input coefficients, and output them to the multiplication module, where the number of terms of the cross-core input coefficients is N / 2;

[0028] The multiplication module includes an N / 2-point karatsuba multiplication submodule, the multiplication module being configured to perform calculations based on even-numbered core input coefficients to obtain even-numbered core output data, and to perform calculations based on odd-numbered core input coefficients to obtain odd-numbered core output data, and to perform calculations based on cross-numbered core input coefficients to obtain cross-numbered core output data; wherein the even-numbered core input coefficients are the first N / 2 terms of the rearranged coefficients, and the odd-numbered core input coefficients are the last N / 2 terms of the rearranged coefficients;

[0029] The post-processing module is used to obtain zero-term output data, odd-term output data and even-term output data according to the even-numbered core output data, the odd-numbered core output data and the cross-numbered core output data, wherein the zero-term output data is equal to the first term of the even-numbered core output data, the even-numbered core output data is equal to the even-numbered core output data shifted left by one term and added to the odd-numbered core output data, and the odd-numbered core output data is equal to the cross-numbered core output data minus the even-numbered core output data and the odd-numbered core output data;

[0030] The merging and adding module is used to perform splicing and addition according to the zeroth output data, the odd-numbered output data, and the even-numbered output data to obtain a multiplication result.

[0031] In some embodiments, the preset model is a binary tree model, the root node value of the binary tree model is 0; the value of the left child node of the target node of the binary tree model is equal to the value of the target node, and the value of the right child node of the target node is equal to the value of the target node plus 2. a , where a is the depth of the target node in the binary tree model, and the target node is any node in the binary tree model;

[0032] in, represents one of the rearrangement coefficients, x index Represents one of the N coefficients of the input data; where i is the value of the kth layer from left to right in the binary tree model, and the corresponding index is 0, 1, 2..., N-1, where k = log2N.

[0033] In some embodiments, N=8, the pre-calculation module includes a first input selector, a second input selector, a third input selector, a fourth input selector, a first adder, a second adder, a first output selector, a second output selector, and a first register and a second register;

[0034] The inputs of the first input selector are the first and third rearrangement coefficients, respectively; the inputs of the second input selector are the second and fourth rearrangement coefficients, respectively; the inputs of the third input selector are the fifth and seventh rearrangement coefficients, respectively; and the inputs of the fourth input selector are the sixth and eighth rearrangement coefficients, respectively;

[0035] The output terminals of the first input selector and the third input selector are connected to the input terminal of the first adder, and the output terminal of the first adder is connected to the first output selector; the output terminal of the first adder is further connected to the multiplication module for outputting the third term in the cross-core input coefficient;

[0036] The output terminals of the second input selector and the fourth input selector are connected to the input terminal of the second adder, and the output terminal of the second adder is connected to the second output selector; the output terminal of the second adder is also connected to the multiplication module for outputting the second term of the cross-core input coefficient;

[0037] The inputs of the first output selector are the output of the first adder and the output of the first register in sequence, and the output end of the first output selector is connected to the input end of the first register;

[0038] The inputs of the second output selector are the output of the second adder and the output of the second register in sequence, and the output end of the second output selector is connected to the input end of the second register;

[0039] The output of the first register is also connected to the multiplication module for outputting the first term in the cross-core input coefficient;

[0040] The output end of the second register is also connected to the multiplication module for outputting the fourth term in the cross-core input coefficient.

[0041] In some embodiments, the multiplication module operates in series, and the multiplication module includes a fifth input selector, an N / 2-point karatsuba multiplication submodule;

[0042] The inputs of the fifth input selector are the even-numbered core input coefficient, the odd-numbered core input coefficient, and the cross-numbered core input coefficient in sequence;

[0043] In the first iteration, the fifth input selector outputs the even-core input coefficients to the N / 2-point Karatsuba multiplication submodule. The N / 2-point Karatsuba multiplication submodule performs calculations based on the even-core input coefficients to obtain even-core output data.

[0044] In the second iteration, the fifth input selector outputs the odd-core input coefficients to the N / 2-point Karatsuba multiplication submodule; the N / 2-point Karatsuba multiplication submodule performs calculations based on the odd-core input coefficients to obtain the odd-core output data.

[0045] In the third iteration cycle, the fifth input selector outputs the cross-core input coefficient to the N / 2-point karatsuba multiplication submodule; the N / 2-point karatsuba multiplication submodule performs calculations based on the cross-core input coefficient to obtain cross-core output data.

[0046] In some embodiments, the post-processing includes a sixth input selector, a seventh input selector, a third register, a fourth register, a shifter, a third output selector, a fourth output selector, a third adder, and a fourth adder; wherein,

[0047] An input terminal of the sixth input selector is connected in sequence to an output terminal of the N / 2-point karatsuba multiplication submodule and an output terminal of the third register;

[0048] An input terminal of the seventh input selector is connected in sequence to an output terminal of the N / 2-point karatsuba multiplication submodule and an output terminal of the fourth register;

[0049] The input terminal of the third register is connected to the output terminal of the sixth input selector; the output terminal of the third register is also connected to the input terminal of the shifter;

[0050] An input terminal of the fourth register is connected to an output terminal of the seventh input selector;

[0051] The shifter is used for shifting the received data to the left by one bit, and the output end of the shifter is connected to the input end of the third output selector;

[0052] An input end of the third output selector is connected to an output end of the shifter and an output end of the register in sequence, for outputting the even-numbered core output data to the third adder in a second iteration cycle;

[0053] An input end of the fourth output selector is connected in sequence to an output end of the fourth register and an output end of the N / 2-point karatsuba multiplication submodule, and the fourth output selector is used to output the odd-numbered core output data to the third adder in a second iteration cycle;

[0054] The third adder is used for outputting the even-numbered output data to the merging and adding module in the second iteration cycle;

[0055] The output terminal of the third adder is further connected to the input terminal of the fourth adder via an inverting circuit;

[0056] The input end of the fourth adder is also connected to the output end of the multiplication module, and the fourth adder is used to output the odd-numbered output data to the merging and adding module in the third iteration cycle;

[0057] The post-processing module is further configured to output the first item of the even-numbered core output data directly to the merge addition module in the first iteration cycle.

[0058] In some embodiments, the merge-add module includes a first splicing circuit, a carry-save adder, and a second splicing circuit;

[0059] The splicing circuit is used to sequentially splice the even-numbered output data to obtain spliced ​​even-numbered data, and to sequentially splice the odd-numbered output data after replacing the highest bit with zero to obtain spliced ​​odd-numbered data, and to sequentially splice the highest bit of the even-numbered output data and the highest bit of the odd-numbered output data to obtain spliced ​​remainder data;

[0060] The carry-save adder is used to add the concatenated even-numbered data, the concatenated odd-numbered data, and the concatenated remainder data to obtain an intermediate multiplication result;

[0061] The second splicing circuit is used to splice the intermediate multiplication result and the first w bits of the zeroth output data to obtain a multiplication result, where w is the bit width of each item of the input data.

[0062] The present application provides an integer multiplication device based on the Karatsuba algorithm, which is used to implement the multiplication operation of two input data represented in the form of N-term polynomials. The device includes a reordering module, a pre-calculation module, a multiplication module, a post-processing module, and a merging and adding module. The reordering module is used to reorder N coefficients to obtain reordered coefficients, thereby obtaining even-core input coefficients and odd-core input coefficients. The pre-calculation module obtains cross-core input coefficients based on the reordered coefficients. The multiplication module includes an N / 2-point Karatsuba multiplication submodule, which performs multiplication calculations based on the even-core input coefficients, the odd-core input coefficients, and the cross-core input coefficients to obtain even-core output data, odd-core output data, and cross-core output data. The post-processing module calculates the zeroth-term output data, the odd-term output data, and the even-term output data, which are then spliced ​​and added by the merging and adding module to obtain the multiplication result. The above-mentioned integer multiplication device can directly splice and add the output results of the multiplication modules to obtain the final multiplication result, saving hardware resources and shortening latency. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] Figure 1 A schematic structural diagram of an integer multiplication device based on the Karatsuba algorithm provided in an embodiment of the present application;

[0064] Figure 2 This is a schematic diagram of the circuit structure of the 2-point FCM architecture used in the embodiment of the present application;

[0065] Figure 3 An exemplary structural diagram of an integer multiplication device based on the Karatsuba algorithm provided in an embodiment of the present application;

[0066] Figure 4 A schematic diagram of the circuit structure of a pre-calculation module in an integer multiplication device based on the Karatsuba algorithm provided in an embodiment of the present application;

[0067] Figure 5 A circuit structure diagram of a multiplication module and a post-processing module in an integer multiplication device based on the Karatsuba algorithm provided in an embodiment of the present application;

[0068] Figure 6 A schematic diagram of the processing process of the merging and adding module in an integer multiplication device based on the Karatsuba algorithm provided in an embodiment of the present application;

[0069] Figure 7 A schematic diagram of the circuit structure of a carry-save adder in a merge-add module in an integer multiplication device based on the Karatsuba algorithm provided in an embodiment of the present application;

[0070] Figure 8 This is a schematic diagram of the circuit structure of the 3-point FCM architecture adopted in the embodiment of the present application. DETAILED DESCRIPTION

[0071] To facilitate the description of the technical solution of the application, some concepts involved in this application are first described below.

[0072] In order to solve the problem that the current integer multiplication device needs to merge the results of the previous recursion through shift operations and addition operations during each recursion, and the merging operation uses shift and addition operations, which consumes a lot of resources and has a long delay, the present application provides an integer multiplication device based on the Karatsuba algorithm through the following embodiments.

[0073] See also Figure 1 The integer multiplication device based on the Karatsuba algorithm provided in the embodiment of the present application is used to realize the multiplication of two input data, wherein the two input data are divided into N items. In the present application, the length of the two input data is L bits, one of the input data is represented by X, and the coefficients of the corresponding N items are represented by x0, x1, ..., x N-1 Indicates that the other input data is represented by Y, and the corresponding N coefficients are y0, y1, ..., y N-1 Indicates that each item has a width of w bits and the multiplication result is represented by Z.

[0074] See also Figure 1 The integer multiplication device includes: a reordering module, a pre-calculation module, a multiplication module, a post-processing module and an addition and merging module.

[0075] The reordering module is used to reorder the N coefficients of the input data based on a preset model to obtain reordered coefficients, and output them to the multiplication module and the pre-calculation module.

[0076] In some embodiments, N is a power of 2, and the input data is split into 4-term polynomial form, 8-term polynomial form, or more. In these embodiments, the preset model is a binary tree model, the root node value of the binary tree model is 0; the value of the left child node of the target node of the binary tree model is equal to the value of the target node, and the value of the right child node of the target node is equal to the value of the target node plus 2. a , where a is the depth of the target node in the binary tree model, and the target node is any node in the binary tree model. in, represents one of the rearrangement coefficients, x j Represents one of the N coefficients of the input data; wherein, i is the value of the kth layer from left to right in the binary tree model, and correspondingly, j is 0, 1, 2..., N-1, wherein k=log2N.

[0077] In one implementation, a depth-first recursive function based on a binary tree model can be used to reorder the N coefficients of the input data. The reordered coefficients are regular and highly scalable. The algorithm of the depth-first recursive function based on the binary tree model is as follows:

[0078]

[0079]

[0080] After reordering, when the input data is split into 4 items, the reordering coefficients are: When the input data is split into 8 items, the rearrangement coefficients are:

[0081] The pre-calculation module is used to perform pre-calculation based on the rearrangement coefficients to obtain cross-core input coefficients, and output the cross-core input coefficients to the multiplication module, wherein the number of items of the cross-core input coefficients is N / 2.

[0082] The multiplication module includes an N / 2-point karatsuba multiplication submodule, which is used to calculate based on the even-numbered core input coefficient to obtain even-numbered core output data, and to calculate based on the odd-numbered core input coefficient to obtain odd-numbered core output data, and to calculate based on the cross-numbered core input coefficient to obtain cross-numbered core output data; wherein the even-numbered core input coefficient is the first N / 2 terms of the rearrangement coefficient, and the odd-numbered core input coefficient is the last N / 2 terms of the rearrangement coefficient.

[0083] The post-processing module is used to obtain the zero-term output data, odd-term output data, and even-term output data according to the even-core output data, odd-core output data, and cross-core output data. Among them, the zero-term output data is equal to the first item in the even-core output data, the even-term output data is equal to the sum of the even-core output data shifted left by one item and the odd-core output data, and the odd-term output data is equal to the cross-core output data minus the even-core output data and the odd-core output data.

[0084] The merging addition module is used to splice and add according to the zero-term output data, odd-term output data, and even-term output data to obtain the multiplication result.

[0085] In some embodiments, the multiplication module includes a karatsuba multiplication sub-module of N / 2 points. In this application, the karatsuba multiplication sub-module adopts the FCM (Fast Convolution-like Multiplier) architecture.

[0086] See Figure 2 is a schematic structural diagram of a 2-point FCM architecture, that is, the input data is split into 2 items. Using the reordering module in the foregoing embodiments, according to the number of items N of the input data, the number of recursive levels is changed (a total of log2N recursive calls are required), so as to be applicable to input data of various sizes. Each recursive call will use 3 lower-level FCM architectures. In the order of recursive calls, the lower-level FCM architectures are respectively represented as even cores, cross cores, and odd cores, and the even output z 2i (0 < i < N) is the result of adding the even-core output data shifted left by one bit and the odd-core output data, and the odd output z 2i+1 (0 ≤ i < N) is the output data of the cross core minus the output data of the corresponding even core and odd core, and so on recursively until the 2-point FCM architecture. See Figure 3 is a 4-point FCM architecture, that is, the input data is split into 4 items.

[0087] As Figure 3 shown, the input data in the 4-point FCM architecture is the reordered coefficient obtained through the reordering module. Figure 3 The 4-point FCM architecture in includes three parallel 2-point FCM architectures. The first 2-point FCM architecture is called the even core in this application, the second 2-point FCM architecture is called the cross core in this application, and the third 2-point FCM architecture is called the odd core in this application. Among them, the even-core input coefficient is the first 2 of the reordered coefficients, the odd-core input coefficient is the last 2 of the reordered coefficients, and the cross-core input coefficients are obtained by cross-calculating the reordered coefficients through the pre-computation module, which are respectively and Calculations are performed separately to obtain even-numbered core output data, odd-numbered core output data, and cross-numbered core output data. The zeroth item output data, odd-numbered item output data, and even-numbered item output data are obtained through the addition and subtraction circuits included in the post-processing module.

[0088] In some embodiments, the multiplication modules operate in series, so that only one lower-level FCM architecture is required in the integer multiplication device. Figure 4 , gives an example of a circuit structure diagram of a pre-calculation module and the multiplication module when the multiplication module works in series (when N=8).

[0089] See also Figure 4 , is a schematic diagram of the circuit structure of the pre-calculation module when N = 8. The pre-calculation module includes a first input selector, a second input selector, a third input selector, a fourth input selector, a first adder, a second adder, a first output selector, a second output selector, and a first register and a second register.

[0090] The inputs of the first input selector are the first and third of the rearrangement coefficients, respectively; the inputs of the second input selector are the second and fourth of the rearrangement coefficients, respectively; the inputs of the third input selector are the fifth and seventh of the rearrangement coefficients, respectively; and the inputs of the fourth input selector are the sixth and eighth of the rearrangement coefficients, respectively.

[0091] The output ends of the first input selector and the third input selector are connected to the input end of the first adder, and the output end of the first adder is connected to the first output selector; the output end of the first adder is also connected to the multiplication module for outputting the third term in the cross-core input coefficient

[0092] The output ends of the second input selector and the fourth input selector are connected to the input end of the second adder, and the output end of the second adder is connected to the second output selector; the output end of the second adder is also connected to the multiplication module for outputting the second term in the cross-core input coefficient

[0093] The inputs of the first output selector are the output of the first adder and the output of the first register in sequence, and the output end of the first output selector is connected to the input end of the first register.

[0094] The inputs of the second output selector are the output of the second adder and the output of the second register in sequence, and the output end of the second output selector is connected to the input end of the second register.

[0095] The output of the first register is also connected to the multiplication module for outputting the first term of the cross-core input coefficient

[0096] The output of the second register is also connected to the multiplication module for outputting the fourth term in the cross-core input coefficient

[0097] In some embodiments, a pre-processing module is further included, and the pre-calculation module is a part of the pre-processing module. During the first iteration cycle, the pre-processing module is used to output the first 4 bits of the rearranged coefficient to the multiplication module. Exemplarily, the first 4 bits of the rearranged coefficient can be transmitted to the multiplication module through a controller and a direct circuit. During the second iteration cycle, the pre-processing module is used to output the last 4 bits of the rearranged coefficient to the multiplication module. The last 4 bits of the rearranged coefficient can be transmitted to the multiplication module through a controller and a direct circuit. During the third iteration cycle, the pre-calculation module in the pre-processing module outputs the calculation result to the multiplication module.

[0098] In these examples, see Figure 5 The multiplication module includes a fifth input selector, an N / 2-point karatsuba multiplication submodule (when N=8, it is a 4-point fast convolution multiplication module, that is, the entire Figure 3 It should be noted that when N=8, the N / 2-point karatsuba multiplication submodule is a 4-point FCN architecture, that is, Figure 3 When N=4, the N / 2-point karatsuba multiplication submodule is a 2-point FCM architecture, that is, Figure 2 .

[0099] The input of the fifth input selector is the even-numbered kernel input coefficients. Odd kernel input coefficients and the cross-kernel input coefficients

[0100] In the first iteration cycle, the fifth input selector outputs the even-numbered kernel input coefficient To the N / 2 point karatsuba multiplication submodule; the N / 2 point karatsuba multiplication submodule performs calculation according to the even core input coefficient to obtain even core output data.

[0101] In the second iteration cycle, the fifth input selector outputs the odd kernel input coefficient To the N / 2 point karatsuba multiplication submodule; the N / 2 point karatsuba multiplication submodule performs calculation according to the odd core input coefficient to obtain odd core output data.

[0102] In the third iteration cycle, the fifth input selector outputs the cross-core input coefficient To the N / 2 point karatsuba multiplication submodule; the N / 2 point karatsuba multiplication submodule performs calculation according to the cross-core input coefficient to obtain cross-core output data.

[0103] The post-processing module is used to obtain the zeroth output data z0, the odd output data z0 and the cross core output data according to the even core output data, the odd core output data and the cross core output data. 奇 And even-numbered output data z 偶 , wherein the zeroth output data z0 is equal to the first item in the even-numbered core output data, and the even-numbered output data z 偶 = equal to the sum of the even-numbered core output data shifted left by one and the odd-numbered core output data, and the odd-numbered output data z 奇 It is equal to the cross-core output data minus the even-core output data and the odd-core output data.

[0104] In these embodiments, the post-processing module includes a sixth input selector, a seventh input selector, a third register, a fourth register, a shifter, a third output selector, a fourth output selector, a third adder, and a fourth adder; wherein,

[0105] The input end of the sixth input selector is sequentially connected to the output end of the N / 2-point karatsuba multiplication submodule and the output end of the third register.

[0106] The input end of the seventh input selector is sequentially connected to the output end of the N / 2-point karatsuba multiplication submodule and the output end of the fourth register.

[0107] The input end of the third register is connected to the output end of the sixth input selector; the output end of the third register is also connected to the input end of the shifter.

[0108] An input terminal of the fourth register is connected to an output terminal of the seventh input selector.

[0109] The shifter is used to shift the received data one bit to the left, and the output end of the shifter is connected to the input end of the third output selector.

[0110] The input end of the third output selector is connected to the output end of the shifter and the output end of the register in sequence, and is used to output the even core output data to the third adder in a second iteration cycle.

[0111] The input end of the fourth output selector is connected to the output end of the fourth register and the output end of the N / 2-point karatsuba multiplication sub-module in sequence, and the fourth output selector is used to output the odd core output data to the third adder in the third iteration cycle.

[0112] The third adder is used to output the even-numbered output data z in the third iteration cycle. 偶 to the post-processing module.

[0113] The output end of the third adder is further connected to the input end of the fourth adder through an inversion circuit.

[0114] The input end of the fourth adder is also connected to the output end of the multiplication module, and the fourth adder is used to output the odd-numbered output data z in the third iteration cycle. 奇 to the post-processing module.

[0115] The post-processing module is further configured to directly output the first item z0 of the even-numbered core output data to the post-processing module in a first iteration cycle.

[0116] To control the selectors in the pre-calculation module, multiplication module, and post-processing module, one implementation introduces two signals: a 2-bit signal num and a single-bit signal s. The value of num starts at 0 and increases by one at each iteration, then returns to zero again after reaching 2, repeating the cycle. s is the sum of the lowest and highest bits of num, i.e., s = num[0] | num[1]. Figure 4 The control signal of all selectors in is s, Figure 5 The control signal of the selector in is num or s.

[0117] In these embodiments, adder reuse is achieved within the N / 2-point Karatsuba multiplication submodule and post-processing module, saving approximately half the number of adders. Three N / 4-point Karatsuba multiplication submodules are connected in parallel within the N / 2-point Karatsuba multiplication submodule, enabling compatibility with both serial and hybrid serial-parallel architectures. This allows for increased adder reuse at the input and output, reducing circuit area and thus meeting varying requirements for area and latency.

[0118] As can be seen from the recursive Karatsuba algorithm, each iteration process requires merging the results of the previous iteration through shift operations and addition operations. This architecture has a large delay and consumes a lot of resources. As the number of multiplication bits increases, the delay and resources will also increase significantly. In this application, a delayed merging method is adopted. The sub-multipliers are no longer merged, but the merging is completed in the merging addition module. Through the merging addition module, the results obtained by the multiplication module are split and reorganized, such as Figure 6 As shown, the even terms and odd terms (excluding the 2w-1th bit) output by the multiplication module are spliced ​​separately, and the 2w-1th bit of each term (except the 0th term) is spliced ​​as the remainder. The three spliced ​​data are added using a (2N-1)w-bit carry-save adder to obtain the final integer multiplication result.

[0119] In some embodiments, the merge-add module includes a first splicing circuit, a carry-save adder, and a second splicing circuit.

[0120] The splicing circuit is used to splice the even-numbered output data in sequence to obtain spliced ​​even-numbered data, and to replace the highest bit of the odd-numbered output data with zero and then splice them in sequence to obtain spliced ​​odd-numbered data, and to splice the highest bit of the even-numbered output data and the highest bit of the odd-numbered output data in sequence to obtain spliced ​​remainder data.

[0121] The carry-save adder is used to add the spliced ​​even-numbered data, the spliced ​​odd-numbered data, and the spliced ​​remainder data to obtain an intermediate multiplication result.

[0122] See also Figure 7 Figure 1 shows the structure of a carry-save adder in one implementation. FA is a full adder, with even-numbered inputs as E, odd-numbered inputs as O, and remainder inputs as R, where n = (2N-1) × w. Using a carry-save adder can shorten the critical path.

[0123] The second splicing circuit is used to splice the intermediate multiplication result and the first w bits of the zeroth output data to obtain the multiplication result, where w is the bit width of the input data. Figure 7 Output data c0, c1, ..., c n+1 The final multiplication result is obtained by concatenating the first w bits of z0.

[0124] In the aforementioned embodiment, the underlying core of the karatsuba multiplication submodule is a 2-point FCM architecture. In some embodiments, the underlying core of the karatsuba multiplication submodule may also adopt a 3-point FCM architecture, thereby supporting polynomials with a number of terms of 2. n ×3 integer multiplication operation. Using the integer multiplication device of the 3-point FCM architecture can reduce the computational complexity to 2 / 3 of the original. Figure 8 The schematic diagram of the circuit structure of the 3-point FCM architecture is shown in Figure 1. Correspondingly, the preset model in the reordering module is a ternary tree model.

[0125] In order to clearly illustrate an integer multiplication device based on the Karatsuba algorithm provided in an embodiment of the present application, the calculation process of the integer multiplication device is described below with reference to specific data.

[0126] Assume that the input data of the integer multiplication device is 128 bits, and zero is padded for data less than 128 bits. The input is divided into 8 items, each of which is 16 bits wide.

[0127] Enter two large hexadecimal numbers, namely:

[0128] X=1d 3b0c 3490840f 2944e824

[0129] Y=ffffffff

[0130] Input X and Y into the architecture and pass through the reordering module to obtain the reordered sequence (i.e., the reordering coefficient):

[0131] X_permute[0:7]=e824,3b0c,840f,0000,2944,001d,3490,0000

[0132] Y_permute[0:7]=ffff,0000,0000,0000,ffff,0000,0000,0000

[0133] The reordered results are fed into the pre-calculation module to calculate the input of the cross kernel of the 4-point FCM. Figure 4 The circuit shown yields the output:

[0134]

[0135] Thus we get the cross-kernel input coefficient:

[0136] X_cross[0:3]=11168,03b29,0b89f,00000;

[0137] Y_cross[0:3]=1fffe,00000,00000,00000;

[0138] Additionally, the even-numbered kernel input coefficients are:

[0139] X_even[0:3]=0e824,03b0c,0840f,00000;

[0140] Y_even[0:3]=0ffff,00000,00000,00000;

[0141] The odd kernel input coefficients are:

[0142] X_odd[0:3]=02944,0001d,03490,00000;

[0143] Y_odd[0:3]=0ffff,00000,00000,00000;

[0144] Input the even core input coefficients, odd core input coefficients, and cross core input coefficients into the 4-point FCM architecture, and the even core output data is:

[0145] Z even[0:6] =0e82317dc,0840e7bf1,03b0bc4f4,000000000,000000000,000000000,000000000;

[0146] The obtained odd core output data is:

[0147] Z odd[0:6] =02943d6bc,0348fcb70,0001cffe3,000000000,000000000,000000000,000000000;

[0148] The obtained cross-kernel output data is:

[0149] Z cross[0:6] =222cddd30,1713c8ec2,0765189ae,

[0150] 000000000,000000000,000000000,000000000;

[0151] After calling the FCM of 4 points three times, the output result is passed through an addition and subtraction circuit (post-processing module) to obtain the result of the post-processing module z 偶 , z 奇 and z0, specifically:

[0152] Z]0:14]=0e82317dc,11166ee98,0ad5252ad,0b89e4761,

[0153] 06f9b9064,03b28c4d7,0001cffe3,000000000,000000000,

[0154] 000000000,000000000,000000000,000000000,000000000,000000000;

[0155] By combining the addition modules, we get the final output:

[0156] C=1d3b0c34734902f4b46414d6bb17dc.

[0157] The above embodiment provides an integer multiplication device based on the Karatsuba algorithm, which is used to realize the multiplication operation of two input data represented in the form of N-term polynomials, including a reordering module, a pre-calculation module, a multiplication module, a post-processing module and a merging and adding module; the reordering module is used to reorder N-term coefficients to obtain rearrangement coefficients, and then obtain even-core input coefficients and odd-core input coefficients, and the pre-calculation module obtains cross-core input coefficients according to the rearrangement coefficients; the multiplication module includes an N / 2-point Karatsuba multiplication sub-module, which performs multiplication calculations according to the even-core input coefficients, odd-core input coefficients and cross-core input coefficients to obtain even-core output data, odd-core output data and cross-core output data, and calculates the zeroth-term output data, odd-term output data and even-term output data through the post-processing module, and then splices and adds them through the merging and adding module to obtain the multiplication result. Before performing a multiplication operation, the integer multiplication device uses a depth-first recursive function to reorder inputs, thereby reducing algorithm complexity. Based on the traditional recursive Karatsuba architecture, it is compatible with serial, parallel, and mixed serial-parallel architectures, and implements adder reuse in the input and output parts of the multiplication module, thereby reducing circuit area. Using a delayed merging method, the recursive process does not perform a merging operation, but instead splits and reorders the results output by the multiplication module, and merges them using a merging addition module to obtain the final result. Compared with the traditional recursive Karatsuba architecture that performs a merging operation in each iteration, this method saves hardware resources and shortens latency.

[0158] The embodiments of the present application can be described using a hardware description language (such as Verilog HDL) and implemented through a field programmable gate array (FPGA), a PLD (programmable logic device), or a logic circuit that implements dedicated logic operations.

[0159] The same and similar parts between the various embodiments of this specification can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

Claims

1. An integer multiplication device based on the Karatsuba algorithm, for realizing the multiplication of two input data, wherein: The two input data are respectively divided into N items, and the integer multiplication device includes: a reordering module, a pre-calculation module, a multiplication module, a post-processing module and an addition and merging module; The reordering module is used to reorder the N coefficients of the input data based on a preset model to obtain reordered coefficients, and output them to the multiplication module and the pre-calculation module; The pre-calculation module is used to perform pre-calculation based on the rearrangement coefficients to obtain cross-core input coefficients, and output the cross-core input coefficients to the multiplication module, wherein the number of items of the cross-core input coefficients is N / 2; The multiplication module includes an N / 2-point karatsuba multiplication submodule, the multiplication module is used to calculate according to the even-core input coefficient to obtain even-core output data, and to calculate according to the odd-core input coefficient to obtain odd-core output data, and to calculate according to the cross-core input coefficient to obtain cross-core output data; wherein the even-core input coefficient is the first N / 2 terms of the rearrangement coefficient, and the odd-core input coefficient is the last N / 2 terms of the rearrangement coefficient; The post-processing module is configured to obtain zeroth output data, odd output data, and even output data according to the even core output data, the odd core output data, and the cross core output data, wherein the zeroth output data is equal to the first item of the even core output data, the even output data is equal to the even core output data shifted left by one item and added to the odd core output data, and the odd output data is equal to the cross core output data minus the even core output data and the odd core output data; The addition and merging module is used to perform splicing and addition according to the zeroth output data, the odd-numbered output data, and the even-numbered output data to obtain a multiplication result.

2. The integer multiplication device according to claim 1, wherein: The preset model is a binary tree model, the root node value of the binary tree model is 0; the value of the left child node of the target node of the binary tree model is equal to the value of the target node, and the value of the right child node of the target node is equal to the value of the target node plus 2. a , where a is the depth of the target node in the binary tree model, and the target node is any node in the binary tree model; in, represents one of the rearrangement coefficients, x index Represents one of the N coefficients of the input data; wherein, i is the value of the kth layer from left to right in the binary tree model, and correspondingly, index is 0, 1, 2..., N-1, wherein k=log2N.

3. The integer multiplication device according to claim 1, wherein: N=8, the pre-calculation module includes a first input selector, a second input selector, a third input selector, a fourth input selector, a first adder, a second adder, a first output selector, a second output selector, and a first register and a second register; The inputs of the first input selector are the first and third of the rearrangement coefficients, respectively; the inputs of the second input selector are the second and fourth of the rearrangement coefficients, respectively; the inputs of the third input selector are the fifth and seventh of the rearrangement coefficients, respectively; and the inputs of the fourth input selector are the sixth and eighth of the rearrangement coefficients, respectively; The output terminals of the first input selector and the third input selector are connected to the input terminal of the first adder, and the output terminal of the first adder is connected to the first output selector; The output terminal of the first adder is also connected to the multiplication module, for outputting the third term in the cross-core input coefficient; The output terminals of the second input selector and the fourth input selector are connected to the input terminal of the second adder, and the output terminal of the second adder is connected to the second output selector; The output terminal of the second adder is also connected to the multiplication module, for outputting the second term of the cross-core input coefficient; The inputs of the first output selector are the output of the first adder and the output of the first register in sequence, and the output end of the first output selector is connected to the input end of the first register; The inputs of the second output selector are the output of the second adder and the output of the second register in sequence, and the output end of the second output selector is connected to the input end of the second register; The output end of the first register is also connected to the multiplication module, for outputting the first term of the cross-core input coefficient; The output end of the second register is also connected to the multiplication module for outputting the fourth term in the cross-core input coefficient.

4. The integer multiplication device according to claim 1, wherein: The multiplication module works in series, and the multiplication module includes a fifth input selector and an N / 2-point karatsuba multiplication submodule; The inputs of the fifth input selector are the even-numbered core input coefficient, the odd-numbered core input coefficient and the cross-core input coefficient in sequence; In a first iteration cycle, the fifth input selector outputs the even-core input coefficient to the N / 2-point Karatsuba multiplication submodule; the N / 2-point Karatsuba multiplication submodule performs calculations based on the even-core input coefficient to obtain even-core output data; In a second iteration cycle, the fifth input selector outputs the odd core input coefficient to the N / 2-point Karatsuba multiplication submodule; the N / 2-point Karatsuba multiplication submodule performs calculations based on the odd core input coefficient to obtain odd core output data; In the third iteration cycle, the fifth input selector outputs the cross-core input coefficient to the N / 2-point karatsuba multiplication submodule; the N / 2-point karatsuba multiplication submodule performs calculations based on the cross-core input coefficient to obtain cross-core output data.

5. The integer multiplication device according to claim 4, characterized in that The post-processing module includes a sixth input selector, a seventh input selector, a third register, a fourth register, a shifter, a third output selector, a fourth output selector, a third adder, and a fourth adder; wherein, The input end of the sixth input selector is connected in sequence to the output end of the N / 2-point karatsuba multiplication submodule and the output end of the third register; The input end of the seventh input selector is connected in sequence to the output end of the N / 2-point karatsuba multiplication submodule and the output end of the fourth register; The input end of the third register is connected to the output end of the sixth input selector; the output end of the third register is also connected to the input end of the shifter; An input terminal of the fourth register is connected to an output terminal of the seventh input selector; The shifter is used to shift the received data one bit to the left, and the output end of the shifter is connected to the input end of the third output selector; The input end of the third output selector is connected to the output end of the shifter and the output end of the register in sequence, for outputting the even-numbered core output data to the third adder in a second iteration cycle; The input end of the fourth output selector is connected in sequence to the output end of the fourth register and the output end of the N / 2-point karatsuba multiplication submodule, and the fourth output selector is used to output the odd-numbered core output data to the third adder in a third iteration cycle; The third adder is used for outputting the even-numbered output data to the addition and merging module in the third iteration cycle; The output end of the third adder is further connected to the input end of the fourth adder through an inverting circuit; The input end of the fourth adder is also connected to the output end of the multiplication module, and the fourth adder is used to output the odd-numbered output data to the addition and merging module in a third iteration cycle; The post-processing module is further configured to directly output the first item of the even-numbered core output data to the addition and merging module in a first iteration cycle.

6. The integer multiplication device according to claim 1, characterized in that: The addition and merging module includes a first splicing circuit, a carry-save adder, and a second splicing circuit; The splicing circuit is used to sequentially splice the even-numbered output data to obtain spliced ​​even-numbered data, and to sequentially splice the odd-numbered output data after replacing the highest bit with zero to obtain spliced ​​odd-numbered data, and to sequentially splice the highest bit of the even-numbered output data and the highest bit of the odd-numbered output data to obtain spliced ​​remainder data; The carry-save adder is used to add the spliced ​​even-numbered data, the spliced ​​odd-numbered data, and the spliced ​​remainder data to obtain an intermediate multiplication result; The second splicing circuit is used to splice the intermediate multiplication result and the first w bits of the zeroth output data to obtain the multiplication result, where w is the bit width of each item of the input data.

Images