A method for testing memory eye diagram, a hardware debugging device and a storage medium

Abstract

An embodiment of the present application provides a method for testing a memory eye diagram, a hardware debugging device, and a storage medium. The method includes: responding to an access instruction from a server under test to the hardware debugging device, obtaining the network segment information of the hardware debugging device through a network module, allocating the network segment information of the hardware debugging device to the server under test, and performing network interconnection between the server under test and the hardware debugging device; responding to a selection instruction for a memory eye diagram test item, and performing a memory eye diagram test on the server under test after network interconnection through a test module; obtaining the data identifiers of the server under test and the memory eye diagram test item through a storage module; generating a storage path for the server under test according to the data identifier and the mapping relationship through the storage module, and storing the memory eye diagram test result based on the generated storage path, reducing the setup of the test environment, and also improving the operability of the memory eye diagram test based on direct response operations, and enhancing the test efficiency.

Description

Technical Field

[0001] The present application relates to the field of computer technologies, and in particular, to a method for testing a memory eye diagram, a hardware debugging device, and a corresponding computer storage medium. Background Art

[0002] Generally, during the server development stage and when introducing new memory in a project, memory testing will be carried out. One of the memory tests can be a memory eye diagram test, which is mainly used to test the signal integrity between the memory and the CPU (Central Processing Unit). It exists as an important item in memory testing.

[0003] However, in the related technologies of memory eye diagram testing, the existing testing devices are difficult to test, making it difficult to set up the testing environment and the testing steps are rather cumbersome, greatly affecting the testing efficiency. Summary of the Invention

[0004] In view of the above problems, embodiments of the present application are proposed to provide a method for testing a memory eye diagram, a hardware debugging device, and a corresponding computer storage medium that overcome the above problems or at least partially solve the above problems.

[0005] Embodiments of the present application disclose a method for testing a memory eye diagram, which relates to a hardware debugging device. The hardware debugging device is used to perform a memory eye diagram test on a server to be tested, and includes a network module, a test module, and a storage module. The method includes:

[0006] Responding to an access instruction from the server to be tested to the hardware debugging device, obtaining the network segment information of the hardware debugging device through the network module, allocating the network segment information of the hardware debugging device to the server to be tested, and performing network interconnection between the server to be tested and the hardware debugging device;

[0007] Responding to a selection instruction for a memory eye diagram test item, performing a memory eye diagram test on the server to be tested after network interconnection through the test module;

[0008] Obtaining data identifiers of the server to be tested and the memory eye diagram test item through the storage module. The data identifier has a pre-established mapping relationship with the storage location of the hardware debugging device;

[0009] Generating a storage path for the server to be tested according to the data identifier and the mapping relationship through the storage module, and storing the memory eye diagram test result based on the generated storage path.

[0010] Optionally, the network module is provided with a static gateway address and / or a dynamic gateway address; obtaining the network segment information of the hardware debugging device through the network module and allocating the network segment information of the hardware debugging device to the server to be tested includes:

[0011] When the network module is set with a static gateway address, in response to a gateway switching instruction for the static gateway address and / or dynamic gateway address set in the network module, obtain the dynamic gateway network segment information of the hardware debugging device through the network module, and allocate the dynamic gateway network segment information of the hardware debugging device to the server under test.

[0012] Optionally, the network module is set with a static gateway address and / or a dynamic gateway address; obtaining the network segment information of the hardware debugging device through the network module and allocating the network segment information of the hardware debugging device to the server under test includes:

[0013] When the network module is set with a dynamic gateway address, in response to a gateway switching instruction for the static gateway address and / or dynamic gateway address set in the network module, obtain the static gateway network segment information of the hardware debugging device through the network module, and allocate the static gateway network segment information of the hardware debugging device to the server under test.

[0014] Optionally, the test module tests the server under test for network interconnection according to the memory eye diagram test item to obtain a memory eye diagram test result, and further includes:

[0015] During the process of performing a memory eye diagram test on the server under test after network interconnection, display the current real-time test information and test exception prompt on the display screen of the hardware debugging device through the test module; wherein, the real-time test information includes any one or more of the remaining test time, test speed, and test progress, and the test exception prompt is used to inform the hardware debugging device of module exceptions during the process of performing a memory eye diagram test on the server under test.

[0016] Optionally, the hardware debugging device further includes a debugging module. After responding to the access instruction of the server under test to the hardware debugging device, it further includes:

[0017] In response to the power-on / off instruction of the hardware debugging device, detect whether the connected server under test presents corresponding operations to the power-on / off instruction through the debugging module to obtain a test environment setup result; the test environment setup result is used to inform the hardware debugging device whether the test environment requirements for the server under test are met during the test environment setup.

[0018] Optionally, the hardware debugging device further includes an expansion module. When the test module performs a memory eye diagram test on the server under test after network interconnection, it further includes:

[0019] Obtain the test log obtained by the test module when performing a memory eye diagram test on the server under test after network interconnection through the expansion module, and perform log analysis on the test log to obtain a memory eye diagram test result.

[0020] In some embodiments of the present application, the present application also discloses a hardware debugging device. When the hardware debugging device is executed, it implements any one of the memory eye diagram test methods. The hardware debugging device is used to perform a memory eye diagram test on a server under test, and includes a network module, a test module, and a storage module;

[0021] Among them, the network module is used to respond to the access instruction of the server under test to the hardware debugging device, obtain the network segment information of the hardware debugging device, allocate the network segment information of the hardware debugging device to the server under test, and network-connect the server under test with the hardware debugging device;

[0022] The test module is used to respond to the selection instruction of the memory eye diagram test item and perform a memory eye diagram test on the server under test after network connection;

[0023] The storage module is used to obtain the data identifiers of the server under test and the memory eye diagram test item, generate a storage path for the server under test according to the data identifier and the mapping relationship, and store the memory eye diagram test result based on the generated storage path.

[0024] Optionally, the hardware debugging device further includes an extension module. The extension module is used to obtain the test log obtained by the test module performing a memory eye diagram test on the server under test after network connection, and perform log analysis on the test log to obtain the memory eye diagram test result.

[0025] Optionally, the hardware debugging device further includes a debugging module. The debugging module is used to respond to the power-on and power-off instructions of the hardware debugging device, detect whether the server under test connected presents the corresponding operations to the power-on and power-off instructions, and obtain the test environment setup result; the test environment setup result is used to inform the hardware debugging device whether the test environment requirements for the server under test are met during the test environment setup.

[0026] In some embodiments of the present application, the present application embodiments also disclose a computer-readable storage medium. A computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, it implements any one of the memory eye diagram test methods.

[0027] The embodiments of the present application have the following advantages:

[0028] In an embodiment of the present application, the hardware debugging device for performing a memory eye diagram test on a server to be tested may itself include a network module, a test module, and a storage module. At this time, the network module can respond to the access instruction of the server to be tested to the hardware debugging device, allocate the network segment information of the hardware debugging device to the server to be tested to perform network interconnection between the server to be tested and the hardware debugging device. Then, the test module can respond to the selection instruction for the memory eye diagram test item, perform a memory eye diagram test on the server to be tested after network interconnection, and the storage module can generate a storage path for the server to be tested according to the data identifier and the mapping relationship, and store the memory eye diagram test result based on the generated storage path. That is, based on the functional modules related to test environment setup that the hardware debugging device itself has, automatic allocation of the same network segment can be achieved when the server to be tested is accessed, reducing the connection to the external network and network configuration settings required for testing, and canceling the control machine in the test environment, reducing the environment setup time. Moreover, based on the direct response operation of the hardware debugging device, the operability of the memory eye diagram test can be improved, and the test efficiency can be enhanced. Further, the memory eye diagram test result of the server to be tested can be stored based on the specified storage path, facilitating the management of the server to be tested, and thus further enhancing the test efficiency. Description of the Drawings

[0029] Figure 1 is a schematic diagram of the implementation of the memory eye diagram test in the related art;

[0030] Figure 2 is a schematic framework diagram of the hardware debugging device provided in an embodiment of the present application;

[0031] Figure 3 is a flowchart of the steps of an embodiment of the memory eye diagram test method of the present application;

[0032] Figure 4 is a block diagram of the structure of an embodiment of the memory eye diagram test device of the present application;

[0033] Figure 5 is a schematic diagram of the non-volatile computer-readable storage medium for implementing the network card stability test method provided in an embodiment of the present application. Detailed Embodiments

[0034] To make the above objects, features, and advantages of the present application more obvious and understandable, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0035] Memory eye diagram testing exists as an important item in memory testing and can mainly be used to test the signal integrity between the memory and the CPU. Among them, the eye diagram refers to the graph displayed by accumulating a series of digital signals on an oscilloscope. It contains rich information. Usually, the effects of inter-symbol interference and noise can be observed from the eye diagram, reflecting the overall characteristics of the digital signal, thereby estimating the quality of the system. It is the core of signal integrity analysis for high-speed interconnection systems.

[0036] Referring to Figure 1 , the implementation schematic diagram of memory eye diagram testing in the related art is shown. The device for performing memory eye diagram testing on the server under test 111 (System Under Test, abbreviated as SUT) is the HDT device 110 (Hardware Debug Tool, hardware debugging device). At this time, during the test, not only the HDT device needs to be configured, but also the server under test needs to add a cold reset interface for test configuration. In addition, since the HDT device 110 cannot perform network connection, a server also needs to be configured at this time to achieve the external network connection between the HDT device 110 and the server under test 111. The configured server can also be used as the control machine 112 or the Test Management Station (abbreviated as TMS). Install the HDT control software and the memory eye diagram testing software under the system so that the control machine 112 can perform memory eye diagram testing on the server under test 111 when executing the software.

[0037] In the specific implementation, since it is necessary to access the official website corresponding to the HDT device during the memory eye diagram testing using the HDT device, a notebook can be connected to the external network at this time, and then through network sharing, both the control machine and the server under test can access the external network. And it is required to ensure that the network ports of the HDT device, the network card of the server under test with memory, the network card of the control machine, and the network port of the notebook connected to the external network can communicate with each other during the test. To achieve network interconnection between various devices, a switch needs to be used.

[0038] In the process of memory eye diagram test, the HDT device also needs to use the JTAG (Joint Test Action Group) interface of the mainboard, that is, it needs to collect test data by connecting the mainboard JTAG to the HDT device. And because the HDT control software and the test software related to the memory eye diagram test are installed on the control machine 112, in the process of testing, the memeye test software (Memeye is a lightweight NodeJS process monitoring tool) installed on the control machine can select test items and test machines, which is convenient for viewing the test process and analyzing the test results. Among them, the test results are saved in the specified path of the control machine. After the HDT software executed by the control machine and the software related to the memory eye diagram test are tested, the memory eye diagram test results for the tested service segment need to be collected from the control machine, and in the process of testing the built test environment, it is necessary to test whether the remote power on and off instructions sent by HDT are effective.

[0039] From the above, it can be seen that in the method of memory eye diagram testing in the related art, it is necessary not only to configure the external network, but also to configure the network of the test machine, control machine and HDT equipment to realize the network interconnection between various devices. Moreover, since it is necessary to build the test environment based on the aforementioned equipment that needs to be configured, it is necessary to repeatedly check the problems in the environment building process, which may easily lead to the problem that problems in the test are not easily located, and the test operation is difficult due to the need to build the test environment, which places high professional requirements on professionals.

[0040] One of the core ideas of the embodiments of the present application is to modularize the functions implemented by the equipment related to the test environment construction, and integrate the modular related modules into the HDT equipment. Figure 1 The HDT device shown is improved to realize the automatic allocation of the same network segment when the server under test is connected based on the functional modules related to the test environment construction possessed by the hardware debugging device itself, thereby reducing the environment such as connecting to the external network and configuring the network required for the test, and canceling the control machine in the test environment, reducing the time for setting up the environment, and can also improve the operability of the memory eye diagram test and improve the test efficiency based on the direct response operation of the hardware debugging device. And because the functional modules implemented by the equipment related to the test environment construction are all integrated in the HDT device, there is no test environment construction based on the required configuration of the aforementioned equipment, so there is no need to repeatedly troubleshoot the problems in the environment construction process, and solve the problem of unclear positioning of problems in the test. Furthermore, the memory eye diagram test results of the server under test can also be stored based on the specified storage path, which is convenient for the management of the server under test, thereby improving the test efficiency.

[0041] Reference Figure 2, showing a schematic framework diagram of the hardware debugging device provided by an embodiment of the present application. The hardware debugging device 21 is used for memory eye diagram testing. This hardware debugging device 21 can mainly be manifested as an HDT device 21 obtained by improving the HDT device 110 as shown in Figure 1 . The improvement made to the HDT device is specifically manifested as modularizing the functions implemented by the devices related to test environment setup and integrating the modularized related modules into the HDT device. Based on the functional modules of the improved HDT device itself, it is possible to avoid configuring other devices for test environment setup. While improving the test efficiency, it can also solve the problem of unclear problem positioning in testing caused by repeatedly troubleshooting problems during environment setup.

[0042] Specifically, the improved HDT device 21 may include a network module 210, a debugging module 211, a testing module 212, a storage module 213, and an expansion module 214.

[0043] Among them, the network module 210 is mainly used to ensure that the improved HDT device 21 itself can be connected to the external network through wired or wireless means. And when the server under test is connected to the HDT device, it can automatically assign an IP in the same network segment to the server under test, realizing network interconnection between the server under test and the hardware debugging device while ensuring that the HDT device 21 has the function of accessing the external network. Specifically, it can be manifested as responding to the access instruction of the server under test to the hardware debugging device, obtaining the network segment information of the hardware debugging device, and then allocating the network segment information of the hardware debugging device to the server under test to interconnect the server under test and the hardware debugging device.

[0044] The debugging module 211 can mainly be used to determine in advance whether the test environment requirements are met to locate problems in advance. It is mainly responsible for responding to the power-on and power-off instructions of the hardware debugging device, detecting whether the server under test connected presents corresponding operations to the power-on and power-off instructions, and obtaining the test environment setup result. At this time, the obtained test environment setup result can be used to inform the hardware debugging device whether it meets the test environment requirements for the server under test during test environment setup.

[0045] The test module 212 is mainly responsible for performing a memory eye diagram test on the server under test. Specifically, it responds to the selection instruction for the memory eye diagram test item, performs a memory eye diagram test on the server under test after network interconnection, and obtains relevant test logs. During the process of performing a memory eye diagram test on the server under test after network interconnection, it can also be responsible for displaying the current real-time test information and test exception prompts on the display screen of the hardware debugging device. Among them, the displayed real-time test information can specifically include any one or more of the remaining test time, test speed, and test progress, and the displayed test exception prompts are mainly used to inform the hardware debugging device of module exceptions during the process of performing a memory eye diagram test on the server under test.

[0046] The storage module 213 is mainly responsible for storing the obtained test logs and / or memory eye diagram test results, ensuring the data storage function of the HDT device 21, so that the system can be normally installed in the HDT device and the test logs can also be saved in the HDT device 21. When storing, the storage module 213 can specifically obtain the data identifiers of the server under test and the memory eye diagram test item. There is a pre-established mapping relationship between the data identifier and the storage location of the hardware debugging device. At this time, the storage path for the server under test can be generated according to the data identifier and the mapping relationship, and the memory eye diagram test results are stored based on the generated storage path, realizing the storage of test logs or test results in the specified path, facilitating the management of the server under test, and thus improving the test efficiency. In addition, the storage module 213 can also reserve a USB interface so that the test logs can be copied through a USB flash drive.

[0047] The expansion module 214 is mainly responsible for providing the HDT device 21 with the ability to autonomously analyze test logs and process test data. That is, at this time, the HDT device 21 can obtain the test logs obtained by the test module for performing a memory eye diagram test on the server under test after network interconnection through the expansion module 214, and perform log analysis on the test logs to obtain the memory eye diagram test results, so as to determine whether the test passes based on the memory eye diagram test results. In addition, the expansion module 214 can also reserve a VGA (Video Graphics Array) interface so that when there is an externally inserted system disk, the system to enter after power-on can be selected based on the reserved VGA interface.

[0048] In the embodiment of the present application, the functions implemented by the devices related to test environment setup can be modularized, and the modularized related modules can be integrated into the HDT device, such as Figure 1Improve the HDT device shown, and implement the function modules related to the test environment setup that the hardware debugging device itself has. When the server under test is connected, automatically allocate the same network segment, reduce the connection to the external network and network configuration required for testing, and cancel the control machine in the test environment, reduce the time for environment setup, and also improve the operability of the memory eye diagram test and the test efficiency based on the direct response operation of the hardware debugging device.

[0049] Refer to Figure 3 , which shows the step flowchart of an embodiment of the memory eye diagram test method of this application, and involves the hardware debugging device for memory eye diagram test as shown in Figure 2 , and specifically may include the following steps:

[0050] Step 301, in response to the access instruction of the server under test to the hardware debugging device, obtain the network segment information of the hardware debugging device through the network module, allocate the network segment information of the hardware debugging device to the server under test, and interconnect the server under test and the hardware debugging device through the network;

[0051] In the memory eye diagram test method in the related art, the HDT device used not only needs to configure the external network, configure the networks of the test machine, control machine and HDT device to achieve network interconnection between various devices, but also because it needs to build a test environment based on the aforementioned devices that need to be configured, it is necessary to repeatedly check problems in the environment setup process, which easily leads to the problem that it is not clear to locate problems that occur during testing, and because it is necessary to build a test environment, it causes difficulties in test operations and high professional requirements for professionals.

[0052] In the embodiment of this application, mainly improve the HDT device used in the related art, which is manifested as modularizing the functions realized by the devices related to the test environment setup, and integrating the modularized related modules in the HDT device, that is, integrating the test execution process, error reporting mechanism, and test log storage in the HDT device, so as to avoid configuring other devices for building a test environment based on the function modules of the improved HDT device itself, while improving the test efficiency, it can also solve the problem that it is not clear to locate problems that occur during testing due to the need to repeatedly check problems in the environment setup process.

[0053] Specifically, a network module can be added to the HDT device to provide a wired or wireless way for the HDT device used in the related art to connect to the external network, and when the server under test is connected to the HDT device, the same network segment IP can be automatically allocated to the server under test, so as to ensure that the HDT device has the function of accessing the external network while realizing the network interconnection between the server under test and the hardware debugging device.

[0054] In practical applications, when the HDT device responds to the access instruction of the server under test to the hardware debugging device, that is, when it detects the access of the server under test to the HDT device, it can obtain the network segment information of the hardware debugging device through its own network module, allocate the network segment information of the hardware debugging device to the server under test, implement the setting of automatic network interconnection, and perform network interconnection between the server under test and the hardware debugging device.

[0055] Among them, the network module is set with a static gateway address (i.e., static IP) and / or a dynamic gateway address (dynamic IP). The setting of the static IP can be mainly manifested as the IP distribution of the HDT device based on the switch. The setting of the dynamic IP can be mainly manifested as when the network module reserves a network interface for the HDT device, configuring the reserved network interface as the DHPC (Dynamic Host Configuration Protocol) mode.

[0056] Specifically, a gateway switching instruction for the static gateway address and / or the dynamic gateway address can be set on the HDT device. At this time, in response to the gateway switching instruction for the static gateway address and / or the dynamic gateway address set in the network module, the static gateway network segment information and / or the dynamic gateway network segment information of the hardware debugging device can be obtained through the network module, and the static gateway network segment information and / or the dynamic gateway network segment information of the hardware debugging device can be allocated to the server under test.

[0057] In one case, when the network module is set with a static gateway address, when the HDT device responds to the gateway switching instruction for the static gateway address and / or the dynamic gateway address set in the network module, it can obtain the dynamic gateway network segment information of the hardware debugging device through the network module and allocate the dynamic gateway network segment information of the hardware debugging device to the server under test.

[0058] In another case, when the network module is set with a dynamic gateway address, when the HDT device responds to the gateway switching instruction for the static gateway address and / or the dynamic gateway address set in the network module, it can obtain the static gateway network segment information of the hardware debugging device through the network module and allocate the static gateway network segment information of the hardware debugging device to the server under test.

[0059] Based on the network interface (abbreviation: network port) reserved by the network module in the HDT device, the server under test can access the external network.

[0060] In some embodiments of the present application, the improved HDT device is also characterized by adding a debugging module to the HDT device to achieve an early judgment on whether the test environment requirements are met, so as to locate problems in advance. That is, the debugging module can test the test environment built for the HDT device. Specifically, it can respond to the power-on and power-off instructions of the hardware debugging device, and detect whether the connected server under test presents corresponding operations to the power-on and power-off instructions to obtain the test environment setup result. At this time, the obtained test environment setup result can be used to inform the hardware debugging device whether the test environment requirements for the server under test are met during the test environment setup.

[0061] In practical applications, the added debugging module in the HDT device can be implemented through the reserved display screen and debugging keys in the HDT device. The reserved keys can be set in the form of a touch screen. During the test, the BMC (Baseboard Management Controller, which is the server remote management controller and the baseboard management controller) of the server under test can be connected to the HDT device based on a dedicated interface, and then basic power-on and power-off instructions are sent through the keys to observe whether the server under test can operate normally according to the key instructions, that is, to detect whether the connected server under test presents corresponding operations to the power-on and power-off instructions. To streamline the hardware resources and cancel the method of obtaining signals from the server motherboard to achieve server power-on and power-off.

[0062] Step 302: Respond to the selection instruction for the memory eye diagram test item, and use the test module to perform a memory eye diagram test on the server under test after network interconnection.

[0063] After network interconnection of the server under test and the hardware debugging device based on automatic allocation according to network segment information, and ensuring that the hardware debugging device meets the test environment requirements for the server under test during the test environment setup, that is, in the case of excluding the abnormal error of test environment setup, use the HDT device to perform a memory eye diagram test on the server under test.

[0064] During the memory eye diagram test, it is mainly implemented through the added test module in the HDT device. In practical applications, mainly Figure 1 Cancel the control machine used to execute the HDT software and the software related to the memory eye diagram test, and endow the relevant functions of the software to be run in the form of a test module in the improved HDT device.

[0065] Then, for the test module, it can achieve the ability to import test software into the HDT device in advance, so as to be able to perform a memory eye diagram test on the server under test after network interconnection in the configured test environment.

[0066] Specifically, the HDT device can respond to a selection instruction for a memory eye diagram test item, and then perform a memory eye diagram test on the server under test after network interconnection through a test module, which is manifested as directly selecting the test item and performing the test.

[0067] In some embodiments of the present application, during the process of performing a memory eye diagram test on the server under test after network interconnection, the test module can also display the current real-time test information and test exception prompts on the display screen of the hardware debugging device, and display the specific storage path where the test log is stored in the HDT device. Among them, the displayed real-time test information can include any one or more of the remaining test time, test speed, and test progress, and the displayed test exception prompt can be used to inform the hardware debugging device of module exceptions during the process of performing a memory eye diagram test on the server under test.

[0068] In specific implementation, the test module is only responsible for performing a memory eye diagram test on the server under test after network interconnection to obtain relevant test logs. In order to obtain the memory eye diagram test results, it is necessary to perform log analysis on the test logs obtained by the test module through an extended module added in the HDT device.

[0069] Step 303, obtain the data identifiers of the server under test and the memory eye diagram test item through the storage module;

[0070] After performing log analysis on the test logs obtained by the test module through the extended module to obtain the memory eye diagram test results, the memory eye diagram test results can be stored.

[0071] Specifically, a storage module can be added to the HDT device. The storage module is mainly responsible for storing the obtained test logs and / or memory eye diagram test results, which can ensure the data storage function of the HDT device, enabling the system to be normally installed in the HDT device and the test logs to be saved in the HDT device.

[0072] In practical applications, the storage module can also store the memory eye diagram test results of the server under test based on the specified storage path, which is convenient for the management of the server under test, thereby improving the test efficiency. The storage performed according to the specified storage path, since there is a pre-established mapping relationship between the data identifier and the storage location of the hardware debugging device, can be manifested as obtaining the data identifiers of the server under test and the memory eye diagram test item to determine the storage location with a mapping relationship.

[0073] Step 304, generate a storage path for the server under test according to the data identifier and the mapping relationship through the storage module, and store the memory eye diagram test results based on the generated storage path.

[0074] After determining the storage location with a mapping relationship, the storage module can specifically generate a storage path for the server under test based on the data identifier and the mapping relationship, i.e., the determined storage location, and store the memory eye diagram test result in the storage module, and determine whether the test passes based on the memory eye diagram test result.

[0075] Exemplarily, assume that the data identifier of the server under test is fuwuqi1, and the data identifier of the memory eye diagram test item it performs is 0. At this time, the data identifier can be formed in the form of "fuwuqi1 + 0", and this data identifier form corresponds to the storage location s0. Then, at this time, a corresponding storage path can be generated based on the storage location s0. Assume that its path is " / / fuwuqi1 + 0, s0", and store the memory eye diagram test log and / or memory eye diagram test result for fuwuqi1 in " / / fuwuqi1 + 0, s0", which is convenient for subsequent management of the server under test, thereby improving the test efficiency.

[0076] In a preferred embodiment of the present application, the storage module can also reserve a USB interface so that the test log can be copied through a USB flash drive to obtain the stored memory eye diagram test result. After the memory eye diagram test result under a certain storage path is exported, in order to ensure the storage space of the HDT device, the memory eye diagram test result stored under this storage path can be automatically deleted, or after the memory eye diagram test result is exported, the memory eye diagram test result stored under the corresponding storage path can be formatted at a preset time interval. The embodiments of the present application do not limit this.

[0077] In the embodiment of the present application, the hardware debugging device for performing a memory eye diagram test on the server to be tested may itself include a network module, a test module, and a storage module. At this time, the network module can respond to the access instruction of the server to be tested to the hardware debugging device, allocate the network segment information of the hardware debugging device to the server to be tested to perform network interconnection between the server to be tested and the hardware debugging device. Then, the test module can respond to the selection instruction for the memory eye diagram test item, perform a memory eye diagram test on the server to be tested after network interconnection, and the storage module can generate a storage path for the server to be tested according to the data identifier and the mapping relationship, and store the memory eye diagram test result based on the generated storage path. That is, based on the functional modules related to the test environment setup possessed by the hardware debugging device itself, automatic allocation of the same network segment can be realized when the server to be tested is accessed, reducing the connection to the external network and network configuration and other environments that need to be set during the test, and canceling the control machine in the test environment, reducing the environment setup time. Moreover, based on the direct response operation on the hardware debugging device, the operability of the memory eye diagram test can be improved, and the test efficiency can be enhanced. Further, the memory eye diagram test result of the server to be tested can also be stored based on the specified storage path, facilitating the management of the server to be tested, and further improving the test efficiency.

[0078] It should be noted that for the method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should know that the embodiments of the present application are not limited by the described action sequence, because according to the embodiments of the present application, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily essential for the embodiments of the present application.

[0079] Referring to Figure 4 , a structural block diagram of an embodiment of a memory eye diagram test device of the present application is shown, which relates to a hardware debugging device. Such as Figure 2 The shown hardware debugging device is used for performing a memory eye diagram test on the server to be tested, and includes a network module, a test module, and a storage module. Specifically, it may include the following modules:

[0080] The network interconnection module 401, located in the network module, is used to respond to the access instruction of the server to be tested to the hardware debugging device, obtain the network segment information of the hardware debugging device, allocate the network segment information of the hardware debugging device to the server to be tested, and perform network interconnection between the server to be tested and the hardware debugging device;

[0081] The memory eye diagram test module 402, located in the test module, is used to respond to the selection instruction for the memory eye diagram test item, and perform a memory eye diagram test on the server to be tested after network interconnection;

[0082] The data identifier acquisition module 403, located in the storage module, is used to acquire the data identifiers of the server under test and the memory eye diagram test items. There is a pre-established mapping relationship between the data identifiers and the storage locations of the hardware debugging device;

[0083] The test result storage module 404, located in the storage module, is used to generate a storage path for the server under test according to the data identifier and the mapping relationship, and store the memory eye diagram test result based on the generated storage path.

[0084] In an embodiment of the present application, the network module is provided with a static gateway address and / or a dynamic gateway address; the network interconnection module 401 may include the following sub-modules:

[0085] The first network segment allocation sub-module is used to, when the network module is set with a static gateway address, in response to a gateway switching instruction for the static gateway address and / or the dynamic gateway address set in the network module, acquire the dynamic gateway network segment information of the hardware debugging device, and allocate the dynamic gateway network segment information of the hardware debugging device to the server under test.

[0086] In an embodiment of the present application, the network module is provided with a static gateway address and / or a dynamic gateway address; the network interconnection module 401 may include the following sub-modules:

[0087] The second network segment allocation sub-module is used to, when the network module is set with a dynamic gateway address, in response to a gateway switching instruction for the static gateway address and / or the dynamic gateway address set in the network module, acquire the static gateway network segment information of the hardware debugging device, and allocate the static gateway network segment information of the hardware debugging device to the server under test.

[0088] In an embodiment of the present application, the hardware debugging device further includes an expansion module. The device proposed in the embodiment of the present application may further include the following module:

[0089] The real-time test information display module, located in the test module, is used to display the current real-time test information and test exception prompt on the display screen of the hardware debugging device during the process of performing a memory eye diagram test on the server under test after network interconnection; wherein, the real-time test information includes any one or more of the remaining test time, test speed, and test progress, and the test exception prompt is used to inform the hardware debugging device of module exceptions during the process of performing a memory eye diagram test on the server under test.

[0090] In an embodiment of the present application, the hardware debugging device further includes a debugging module. After responding to the access instruction of the server under test to the hardware debugging device, the device proposed in the embodiment of the present application may further include the following module:

[0091] The test environment setup detection module, located in the debugging module, is used to respond to the power-on and power-off instructions of the hardware debugging device, detect whether the connected server under test presents corresponding operations to the power-on and power-off instructions, and obtain the test environment setup result; the test environment setup result is used to inform the hardware debugging device whether the test environment requirements for the server under test are met during the test environment setup.

[0092] In an embodiment of the present application, the hardware debugging device further includes an expansion module. The device proposed in the embodiment of the present application may further include the following modules:

[0093] The test result generation module, located in the expansion module, is used to obtain the test log obtained by the test module for performing a memory eye diagram test on the server under test after network interconnection, and perform log analysis on the test log to obtain the memory eye diagram test result.

[0094] In the memory eye diagram test device proposed in the embodiment of the present application, the network module can respond to the access instruction of the server under test to the hardware debugging device, allocate the network segment information of the hardware debugging device to the server under test to perform network interconnection between the server under test and the hardware debugging device. Then, the test module can respond to the selection instruction for the memory eye diagram test item, perform a memory eye diagram test on the server under test after network interconnection, and the storage module can generate a storage path for the server under test according to the data identifier and the mapping relationship, and store the memory eye diagram test result based on the generated storage path. That is, based on the function modules related to the test environment setup possessed by the hardware debugging device itself, automatic allocation of the same network segment can be realized when the server under test is accessed, reducing the connection to the external network and network configuration and other environments required for testing, and canceling the control machine in the test environment, reducing the environment setup time. Moreover, based on the direct response operation to the hardware debugging device, the operability of the memory eye diagram test can be improved, and the test efficiency can be enhanced. Further, the memory eye diagram test result of the server under test can be stored based on the specified storage path, which is convenient for the management of the server under test, thereby further enhancing the test efficiency.

[0095] For the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple. For the relevant parts, refer to the partial description of the method embodiment.

[0096] In some embodiments of the present application, the embodiment of the present application also provides a non-volatile computer-readable storage medium, as Figure 5 shown, a computer program 51 is stored on the non-volatile computer-readable storage medium 5. When the computer program 51 is executed by a processor, it implements each process of the above-mentioned network card stability test method embodiment and can achieve the same technical effect. To avoid repetition, it will not be elaborated here.

[0097] Each embodiment in this specification is described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other.

[0098] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a device, or a computer program product. Therefore, the embodiments of the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0099] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the method, terminal device (system), and computer program product according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram can be implemented by computer program instructions, and the combination of the processes and / or blocks in the flowchart and / or block diagram can also be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal devices generate a device for implementing the functions specified in one process Figure 1 one process or multiple processes and / or blocks Figure 1 or multiple blocks.

[0100] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal device to work in a specific manner, so that the instructions stored in the computer-readable memory generate a manufactured product including an instruction device, and the instruction device implements the functions specified in one process Figure 1 one process or multiple processes and / or blocks Figure 1 or multiple blocks.

[0101] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device, so that a series of operation steps are executed on the computer or other programmable terminal device to generate a computer-implemented process. Thus, the instructions executed on the computer or other programmable terminal device provide steps for implementing the functions specified in one process Figure 1 one process or multiple processes and / or blocks Figure 1 or multiple blocks.

[0102] Although the preferred embodiments of the embodiments of the present application have been described, those skilled in the art can make additional changes and modifications once they learn the basic creative concepts. Therefore, the appended claims are intended to be construed to include the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present application.

[0103] Finally, it should also be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or terminal device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or terminal device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or terminal device comprising the element.

[0104] The above has introduced in detail a method for testing the memory eye diagram, a hardware debugging device, and a corresponding computer storage medium provided by the present application. Specific examples are used in this text to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for those of ordinary skill in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A method for testing the memory eye diagram, characterized in that, it relates to a hardware debugging device, and the hardware debugging device is used to perform memory eye diagram testing on the server to be tested, including a network module, a testing module, and a storage module. The method includes: Responding to the access instruction of the server to be tested to the hardware debugging device, obtaining the network segment information of the hardware debugging device through the network module, allocating the network segment information of the hardware debugging device to the server to be tested, and performing network interconnection between the server to be tested and the hardware debugging device; Responding to the selection instruction of the memory eye diagram test item, and performing memory eye diagram testing on the server to be tested after network interconnection through the testing module; Obtaining the data identifiers of the server to be tested and the memory eye diagram test item through the storage module, and a pre-established mapping relationship exists between the data identifier and the storage location of the hardware debugging device; Generating a storage path for the server to be tested according to the data identifier and the mapping relationship through the storage module, and storing the memory eye diagram test result based on the generated storage path; The network module is provided with a static gateway address and / or a dynamic gateway address; the obtaining the network segment information of the hardware debugging device through the network module and allocating the network segment information of the hardware debugging device to the server to be tested includes: When the network module is set with a static gateway address, responding to the gateway switching instruction of the static gateway address and / or the dynamic gateway address set in the network module, obtaining the dynamic gateway network segment information of the hardware debugging device through the network module, and allocating the dynamic gateway network segment information of the hardware debugging device to the server to be tested; The network module is provided with a static gateway address and / or a dynamic gateway address; the obtaining the network segment information of the hardware debugging device through the network module and allocating the network segment information of the hardware debugging device to the server to be tested includes: When the network module is set with a dynamic gateway address, responding to the gateway switching instruction of the static gateway address and / or the dynamic gateway address set in the network module, obtaining the static gateway network segment information of the hardware debugging device through the network module, and allocating the static gateway network segment information of the hardware debugging device to the server to be tested.

2. The method according to claim 1, characterized in that, testing the server to be tested after network interconnection according to the memory eye diagram test item through the testing module to obtain the memory eye diagram test result, and further includes: During the process of performing memory eye diagram testing on the server to be tested after network interconnection, displaying the current real-time test information and test exception prompt on the display screen of the hardware debugging device through the testing module; wherein, the real-time test information includes any one or more of the remaining test time, test speed, and test progress, and the test exception prompt is used to inform the hardware debugging device of module exceptions during the process of performing memory eye diagram testing on the server to be tested.

3. The method according to claim 1 or 2, It is characterized in that the hardware debugging device further includes a debugging module. After responding to the access instruction of the server under test to the hardware debugging device, it further includes: responding to the power-on and power-off instruction of the hardware debugging device, detecting whether the accessed server under test presents corresponding operations to the power-on and power-off instruction through the debugging module, and obtaining a test environment setup result; the test environment setup result is used to inform the hardware debugging device whether the test environment requirements for the server under test are met during the test environment setup.

4. The method according to claim 1, It is characterized in that the hardware debugging device further includes an expansion module. After the test module performs a memory eye diagram test on the server under test after network interconnection, it further includes: obtaining the test log obtained by the test module for performing a memory eye diagram test on the server under test after network interconnection through the expansion module, and performing log analysis on the test log to obtain a memory eye diagram test result.

5. A hardware debugging device, It is characterized in that when the hardware debugging device is executed, it implements the memory eye diagram test method according to any one of claims 1 to 4. The hardware debugging device is used to perform a memory eye diagram test on the server under test, and includes a network module, a test module, and a storage module; wherein, the network module is used to respond to the access instruction of the server under test to the hardware debugging device, obtain the network segment information of the hardware debugging device, allocate the network segment information of the hardware debugging device to the server under test, and perform network interconnection between the server under test and the hardware debugging device; the test module is used to respond to the selection instruction of the memory eye diagram test item and perform a memory eye diagram test on the server under test after network interconnection; the storage module is used to obtain the data identifiers of the server under test and the memory eye diagram test item, generate a storage path for the server under test according to the data identifier and the mapping relationship, and store the memory eye diagram test result based on the generated storage path; the network module is provided with a static gateway address and / or a dynamic gateway address; the network interconnection module includes the following sub-modules: a first network segment allocation sub-module, configured to, when the network module is set with a static gateway address, respond to the gateway switching instruction of the static gateway address and / or the dynamic gateway address set in the network module, obtain the dynamic gateway network segment information of the hardware debugging device, and allocate the dynamic gateway network segment information of the hardware debugging device to the server under test; a second network segment allocation sub-module, configured to, when the network module is set with a dynamic gateway address, respond to the gateway switching instruction of the static gateway address and / or the dynamic gateway address set in the network module, obtain the static gateway network segment information of the hardware debugging device, and allocate the static gateway network segment information of the hardware debugging device to the server under test.

6. The hardware debugging device according to claim 5, It is characterized in that The hardware debugging device further includes an expansion module, which is configured to obtain the test log obtained by the test module for performing a memory eye diagram test on the server under test after network interconnection, and perform log analysis on the test log to obtain the memory eye diagram test result.

7. The hardware debugging device according to claim 5 or 6, wherein, the hardware debugging device further includes a debugging module, which is configured to respond to the power-on and power-off instructions of the hardware debugging device, detect whether the server under test connected thereto presents corresponding operations to the power-on and power-off instructions, and obtain the test environment setup result; The test environment setup result is used to inform the hardware debugging device whether the test environment requirements for the server under test are met during the test environment setup.

8. A computer-readable storage medium, wherein, a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the memory eye diagram test method according to any one of claims 1 to 4 is implemented.

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