A hardware architecture for matching board card fool-proofing

Abstract

The application provides a hardware architecture for matching board cards and preventing mistakes, comprising a mainboard and a daughterboard; three XOR modules, an OR module, a control module and a VR output module are arranged on the mainboard; three daughterboard access ends are arranged on the daughterboard; input ends of the XOR modules are connected with mainboard input ends and the daughterboard access ends respectively; an output end of one XOR module is connected with an input end of the OR module; an output end of the OR module is connected with a control end of the control module; an input end of the control module and an EN end of the VR output module are connected to a Power Enable end respectively; an output end of the control module is grounded; if versions of the mainboard and the daughterboard are the same, an output state of the OR module is 0, the control module is not turned on, and the VR output module does not output a level. The hardware architecture solves the matching problem between different board card versions, solves the version matching problem between the mainboard and the daughterboard, and improves the research and development efficiency of researchers.

Description

Technical Field

[0001] This invention relates to the field of board version matching technology, and in particular to a hardware architecture for preventing mistaken matching of boards. Background Technology

[0002] In the hardware development process, there are always initial development versions, several intermediate versions, and finally the mass production version. A system might use five or six or more boards, including the motherboard. It's possible that the motherboard uses a newer version while the daughterboard uses an older version, which could cause incompatibility issues, requiring the daughterboard to also use the newer version. This often requires developers to pay close attention to version compatibility.

[0003] In the current R&D process, if a problem is known, it may not be discovered when using different versions of motherboards. Often, the compatibility issue is only remembered after the problem occurs, resulting in a significant waste of time. Alternatively, the testing department may not pay close attention to version compatibility when receiving motherboards. If an anomaly occurs, developers may not immediately know whether it's a compatibility issue between the motherboard and daughterboard, or a version issue between them. This wastes considerable time for developers searching for the problem, ultimately wasting development resources. Summary of the Invention

[0004] The hardware architecture for error-proofing matching boards provided by this invention solves the compatibility problem between different board versions and the version compatibility problem between the motherboard and the daughterboard, thereby improving the R&D efficiency of researchers. The hardware architecture for error-proofing matching boards includes: a motherboard and a daughterboard;

[0005] The motherboard is equipped with a first XOR module, a second XOR module, a third XOR module, an OR module, a control module, and a VR output module;

[0006] The daughterboard has three daughterboard access terminals;

[0007] The first input terminal A1 of the first XOR module is connected to the first motherboard input terminal;

[0008] The second input terminal B1 of the first XOR module is connected to the first daughterboard access terminal;

[0009] The first input terminal A2 of the second XOR module is connected to the input terminal of the second motherboard.

[0010] The second input terminal B2 of the second XOR module is connected to the access terminal of the second daughter board.

[0011] The first input terminal A3 of the third XOR module is connected to the input terminal of the third motherboard.

[0012] The second input terminal B3 of the third XOR module is connected to the access terminal of the third daughterboard.

[0013] The output terminals of the first XOR module, the second XOR module, and the third XOR module are respectively connected to the input terminal of the OR module.

[0014] The output of the OR module is connected to the control terminal of the control module; the input of the control module and the EN terminal of the VR output module are respectively connected to the Power Enable terminal; the output of the control module is grounded.

[0015] If the motherboard version and the daughterboard version are the same, the output state of the OR module is 0, the control module is not turned on, and the VR output module does not output a level.

[0016] It should be further noted that if the version of the daughterboard is different from that of the motherboard, the output state of the OR module will be 1, the control module will be turned on, the VR output module will not be able to output a level, and the system will not power on.

[0017] It should be further noted that a resistor R1 is set on the power connection line between the first motherboard input terminal and the power supply, so that the first input terminal A1 of the first XOR module is connected to the power supply through the resistor R1, and the output state of the first XOR module is 1.

[0018] Alternatively, a resistor R1 can be set on the connection line between the first motherboard input terminal and the ground, so that the first input terminal A1 of the first XOR module is grounded through the resistor R1, and the output state of the first XOR module is 0.

[0019] It should be further noted that a resistor R2 is set on the power connection line between the second motherboard input terminal and the power supply, so that the second input terminal A2 of the second XOR module is connected to the power supply through the resistor R2, and the output state of the second XOR module is 1.

[0020] Alternatively, a resistor R2 can be set on the connection line between the input terminal of the second motherboard and the ground, so that the first input terminal A2 of the second XOR module is grounded through the resistor R2, and the output state of the second XOR module is 0.

[0021] It should be further noted that a resistor R3 is set on the power supply connection line between the third motherboard input terminal and the power supply, so that the third input terminal A3 of the third XOR module is connected to the power supply through the resistor R3, and the output state of the third XOR module is 1.

[0022] Alternatively, a resistor R3 can be set on the connection line between the third motherboard input terminal and the ground, so that the first input terminal A3 of the third XOR module is grounded through the resistor R3, and the output state of the third XOR module is 0.

[0023] It should be further noted that a resistor R11 is set on the power connection line between the first daughterboard access terminal and the power supply, so that the first daughterboard access terminal is connected to the power supply through the resistor R11, and the output state of the first daughterboard access terminal is 1.

[0024] Alternatively, a resistor R11 can be set on the grounding connection line between the first daughterboard access terminal and the grounding connection line, so that the first daughterboard access terminal is grounded through the resistor R1, and the output state of the first daughterboard access terminal is 0.

[0025] A resistor R12 is set on the power connection line between the second daughterboard access terminal and the power supply, so that the second daughterboard access terminal is connected to the power supply through the resistor R12, and the output state of the second daughterboard access terminal is 1.

[0026] Alternatively, a resistor R12 can be set on the connection line between the second sub-board access terminal and the grounding line, so that the second sub-board access terminal is grounded through the resistor R12, and the output state of the second sub-board access terminal is 0.

[0027] A resistor R13 is set on the power connection line between the third daughterboard access terminal and the power supply, so that the third daughterboard access terminal is connected to the power supply through the resistor R13, and the output state of the third daughterboard access terminal is 1.

[0028] Alternatively, a resistor R13 can be installed on the connection line between the third daughterboard access terminal and the grounding line, so that the third daughterboard access terminal is grounded through the resistor R13, and the output state of the third daughterboard access terminal is 0.

[0029] It should be further explained that the OR module processes the output signals from the first XOR module, the second XOR module, and the third XOR module as follows:

[0030] OR1=(A1⊕B1)+(A2⊕B2)+(A3⊕B3).

[0031] It should be further noted that the motherboard has a motherboard communication module.

[0032] The daughterboard is equipped with a daughterboard communication module;

[0033] The motherboard communication module and the daughterboard communication module are connected via a communication cable;

[0034] The motherboard communication module and the daughterboard communication module are connected wirelessly.

[0035] It should be further noted that the control module uses a transistor Q1 or a field-effect transistor.

[0036] As can be seen from the above technical solutions, the present invention has the following advantages:

[0037] The hardware architecture for preventing mismatches in matching boards provided by this invention is based on Boolean algebra for detection. This hardware architecture can perform set operations and logical operations based on Boolean algebra. If the versions are different, the input to the OR module is 1; if they are the same, it is 0. Therefore, if one input is 1, it indicates a difference, resulting in an output of 1, which in turn turns on Q1 and disables the PowerEnable pin. This blocks the output level of the VR output module, cutting off the power timing. Based on this implementation, when different board versions are paired, version compatibility issues no longer need to be considered only when anomalies occur, and manual intervention is unnecessary.

[0038] The hardware architecture for error-proofing matching boards provided by this invention solves the compatibility problem between different board versions, resolves the version compatibility problem between the motherboard and the daughterboard, and improves the R&D efficiency of R&D personnel. Attached Figure Description

[0039] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the description will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a schematic diagram of the hardware architecture used for foolproof matching of the board. Detailed Implementation

[0041] like Figure 1 As shown, the illustrations provided in the hardware architecture for matching board error prevention provided by the present invention are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and not the number, shape and connection relationship of the components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be arbitrarily changed, and the component layout may also be more complex.

[0042] The hardware architecture for preventing faulty matching of boards provided by this invention is to solve the problem of mismatch between motherboard 1 and daughterboard 2, or the problem of abnormalities caused by version issues between motherboard 1 and daughterboard 2, which prevents R&D personnel from knowing about the abnormality in time, thus wasting a lot of time for R&D personnel to find the abnormality.

[0043] The versions involved in this invention include, but are not limited to, EVT1, EVT2, DVT1, DVT2, PVT1, PVT2, etc. Typically, motherboard 1 is version EVT1, and the corresponding daughterboard 2 is also version EVT1. If motherboard 1 is version DVT1, the corresponding daughterboard 2 will also be version DVT1. However, if motherboard 1 is version EVT1 and the corresponding daughterboard 2 is version DVT1, an abnormal problem will occur. The aforementioned EVT1, EVT2, DVT1, DVT2, PVT1, PVT2, etc., refer to the version models of motherboard 1 and daughterboard 2, and the specific models are not limited.

[0044] The hardware architecture for matching board foolproofing provided by the present invention includes a first XOR module 3, a second XOR module 4, a third XOR module 5, an OR module 6, a control module, and a VR output module 7 on the motherboard 1; the control module adopts a transistor Q1 or a field-effect transistor.

[0045] Sub-board 2 has three sub-board 2 access terminals;

[0046] The first input terminal A1 of the first XOR module 3 is connected to the input terminal of the first motherboard 1; the second input terminal B1 of the first XOR module 3 is connected to the access terminal of the first daughterboard 2; the first input terminal A2 of the second XOR module 4 is connected to the input terminal of the second motherboard 1; the second input terminal B2 of the second XOR module 4 is connected to the access terminal of the second daughterboard 2; the first input terminal A3 of the third XOR module 5 is connected to the input terminal of the third motherboard 1; the second input terminal B3 of the third XOR module 5 is connected to the access terminal of the third daughterboard 2; the output terminals of the first XOR module 3, the second XOR module 4, and the third XOR module 5 are respectively connected to the input terminal of the OR module 6; the output terminal of the OR module 6 is connected to the control terminal of the control module; the input terminal of the control module and the EN terminal of the VR output module 7 are respectively connected to the Power Enable terminal; the output terminal of the control module is grounded.

[0047] The processing method of OR module 6 receiving the output signals of the first XOR module 3, the second XOR module 4 and the third XOR module 5 is: OR1 = (A1⊕B1) + (A2⊕B2) + (A3⊕B3).

[0048] In other words, the hardware architecture used for error-proofing matching boards is based on Boolean algebra for detection, and the hardware architecture of this invention can perform set operations and logical operations based on Boolean algebra. Set operations using Boolean algebra can obtain the intersection, union, or complement of different sets, while logical operations can be performed on different sets.

[0049] From this Boolean algebra, we can see that if the versions are different, the input of OR module 6 is 1; if they are the same, it is 0. Therefore, if one input is 1, it means there is a difference, resulting in an output of 1, which in turn turns on Q1 and disables the Power Enable terminal. This thus blocks the output level of VR output module 7, cutting off the power supply timing.

[0050] Furthermore, a resistor R1 is provided on the power connection line between the input terminal of the first motherboard 1 and the power supply, so that the first input terminal A1 of the first XOR module 3 is connected to the power supply through the resistor R1, and the output state of the first XOR module 3 is 1; or a resistor R1 is provided on the ground connection line between the input terminal of the first motherboard 1 and the ground, so that the first input terminal A1 of the first XOR module 3 is grounded through the resistor R1, and the output state of the first XOR module 3 is 0.

[0051] In this invention, a resistor R2 is provided on the power supply connection line between the input terminal of the second motherboard 1 and the power supply, so that the second input terminal A2 of the second XOR module 4 is connected to the power supply through the resistor R2, and the output state of the second XOR module 4 is 1; or a resistor R2 is provided on the ground connection line between the input terminal of the second motherboard 1 and the ground, so that the first input terminal A2 of the second XOR module 4 is grounded through the resistor R2, and the output state of the second XOR module 4 is 0.

[0052] In this invention, a resistor R3 is provided on the power supply connection line between the input terminal of the third motherboard 1 and the power supply, so that the third input terminal A3 of the third XOR module 5 is connected to the power supply through the resistor R3, and the output state of the third XOR module 5 is 1; or a resistor R3 is provided on the ground connection line between the input terminal of the third motherboard 1 and the ground, so that the first input terminal A3 of the third XOR module 5 is grounded through the resistor R3, and the output state of the third XOR module 5 is 0.

[0053] As for the sub-board 2 of the present invention, a resistor R11 is provided on the power connection line between the first sub-board 2 access terminal and the power supply line, so that the first sub-board 2 access terminal is connected to the power supply through the resistor R11, and the output state of the first sub-board 2 access terminal is 1; or a resistor R11 is provided on the ground connection line between the first sub-board 2 access terminal and the ground, so that the first sub-board 2 access terminal is grounded through the resistor R1, and the output state of the first sub-board 2 access terminal is 0.

[0054] A resistor R12 is set on the power connection line between the second sub-board 2 access terminal and the power supply line, so that the second sub-board 2 access terminal is connected to the power supply through the resistor R12, and the output state of the second sub-board 2 access terminal is 1.

[0055] Alternatively, a resistor R12 can be set on the connection line between the second sub-board 2 access terminal and the grounding line, so that the second sub-board 2 access terminal is grounded through the resistor R12, and the output state of the second sub-board 2 access terminal is 0.

[0056] A resistor R13 is set on the power connection line between the third daughterboard 2 access terminal and the power supply line, so that the third daughterboard 2 access terminal is connected to the power supply through the resistor R13, and the output state of the third daughterboard 2 access terminal is 1.

[0057] Alternatively, a resistor R13 can be installed on the connection line between the third sub-board 2 access terminal and the grounding line, so that the third sub-board 2 access terminal is grounded through the resistor R13, and the output state of the third sub-board 2 access terminal is 0.

[0058] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0059] One embodiment of the hardware architecture for foolproof matching of matching boards provided by this invention is as follows: The motherboard 1 is an EVT version, and the daughter card is also an EVT version. A resistor R1 is set on the ground connection line between the first motherboard 1 input terminal and the ground connection line, so that the first input terminal A1 of the first XOR module 3 is grounded through resistor R1, and the output state of the first XOR module 3 is 0. A resistor R2 is set on the ground connection line between the second motherboard 1 input terminal and the ground connection line, so that the first input terminal A2 of the second XOR module 4 is grounded through resistor R2, and the output state of the second XOR module 4 is 0. A resistor R3 is set on the ground connection line between the third motherboard 1 input terminal and the ground connection line, so that the first input terminal A3 of the third XOR module 5 is grounded through resistor R3, and the output state of the third XOR module 5 is 0.

[0060] A resistor R11 is installed on the connection line between the first sub-board 2 access terminal and the grounding line, so that the first sub-board 2 access terminal is grounded through the resistor R1, and the output state of the first sub-board 2 access terminal is 0; a resistor R12 is installed on the connection line between the second sub-board 2 access terminal and the grounding line, so that the second sub-board 2 access terminal is grounded through the resistor R12, and the output state of the second sub-board 2 access terminal is 0; a resistor R13 is installed on the connection line between the third sub-board 2 access terminal and the grounding line, so that the third sub-board 2 access terminal is grounded through the resistor R13, and the output state of the third sub-board 2 access terminal is 0.

[0061] OR module 6 calculates based on OR1=(A1⊕B1)+(A2⊕B2)+(A3⊕B3). The output of OR module 6 is also 0, so transistor Q1 is not conducting, VR output module 7 does not output a level, and the version of motherboard 1 is matched with the version of daughterboard 2.

[0062] In another embodiment of the present invention, specifically, the motherboard 1 is a DVT version, but the accompanying daughterboard 2 is an EVT version.

[0063] In other words, a resistor R1 is installed on the ground connection line between the input terminal of the first motherboard 1 and the ground connection line, so that the first input terminal A1 of the first XOR module 3 is grounded through the resistor R1, and the output state of the first XOR module 3 is 0. A resistor R2 is installed on the ground connection line between the input terminal of the second motherboard 1 and the ground connection line, so that the first input terminal A2 of the second XOR module 4 is grounded through the resistor R2, and the output state of the second XOR module 4 is 0. A resistor R3 is installed on the power connection line between the input terminal of the third motherboard 1 and the power supply connection line, so that the third input terminal A3 of the third XOR module 5 is connected to the power supply through the resistor R3, and the output state of the third XOR module 5 is 1.

[0064] A resistor R11 is installed on the connection line between the first sub-board 2 access terminal and the grounding line, so that the first sub-board 2 access terminal is grounded through the resistor R1, and the output state of the first sub-board 2 access terminal is 0; a resistor R12 is installed on the connection line between the second sub-board 2 access terminal and the grounding line, so that the second sub-board 2 access terminal is grounded through the resistor R12, and the output state of the second sub-board 2 access terminal is 0; a resistor R13 is installed on the connection line between the third sub-board 2 access terminal and the grounding line, so that the third sub-board 2 access terminal is grounded through the resistor R13, and the output state of the third sub-board 2 access terminal is 0.

[0065] OR module 6 calculates based on OR1=(A1⊕B1)+(A2⊕B2)+(A3⊕B3), and the output of OR module 6 is also 1. Therefore, transistor Q1 is turned on, and VR output module 7 cannot output a level, thus blocking the power-on process. The versions of motherboard 1 and daughterboard 2 are incompatible, and the system can also issue a prompt message.

[0066] In another embodiment of the present invention, the motherboard 1 is a DVT version, and the daughter card is also a DVT version. A resistor R1 is provided on the input terminal and ground connection line of the first motherboard 1, so that the first input terminal A1 of the first XOR module 3 is grounded through resistor R1, and the output state of the first XOR module 3 is 0. A resistor R2 is provided on the input terminal and ground connection line of the second motherboard 1, so that the first input terminal A2 of the second XOR module 4 is grounded through resistor R2, and the output state of the second XOR module 4 is 0. A resistor R3 is provided on the input terminal and power connection line of the third motherboard 1, so that the third input terminal A3 of the third XOR module 5 is connected to the power supply through resistor R3, and the output state of the third XOR module 5 is 1.

[0067] A resistor R11 is installed on the connection line between the first sub-board 2 access terminal and the grounding line, so that the first sub-board 2 access terminal is grounded through the resistor R1, and the output state of the first sub-board 2 access terminal is 0; a resistor R12 is installed on the connection line between the second sub-board 2 access terminal and the grounding line, so that the second sub-board 2 access terminal is grounded through the resistor R12, and the output state of the second sub-board 2 access terminal is 0; a resistor R13 is installed on the connection line between the third sub-board 2 access terminal and the power supply line, so that the third sub-board 2 access terminal is connected to the power supply through the resistor R13, and the output state of the third sub-board 2 access terminal is 1;

[0068] OR module 6 calculates based on OR1=(A1⊕B1)+(A2⊕B2)+(A3⊕B3), and the output of OR module 6 is also 1. Therefore, transistor Q1 is not conducting. The control of VR output module 7 is on the Power Enable GPIO. If Power Enable is 1, VR will output a level; if it is 0, VR will not output a level.

[0069] This implementation method eliminates the need to consider version compatibility issues only when exceptions occur when different board versions are paired together, and also eliminates the need for manual intervention.

[0070] The hardware architecture for error-proofing matching boards provided by this invention solves the compatibility problem between different board versions, resolves the version compatibility problem between motherboard 1 and daughterboard 2, and improves the R&D efficiency of R&D personnel.

[0071] The units and algorithm steps of the various examples described in the embodiments of the hardware architecture for foolproof matching boards provided by this invention can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0072] In the hardware architecture for foolproof matching boards provided by this invention, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or units, or it may be an electrical, mechanical, or other form of connection.

[0073] The hardware architecture for fault-proofing matching boards provided by this invention can be combined in one or more embodiments in any suitable manner. In the following description, numerous specific details are provided to give a full understanding of embodiments of the invention. However, those skilled in the art will recognize that the technical solutions of the invention can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of the invention.

[0074] The hardware architecture for foolproof matching boards provided by this invention can be used to write program code for performing the operations of this disclosure in any combination of one or more programming languages. These programming languages ​​include object-oriented programming languages—such as Java and C++—and conventional procedural programming languages—such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0075] The terms "first," "second," "third," "fourth," etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0076] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A hardware architecture for error-proofing matching boards, characterized in that, include: Motherboard and daughterboard; The motherboard is equipped with a first XOR module, a second XOR module, a third XOR module, an OR module, a control module, and a VR output module; The daughterboard has three daughterboard access terminals; The first input terminal A1 of the first XOR module is connected to the first motherboard input terminal; The second input terminal B1 of the first XOR module is connected to the first daughterboard access terminal; The first input terminal A2 of the second XOR module is connected to the input terminal of the second motherboard. The second input terminal B2 of the second XOR module is connected to the access terminal of the second daughter board. The first input terminal A3 of the third XOR module is connected to the input terminal of the third motherboard. The second input terminal B3 of the third XOR module is connected to the access terminal of the third daughterboard. The output terminals of the first XOR module, the second XOR module, and the third XOR module are respectively connected to the input terminal of the OR module. The output of the OR module is connected to the control terminal of the control module; the input of the control module and the EN terminal of the VR output module are respectively connected to the Power Enable terminal; the output of the control module is grounded. If the motherboard version and the daughterboard version are the same, the output state of the OR module is 0, the control module is not turned on, and the VR output module will not be unable to output a level. If the version of the daughterboard is different from that of the motherboard, the output state of the OR module will be 1, the control module will be turned on, the VR output module will not be able to output a level, and the system will not power on.

2. The hardware architecture for error-proofing matching boards according to claim 1, characterized in that, A resistor R1 is set on the power connection line between the input terminal of the first motherboard and the power supply, so that the first input terminal A1 of the first XOR module is connected to the power supply through the resistor R1, and the output state of the first XOR module is 1. Alternatively, a resistor R1 can be set on the connection line between the first motherboard input terminal and the ground, so that the first input terminal A1 of the first XOR module is grounded through the resistor R1, and the output state of the first XOR module is 0.

3. The hardware architecture for error-proofing matching boards according to claim 1, characterized in that, A resistor R2 is set on the power connection line between the second motherboard input terminal and the power supply, so that the second input terminal A2 of the second XOR module is connected to the power supply through the resistor R2, and the output state of the second XOR module is 1. Alternatively, a resistor R2 can be set on the connection line between the input terminal of the second motherboard and the ground, so that the first input terminal A2 of the second XOR module is grounded through the resistor R2, and the output state of the second XOR module is 0.

4. The hardware architecture for error-proofing matching boards according to claim 1, characterized in that, A resistor R3 is set on the power connection line between the third motherboard input terminal and the power supply, so that the third input terminal A3 of the third XOR module is connected to the power supply through the resistor R3, and the output state of the third XOR module is 1. Alternatively, a resistor R3 can be set on the connection line between the third motherboard input terminal and the ground, so that the first input terminal A3 of the third XOR module is grounded through the resistor R3, and the output state of the third XOR module is 0.

5. The hardware architecture for error-proofing matching boards according to claim 1, characterized in that, A resistor R11 is set on the power connection line between the first daughterboard access terminal and the power supply, so that the first daughterboard access terminal is connected to the power supply through the resistor R11, and the output state of the first daughterboard access terminal is 1. Alternatively, a resistor R11 can be set on the grounding connection line between the first daughterboard access terminal and the grounding connection line, so that the first daughterboard access terminal is grounded through the resistor R1, and the output state of the first daughterboard access terminal is 0. A resistor R12 is set on the power connection line between the second daughterboard access terminal and the power supply, so that the second daughterboard access terminal is connected to the power supply through the resistor R12, and the output state of the second daughterboard access terminal is 1. Alternatively, a resistor R12 can be set on the connection line between the second sub-board access terminal and the grounding line, so that the second sub-board access terminal is grounded through the resistor R12, and the output state of the second sub-board access terminal is 0. A resistor R13 is set on the power connection line between the third daughterboard access terminal and the power supply, so that the third daughterboard access terminal is connected to the power supply through the resistor R13, and the output state of the third daughterboard access terminal is 1. Alternatively, a resistor R13 can be installed on the connection line between the third daughterboard access terminal and the grounding line, so that the third daughterboard access terminal is grounded through the resistor R13, and the output state of the third daughterboard access terminal is 0.

6. The hardware architecture for error-proofing matching boards according to claim 1, characterized in that, The OR module processes the output signals from the first XOR module, the second XOR module, and the third XOR module as follows: OR1=(A1⊕B1)+(A2⊕B2)+(A3⊕B3).

7. The hardware architecture for error-proofing matching boards according to claim 1, characterized in that, The motherboard has a motherboard communication module; The daughterboard is equipped with a daughterboard communication module; The motherboard communication module and the daughterboard communication module are connected via a communication cable; The motherboard communication module and the daughterboard communication module are connected wirelessly.

8. The hardware architecture for error-proofing matching boards according to claim 1, characterized in that, The control module uses a transistor Q1 or a field-effect transistor.

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