Method, device, system and storage medium for processing ciphertext integers

Abstract

The present invention provides a method, device, system, and storage medium for processing ciphertext integers, which are applied to the computer field. The method comprises: performing single-instruction, multiple-data (SIMD) encoding on two ciphertext integers to be added to obtain a first coded integer and a second coded integer; performing a homomorphic addition operation on the first coded integer and the second coded integer to obtain a first operation result; and performing a homomorphic multiplication operation on the first coded integer and the second coded integer to obtain a second operation result. Based on the first operation result and the second operation result, an intermediate variable result is generated; and a homomorphic addition operation is performed on the intermediate variable result and the first operation result to obtain a calculation result of the two ciphertext integers to be added. The present invention adopts a SIMD encoding method to improve the operational efficiency of ciphertext integer addition, while being able to efficiently implement arithmetic operations and Boolean logic operations.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and more specifically, to a method, device, system and storage medium for processing ciphertext integers. Background Art

[0002] Fully homomorphic encryption technology allows for direct computation on ciphertext without decryption, protecting customer privacy and information security. Since Gentry et al. proposed the first achievable fully homomorphic encryption technology in 2009, a variety of fully homomorphic encryption schemes have been proposed, continuously improving the efficiency of homomorphic computing.

[0003] In the process of implementing the present invention, the inventors found that when only a certain type of fully homomorphic encryption scheme is used, we cannot efficiently implement arithmetic operations and Boolean logic operations at the same time. Summary of the Invention

[0004] In view of this, the present invention provides a ciphertext integer processing method, device, system and storage medium that can simultaneously and efficiently implement arithmetic operations and Boolean logic operations.

[0005] One aspect of the present invention provides a method for processing a ciphertext integer, comprising:

[0006] Performing single instruction multiple data encoding on both ciphertext integers to be added to obtain a first encoded integer and a second encoded integer;

[0007] performing a homomorphic addition operation on the first encoded integer and the second encoded integer to obtain a first operation result, and performing a homomorphic multiplication operation on the first encoded integer and the second encoded integer to obtain a second operation result;

[0008] generating an intermediate variable result based on the first operation result and the second operation result;

[0009] Perform a homomorphic addition operation on the intermediate variable result and the first operation result to obtain the operation results of the two ciphertext integers to be added.

[0010] In one embodiment of the present invention, generating an intermediate variable result based on the first operation result and the second operation result includes:

[0011] generating a second type of intermediate variables based on the first operation result and the second operation result, where the second type of intermediate variables includes at least one intermediate variable;

[0012] Perform a homomorphic addition operation on all the intermediate variables to obtain the intermediate variable results.

[0013] In one embodiment of the present invention, generating the second type of intermediate variables based on the first operation result and the second operation result includes:

[0014] Based on the first operation result, generating a first type of intermediate variable;

[0015] Based on the second operation result and the first type of intermediate variables, the second type of intermediate variables are generated.

[0016] In one embodiment of the present invention, generating a first type of intermediate variable based on the first operation result includes:

[0017] Let the result of the first operation be C, and the first type of intermediate variable be IC(m), m∈[1,μ / 2-1], then:

[0018]

[0019] Wherein, μ represents the number of bits of the two ciphertext integers to be added, C i Indicates the i-th position of C, the operator Represents a single instruction multiple data homomorphic multiplication operation, {C 7-1 ,0} represents the ciphertext with C0 set to 0, q is the largest power of 2 less than m, p=mq, and m, p and q are all positive integers.

[0020] In one embodiment of the present invention, generating the second-type intermediate variable based on the second operation result and the first-type intermediate variable includes:

[0021] Let the result of the second operation be D, and the second type of intermediate variable be ID(n), n∈[1,μ-1], then:

[0022]

[0023] Wherein, μ represents the number of bits of the two ciphertext integers to be added, D 1 Indicates that D is shifted one bit higher, the operator Represents a single-instruction multiple-data homomorphic multiplication operation, where r is the largest power of 2 less than n, s=nr, and n, s, and r are all positive integers.

[0024] Another aspect of the present invention provides a ciphertext integer processing device, comprising:

[0025] an encoding module, configured to perform single instruction multiple data encoding on two ciphertext integers to be added, to obtain a first encoded integer and a second encoded integer;

[0026] a first operation module, configured to perform a homomorphic addition operation on the first coded integer and the second coded integer to obtain a first operation result, and to perform a homomorphic multiplication operation on the first coded integer and the second coded integer to obtain a second operation result;

[0027] A generating module, configured to generate an intermediate variable result based on the first operation result and the second operation result;

[0028] The second operation module is used to perform a homomorphic addition operation on the intermediate variable result and the first operation result to obtain the operation results of the two ciphertext integers to be added.

[0029] In one embodiment of the present invention, the generating module includes:

[0030] a generating submodule, configured to generate a second type of intermediate variables based on the first operation result and the second operation result, wherein the second type of intermediate variables includes at least one intermediate variable;

[0031] The operation submodule is used to perform a homomorphic addition operation on all the intermediate variables to obtain the intermediate variable results.

[0032] In one embodiment of the present invention, the generating submodule includes:

[0033] A first generating subunit, configured to generate a first type of intermediate variable based on the first operation result;

[0034] The second generating subunit is configured to generate the second-type intermediate variables based on the second operation result and the first-type intermediate variables.

[0035] In one embodiment of the present invention, the first generating subunit is specifically configured to set the first operation result to be C, the first type of intermediate variable to be IC(m), m∈[1, μ / 2-1], then:

[0036]

[0037] Wherein, μ represents the number of bits of the two ciphertext integers to be added, C i Indicates the i-th position of C, the operator Represents a single instruction multiple data homomorphic multiplication operation, {C 7-1 ,0} represents the ciphertext with C0 set to 0, q is the largest power of 2 less than m, p=mq, and m, p and q are all positive integers.

[0038] In one embodiment of the present invention, the second generating subunit is specifically configured to set the second operation result to D, the second intermediate variable to ID(n), n∈[1,μ-1], then:

[0039]

[0040] Wherein, μ represents the number of bits of the two ciphertext integers to be added, D 1 Indicates that D is shifted one bit higher, and the operator Represents a single-instruction multiple-data homomorphic multiplication operation, where r is the largest power of 2 less than n, s=nr, and n, s, and r are all positive integers.

[0041] Another aspect of the present invention provides a computer-readable storage medium storing computer-executable instructions, which are used to implement the above method when executed.

[0042] Another aspect of the present invention provides a computer program, comprising computer executable instructions, which are used to implement the method described above when executed.

[0043] According to embodiments of the present invention, a method, apparatus, system, and storage medium for processing ciphertext integers are subjected to single-instruction, multiple-data (SIMD) encoding for each of two ciphertext integers to be added, obtaining a first encoded integer and a second encoded integer. A homomorphic addition operation is performed on the first encoded integer and the second encoded integer to obtain a first operation result. Furthermore, a homomorphic multiplication operation is performed on the first encoded integer and the second encoded integer to obtain a second operation result. Based on the first and second operation results, an intermediate variable result is generated. The intermediate variable result and the first operation result are homomorphically added to obtain the operation result of the two ciphertext integers to be added. The use of SIMD encoding improves the computational efficiency of ciphertext integer addition and enables efficient simultaneous implementation of arithmetic and Boolean logic operations. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0045] Figure 1 The following schematically shows a flow chart of a method for processing ciphertext integers according to an embodiment of the present invention;

[0046] Figure 2 A schematic diagram schematically illustrates an operation on a first coded integer and a second coded integer according to an embodiment of the present invention;

[0047] Figure 3 The following schematically shows a flow chart of a method for processing ciphertext integers according to an embodiment of the present invention;

[0048] Figure 4A block diagram schematically shows a ciphertext integer processing apparatus according to an embodiment of the present invention; and

[0049] Figure 5 The block diagram of a computer system according to an embodiment of the present invention is schematically shown. DETAILED DESCRIPTION

[0050] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present invention. In the following detailed description, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of embodiments of the present invention. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concept of the present invention.

[0051] The terms used herein are only for describing specific embodiments and are not intended to limit the present invention. The terms "comprise", "include", etc. used herein indicate the presence of the features, steps, operations and / or components, but do not exclude the presence or addition of one or more other features, steps, operations or components.

[0052] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0053] When expressions such as “at least one of A, B, and C, etc.” are used, they should generally be interpreted in accordance with the meaning commonly understood by those skilled in the art (e.g., “a system having at least one of A, B, and C” should include but is not limited to systems having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, and C, etc.). When expressions such as “at least one of A, B, or C, etc.” are used, they should generally be interpreted in accordance with the meaning commonly understood by those skilled in the art (e.g., “a system having at least one of A, B, or C” should include but is not limited to systems having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, and C, etc.).

[0054] An embodiment of the present invention provides a ciphertext integer processing method, comprising: performing single-instruction multiple-data encoding on two ciphertext integers to be added to obtain a first encoded integer and a second encoded integer, performing a homomorphic addition operation on the first encoded integer and the second encoded integer to obtain a first operation result, and performing a homomorphic multiplication operation on the first encoded integer and the second encoded integer to obtain a second operation result, generating an intermediate variable result based on the first operation result and the second operation result, performing a homomorphic addition operation on the intermediate variable result and the first operation result to obtain an operation result of the two ciphertext integers to be added, and efficiently implementing arithmetic operations and Boolean logic operations simultaneously.

[0055] Figure 1 The flowchart of the ciphertext integer processing method according to an embodiment of the present invention is schematically shown.

[0056] like Figure 1 As shown, the method includes operations S101 to S103.

[0057] In operation S101 , two ciphertext integers to be added are both subjected to single instruction multiple data encoding to obtain a first encoded integer and a second encoded integer.

[0058] In the present invention, Single Instruction Multiple Data (SIMD) encoding is an acceleration method for the BGV12 type fully homomorphic encryption algorithm. The operations of SIMD encoding include homomorphic addition, homomorphic multiplication and shift operations. This encoding method can simultaneously operate on data in multiple SIMD data slots to achieve formal parallel computing.

[0059] In the present invention, the plaintexts corresponding to the two ciphertext integers are both binary numbers with values of "0" or "1", and the plaintexts corresponding to the first coded integer and the second coded integer are also both binary numbers of "0" or "1". The plaintexts corresponding to all data involved in the present invention are both binary numbers of "0" or "1". In the present invention, the first coded integer is represented by x, the second coded integer is represented by y, and x i represents the i-th position of x, y i represents the i-th bit of y. In one example, the number of bits of the first coded integer and the second coded integer are both 8 bits, such as Figure 2 As shown, each square represents a SIMD data slot, and 1 bit of data is placed in the slot.

[0060] In operation S102 , a homomorphic addition operation is performed on the first encoded integer and the second encoded integer to obtain a first operation result, and a homomorphic multiplication operation is performed on the first encoded integer and the second encoded integer to obtain a second operation result.

[0061] In the present invention, represents a homomorphic addition operation, Represents a homomorphic multiplication operation, C represents the result of the first operation, C i Indicates the i-th position of C, D i Indicates the result of the second operation, D i represents the i-th bit of D, like Figure 2 As shown, a homomorphic addition operation is performed on the first encoded integer x and the second encoded integer y to obtain a logical "OR" result C, and a homomorphic multiplication operation is performed on the first encoded integer x and the second encoded integer y to obtain a logical "AND" result D.

[0062] In operation S103 , an intermediate variable result is generated based on the first operation result and the second operation result.

[0063] In the present invention, let h be the result of the addition operation of the first coded integer x and the second coded integer y. The most direct implementation of the addition operation of two ciphertext integers x and y with a bit width of μ bits can be expressed as formula (1):

[0064] add(x,y)=(h0,h1,...,h μ-1 ) Formula (1)

[0065] Among them, h i The ith position of table h, c represents carry, c i represents the i-th position of c,

[0066] In the present invention, using the above formula (1), according to the SIMD encoding method, the addition result of the first encoded integer x and the second encoded integer y can be written as formula (2):

[0067]

[0068] That is the intermediate variable result. After operation S102, the first operation result and the second operation result are calculated. The intermediate variable result can be obtained according to the first operation result and the second operation result. in,

[0069] In operation S104, a homomorphic addition operation is performed on the intermediate variable result and the first operation result to obtain the operation result of the two ciphertext integers to be added.

[0070] In the present invention, as shown in the above formula (2), the first operation result is The intermediate variable results are The intermediate variable result and the first operation result Perform a homomorphic addition operation to obtain the result h of the two ciphertext integers to be added. i .

[0071] Figure 3 The flowchart of the ciphertext integer processing method according to an embodiment of the present invention is schematically shown.

[0072] like Figure 3 As shown, the method includes operations S301 to S306.

[0073] In operation S301 , two ciphertext integers to be added are both subjected to single instruction multiple data encoding to obtain a first encoded integer and a second encoded integer.

[0074] In operation S302 , a homomorphic addition operation is performed on the first encoded integer and the second encoded integer to obtain a first operation result, and a homomorphic multiplication operation is performed on the first encoded integer and the second encoded integer to obtain a second operation result.

[0075] In operation S303 , a first type of intermediate variable is generated based on the first operation result.

[0076] In the present invention, let the first operation result be C, the first type of intermediate variable be IC(m), m∈[1,μ / 2-1], then:

[0077]

[0078] Wherein, μ represents the number of bits of the two ciphertext integers to be added, C i Indicates the i-th position of C, the operator Represents a single instruction multiple data homomorphic multiplication operation, {C 7-1 ,0} represents the ciphertext with C0 set to 0, q is the largest power of 2 less than m, p=mq, and m, p and q are all positive integers.

[0079] In operation S304 , the second-type intermediate variable is generated based on the second operation result and the first-type intermediate variable.

[0080] In the present invention, let the second operation result be D, the second type of intermediate variable be ID(n), n∈[1,μ-1], then:

[0081]

[0082] Wherein, μ represents the number of bits of the two ciphertext integers to be added, D 1Indicates that D is shifted one bit higher, the operator Represents a single-instruction multiple-data homomorphic multiplication operation, where r is the largest power of 2 less than n, s=nr, and n, s, and r are all positive integers.

[0083] In operation S305 , a homomorphic addition operation is performed on all the intermediate variables to obtain the intermediate variable results.

[0084] In the present invention, all the intermediate variables are subjected to homomorphic addition operations to obtain the intermediate variable results, which are

[0085] In operation S306, a homomorphic addition operation is performed on the intermediate variable result and the first operation result to obtain the operation result of the two ciphertext integers to be added.

[0086] In the present invention, the Perform the homomorphic addition operation with C, and the result is the SIMD encoded h0~h μ-1 , that is, the calculation result of the radix-2 SIMD addition operation of the two ciphertext integers to be added is obtained.

[0087] Operation S301 of this embodiment is the same as operation S101 of the above embodiment, operation S302 is the same as operation S102 of the above embodiment, and operation S306 is the same as operation S104 of the above embodiment, which will not be repeated here.

[0088] In one example, taking the first coded integer and the second coded integer as 8 bits each, the intermediate variable result is represented as right Expanding this gives Table 1:

[0089] Table 1

[0090]

[0091] In the figure above, each row represents the i-th bit, and the 8-bit data in each rectangle constitutes a series of intermediate variables, namely IC(m) and ID(n). By performing the homomorphic addition operation on ID(1) to ID(μ-1) as shown in formula (4), the values of all bits can be calculated simultaneously.

[0092]

[0093] When the number of bits of the first coded integer and the second coded integer is 8 bits, IC(m) and ID(n) can be calculated as:

[0094] IC(m) shape is as follows:

[0095] IC(1)={C 7-1 ,0} 1

[0096]

[0097]

[0098] ID(n) is in the form of:

[0099] ID(1)=D 1

[0100]

[0101]

[0102]

[0103]

[0104]

[0105]

[0106] In the present invention, a b Indicates that data a is shifted to the left (high bit) by b bits. For example, ID(1) 6 Indicates that ID(1) is shifted 6 bits to the left (high bit), IC(2) 1 Indicates shifting IC(2) 1 bit to the left (higher order).

[0107] Figure 4 The block diagram of the ciphertext integer processing device according to an embodiment of the present invention is schematically shown.

[0108] like Figure 4 As shown, the ciphertext integer processing apparatus 400 includes an encoding module 410 , a first operation module 420 , a generation module 430 and a second operation module 440 .

[0109] The encoding module 410 is configured to perform single instruction multiple data encoding on two ciphertext integers to be added to obtain a first encoded integer and a second encoded integer.

[0110] The first operation module 420 is configured to perform a homomorphic addition operation on the first coded integer and the second coded integer to obtain a first operation result, and to perform a homomorphic multiplication operation on the first coded integer and the second coded integer to obtain a second operation result.

[0111] The generating module 430 is configured to generate an intermediate variable result based on the first operation result and the second operation result.

[0112] The second operation module 440 is configured to perform a homomorphic addition operation on the intermediate variable result and the first operation result to obtain an operation result of the two ciphertext integers to be added.

[0113] In one embodiment of the present invention, the generating module 430 includes:

[0114] The generating submodule is configured to generate a second type of intermediate variable based on the first operation result and the second operation result, where the second type of intermediate variable includes at least one intermediate variable.

[0115] The operation submodule is used to perform a homomorphic addition operation on all the intermediate variables to obtain the intermediate variable results.

[0116] In one embodiment of the present invention, the generating submodule includes:

[0117] A first generating subunit, configured to generate a first type of intermediate variable based on the first operation result;

[0118] The second generating subunit is configured to generate the second type of intermediate variable based on the second operation result and the first type of intermediate variable.

[0119] In one embodiment of the present invention, the first generating subunit is specifically configured to set the first operation result to C, the first type of intermediate variable to IC(m), m∈[1, μ / 2-1], then:

[0120]

[0121] Wherein, μ represents the number of bits of the two ciphertext integers to be added, C i Indicates the i-th position of C, the operator Represents a single instruction multiple data homomorphic multiplication operation, {C 7-1 ,0} represents the ciphertext with C0 set to 0, q is the largest power of 2 less than m, p=mq, and m, p and q are all positive integers.

[0122] In one embodiment of the present invention, the second generating subunit is specifically configured to set the second operation result to D, the second type of intermediate variable to ID(n), n∈[1,μ-1], then:

[0123]

[0124] Wherein, μ represents the number of bits of the two ciphertext integers to be added, D 1 Indicates that D is shifted one bit higher, the operator Represents a single-instruction multiple-data homomorphic multiplication operation, where r is the largest power of 2 less than n, s=nr, and n, s, and r are all positive integers.

[0125] According to the embodiments of the present invention, any number of modules, submodules, units, and subunits, or at least part of the functions of any number of them can be implemented in one module. According to the embodiments of the present invention, any one or more of the modules, submodules, units, and subunits can be split into multiple modules for implementation. According to the embodiments of the present invention, any one or more of the modules, submodules, units, and subunits can be at least partially implemented as a hardware circuit, such as a field programmable gate array (FPGA), a programmable logic array (PLA), a system on a chip, a system on a substrate, a system on a package, an application specific integrated circuit (ASIC), or can be implemented by hardware or firmware of any other reasonable way of integrating or packaging the circuit, or implemented in any one of the three implementation modes of software, hardware, and firmware, or in an appropriate combination of any of them. Alternatively, according to the embodiments of the present invention, one or more of the modules, submodules, units, and subunits can be at least partially implemented as a computer program module, which can perform the corresponding function when the computer program module is run.

[0126] For example, any multiple of the encoding module 410, the first operation module 420, the generation module 430, and the second operation module 440 can be combined into one module / unit / sub-unit for implementation, or any one of the modules / units / sub-units can be split into multiple modules / units / sub-units. Alternatively, at least part of the functions of one or more of these modules / units / sub-units can be combined with at least part of the functions of other modules / units / sub-units and implemented in one module / unit / sub-unit. According to an embodiment of the present invention, at least one of the encoding module 410, the first operation module 420, the generation module 430, and the second operation module 440 can be at least partially implemented as a hardware circuit, such as a field programmable gate array (FPGA), a programmable logic array (PLA), a system on a chip, a system on a substrate, a system on a package, an application specific integrated circuit (ASIC), or can be implemented by hardware or firmware such as any other reasonable way of integrating or packaging the circuit, or implemented in any one of the three implementation modes of software, hardware, and firmware, or in an appropriate combination of any of them. Alternatively, at least one of the encoding module 410 , the first operation module 420 , the generating module 430 and the second operation module 440 may be at least partially implemented as a computer program module, which may perform corresponding functions when executed.

[0127] It should be noted that the ciphertext integer processing device part in the embodiment of the present invention corresponds to the ciphertext integer processing method part in the embodiment of the present invention. The description of the ciphertext integer processing device part specifically refers to the ciphertext integer processing method part, which will not be repeated here.

[0128] Figure 5 The block diagram of a computer system suitable for implementing the above-described method according to an embodiment of the present invention is schematically shown. Figure 5 The computer system shown is only an example and should not limit the functions and scope of use of the embodiments of the present invention.

[0129] like Figure 5 As shown, the computer system 500 according to an embodiment of the present invention includes a processor 501, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 502 or a program loaded from a storage part 508 into a random access memory (RAM) 503. The processor 501 may, for example, include a general-purpose microprocessor (e.g., a CPU), an instruction set processor and / or a related chipset and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 501 may also include an onboard memory for caching purposes. The processor 501 may include a single processing unit or multiple processing units for performing different actions of the method flow according to an embodiment of the present invention.

[0130] RAM 503 stores various programs and data required for the operation of system 500. Processor 501, ROM 502, and RAM 503 are interconnected via bus 504. Processor 501 executes the programs in ROM 502 and / or RAM 503 to perform various operations according to the method flow of the embodiment of the present invention. It should be noted that the programs may also be stored in one or more memories other than ROM 502 and RAM 503. Processor 501 may also execute the programs stored in the one or more memories to perform various operations according to the method flow of the embodiment of the present invention.

[0131] According to an embodiment of the present invention, system 500 may further include an input / output (I / O) interface 505, which is also connected to bus 504. System 500 may also include one or more of the following components connected to I / O interface 505: an input section 506 including a keyboard, a mouse, etc.; an output section 507 including devices such as a cathode ray tube (CRT), a liquid crystal display (LCD), and speakers; a storage section 508 including a hard disk; and a communication section 509 including a network interface card such as a LAN card or a modem. Communication section 509 performs communication processing via a network such as the Internet. Drive 510 is also connected to I / O interface 505 as needed. Removable media 511, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed in drive 510 as needed, so that computer programs read from the removable media can be installed into storage section 508 as needed.

[0132] According to an embodiment of the present invention, the method flow according to an embodiment of the present invention can be implemented as a computer software program. For example, an embodiment of the present invention includes a computer program product, which includes a computer program carried on a computer-readable storage medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from the network through the communication part 509, and / or installed from the removable medium 511. When the computer program is executed by the processor 501, the above-mentioned functions defined in the system of the embodiment of the present invention are executed. According to an embodiment of the present invention, the system, equipment, device, module, unit, etc. described above can be implemented by a computer program module.

[0133] The present invention also provides a computer-readable storage medium, which may be included in the device / apparatus / system described in the above embodiments, or may exist independently and not incorporated into the device / apparatus / system. The computer-readable storage medium carries one or more programs, which, when executed, implement the method according to the embodiments of the present invention.

[0134] According to an embodiment of the present invention, a computer-readable storage medium may be a non-volatile computer-readable storage medium. For example, it may include, but is not limited to: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In the present invention, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0135] For example, according to an embodiment of the present invention, the computer-readable storage medium may include the ROM 502 and / or the RAM 503 described above and / or one or more memories other than the ROM 502 and the RAM 503 .

[0136] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or a part of code, and the above-mentioned module, program segment, or a part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart, can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0137] Those skilled in the art will appreciate that various combinations and / or combinations of features described in the various embodiments and / or claims of the present invention may be made, even if such combinations or combinations are not explicitly described in the present invention. In particular, various combinations and / or combinations of features described in the various embodiments and / or claims of the present invention may be made, without departing from the spirit and teachings of the present invention. All such combinations and / or combinations fall within the scope of the present invention.

[0138] The above describes embodiments of the present invention. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present invention. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be advantageously used in combination. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, those skilled in the art may make various substitutions and modifications, which are intended to fall within the scope of the present invention.

Claims

1. A method for processing a ciphertext integer, comprising: Performing single instruction multiple data encoding on both ciphertext integers to be added to obtain a first encoded integer and a second encoded integer; performing a homomorphic addition operation on the first encoded integer and the second encoded integer to obtain a first operation result, and performing a homomorphic multiplication operation on the first encoded integer and the second encoded integer to obtain a second operation result; generating an intermediate variable result based on the first operation result and the second operation result; Performing a homomorphic addition operation on the intermediate variable result and the first operation result to obtain the operation result of the two ciphertext integers to be added; The generating of the first type of intermediate variables based on the first operation result includes: Let the first operation result be , the first type of intermediate variable is , ,but: ； in, represents the number of bits of the two ciphertext integers to be added, express No. Bit, operator Represents a single instruction multiple data homomorphic multiplication operation, Indicates that Ciphertext set to 0, is less than The largest power of 2, ,and 、 and are all positive integers; The generating of the second type of intermediate variables based on the second operation result and the first type of intermediate variables includes: Let the result of the second operation be , the second type of intermediate variables are , ,but: ； in, represents the number of bits of the two ciphertext integers to be added, express Shift one bit to the higher position, the operator Represents a single instruction multiple data homomorphic multiplication operation, is less than The largest power of 2, ,and 、 and r are both positive integers.

2. The processing method according to claim 1, wherein The generating of an intermediate variable result based on the first operation result and the second operation result includes: generating a second type of intermediate variables based on the first operation result and the second operation result, where the second type of intermediate variables includes at least one intermediate variable; Perform a homomorphic addition operation on all the intermediate variables to obtain the intermediate variable results.

3. The processing method according to claim 2, wherein: The generating of the second type of intermediate variables based on the first operation result and the second operation result includes: Based on the first operation result, generating a first type of intermediate variable; Based on the second operation result and the first type of intermediate variables, the second type of intermediate variables are generated.

4. A device for processing a ciphertext integer, comprising: an encoding module, configured to perform single instruction multiple data encoding on two ciphertext integers to be added, to obtain a first encoded integer and a second encoded integer; a first operation module, configured to perform a homomorphic addition operation on the first coded integer and the second coded integer to obtain a first operation result, and to perform a homomorphic multiplication operation on the first coded integer and the second coded integer to obtain a second operation result; A generating module, configured to generate an intermediate variable result based on the first operation result and the second operation result; a second operation module, configured to perform a homomorphic addition operation on the intermediate variable result and the first operation result to obtain an operation result of the two ciphertext integers to be added; The generating of the first type of intermediate variables based on the first operation result includes: Let the first operation result be , the first type of intermediate variable is , ,but: ； in, represents the number of bits of the two ciphertext integers to be added, express No. Bit, operator Represents a single instruction multiple data homomorphic multiplication operation, Indicates that Ciphertext set to 0, is less than The largest power of 2, ,and 、 and are all positive integers; The generating of the second type of intermediate variables based on the second operation result and the first type of intermediate variables includes: Let the result of the second operation be , the second type of intermediate variables are , ,but: ； in, represents the number of bits of the two ciphertext integers to be added, express Shift one bit to the higher position, the operator Represents a single instruction multiple data homomorphic multiplication operation, is less than The largest power of 2, ,and 、 and r are both positive integers.

5. The processing device according to claim 4, wherein The generation module includes: a generating submodule, configured to generate a second type of intermediate variables based on the first operation result and the second operation result, wherein the second type of intermediate variables includes at least one intermediate variable; The operation submodule is used to perform a homomorphic addition operation on all the intermediate variables to obtain the intermediate variable results.

6. The processing device according to claim 5, wherein The generation submodule includes: A first generating subunit, configured to generate a first type of intermediate variable based on the first operation result; The second generating subunit is configured to generate the second-type intermediate variables based on the second operation result and the first-type intermediate variables.

7. A computer system comprising: one or more processors; a memory for storing one or more programs, When the one or more programs are executed by the one or more processors, the one or more processors are enabled to implement the method according to any one of claims 1 to 3.

8. A computer-readable storage medium having executable instructions stored thereon, which, when executed by a processor, causes the processor to implement the method according to any one of claims 1 to 3.

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