PUF circuits for defending against machine learning modeling attacks

Abstract

A PUF circuit for resisting machine learning modeling attacks includes: a weak PUF component, a strong PUF component, a nonlinear logic operation unit, a control register, and an XOR gate. The inputs of the nonlinear logic operation unit and the strong PUF component serve as n input pins of the PUF circuit to receive stimuli. The weak PUF component outputs an n-bit response to the control register, which outputs a control vector to the nonlinear logic operation unit. The nonlinear logic operation unit outputs a 1-bit logic operation result, which is XORed with the response vector output by the strong PUF component through an XOR gate. The 1-bit output of the XOR gate serves as the output pin of the secure PUF circuit and outputs the response. This invention possesses the ability to resist existing machine learning modeling attacks while maintaining its lightweight design.

Description

Technical Field

[0001] The present invention relates to a technology in the field of information security, specifically a physically unclonable function (PUF) circuit for resisting machine learning modeling attacks. Background Art

[0002] A physical unclonable function (PUF) is a hardware security mechanism that provides randomness based on process variations introduced during the integrated circuit manufacturing process. PUF extracts the inherent mismatches in chip parameters (such as internal line delays, gate voltages, and other electrical characteristics) and maps input stimuli into binary output responses.

[0003] While this technology offers the potential to replace traditional security mechanisms, its inherent security is threatened by machine learning modeling attacks. Currently, attackers can exploit PUFs that fail to meet security standards by using machine learning algorithms based on a sufficient number of challenge-response pairs (CRPs). By building a model of the PUF and mimicking its stimulus-response behavior, it can compromise its security properties. Traditional circuits, by simply increasing the size of the PUF and adding numerous additional components, not only fail to improve security but also negate the PUF's lightweight nature. Summary of the Invention

[0004] To address the shortcomings of existing circuit technologies, such as high circuit resource usage and complex operation, this paper proposes a PUF circuit for resisting machine learning modeling attacks. This circuit uses a nonlinear logic operation unit to operate on a portion of the bits in the PUF circuit's stimulus, and the result of the operation is used to obfuscate the response of the strong PUF component. Based on the response of the weak PUF component, the circuit determines whether the corresponding bit in the stimulus participates in the nonlinear logic operation. While maintaining its lightweight nature, this paper possesses the ability to resist existing machine learning modeling attacks, including but not limited to feedforward neural network (FNN) attacks, logistic regression (LR) attacks, and support vector machine (SVM) attacks.

[0005] The present invention is achieved through the following technical solutions:

[0006] The present invention relates to a PUF circuit for resisting machine learning modeling attacks, which is an n-stimulus 1-response circuit, comprising: a weak PUF component, a strong PUF component, a nonlinear logic operation unit, a control register, and an XOR gate, wherein: the input ends of the nonlinear logic operation unit and the strong PUF component serve as n input pins of the PUF circuit to receive a stimulus c; the weak PUF component outputs an n-bit response To the control register, the control register outputs the control vector s to the nonlinear logic operation unit, and the nonlinear logic operation unit outputs a 1-bit logic operation result The response vector output by the strong PUF component The XOR operation is performed through the XOR gate, and the 1-bit output end of the XOR gate is used as the output pin of the PUF circuit and outputs the response .

[0007] The logic operation performed by the nonlinear logic operation unit is: when the i-th bit in the control vector s is 1, the i-th bit in the stimulus c is selected. Perform XOR operation and get the result ; When the i-th bit in the control vector is 0, the i-th bit in the stimulus c is Does not participate in the operation, the selected bit is XORed in the nonlinear logic operation unit and the result is obtained .

[0008] The selection is to select the i-th position from the stimulus c The operations are: , where the superscript T represents the transpose operation, is an n-bit control vector, where only the i-th bit is 1 and the rest of the bits are 0.

[0009] The bitwise XOR operation means that when the bits involved in the operation are equivalently transformed: the value 1 remains unchanged and the value 0 becomes -1, the XOR operation can be equivalently transformed into a multiplication operation. According to the above formula, the operation of selecting multiple bits from the stimulus c for XOR operation is: ,in: represents the Kronecker product, is a dimensional vector, is a dimensional vector, parameter l represents the number of bits involved in the XOR operation, and when sufficient (c, ) data pairs, use machine learning algorithms to learn vectors The difficulty of learning the control vector increases exponentially with the increase of parameter l. When l is large enough, the control vector cannot be learned by machine learning. , it is impossible to predict the results under the condition of providing incentive c , it is impossible to further predict the correct response of the PUF circuit .

[0010] According to the uniformity of the response of the weak PUF component, the number of bits involved in the XOR operation, that is, the parameter l in When n is 128, meaning the secure PUF circuit uses a 128-bit stimulus, the theoretical value of l is 64. While the actual value of l may vary somewhat, these small deviations do not affect the circuit's resistance to machine learning modeling. Obfuscating the response by XORing the result of bit 1 in stimulus c provides similar anti-modeling security to that of the l-XOR APUF.

[0011] The strong PUF component adopts but is not limited to arbiter-based PUF (Arbiter-based PUF), such as arbiter PUF (APUF), multiplexer PUF (MPUF), feedforward PUF (FFPUF), interposed PUF (iPUF), etc. The input and output parameters of the strong PUF component should meet n-bit stimulus and 1-bit response.

[0012] The nonlinear logic operation unit is used for performing an XOR operation, and its main component is a multi-input single-output XOR gate.

[0013] The weak PUF component may be, but is not limited to, an SRAM PUF, a DRAM PUF, or a RO PUF. The weak PUF component outputs n bits, which is the same as the number of excitation bits of the PUF circuit.

[0014] Technical Effects

[0015] This invention directly selects a portion of the stimulus data for nonlinear operations, and the results are used to obfuscate the response, achieving resistance to machine learning modeling attacks. Existing strong PUF circuits typically use obfuscated stimuli, requiring a large number of additional auxiliary components. The few circuits that do use obfuscated responses also don't directly use the results of the stimulus's nonlinear operations, similarly requiring significant additional resources to ensure resistance to machine learning modeling. Secondly, this invention uses weak PUF components to generate control information, which determines whether each bit of stimulus data participates in the nonlinear operations, ensuring the PUF circuit possesses sufficient randomness and resistance to machine learning modeling attacks. Compared to existing technologies, this invention's response obfuscation technology, based on nonlinear stimuli operations, resists machine learning modeling attacks without the need for additional obfuscation components or increased circuit size, offering the advantages of low resource usage and simple operation. "Simple operation" here primarily refers to the absence of additional auxiliary signals or protocols. This invention, based on the stimulus selection technology of weak PUF components, provides randomness while satisfying Kerckhoff's principle, enabling the circuit to resist existing machine learning modeling attacks. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a schematic diagram of the secure PUF circuit principle of the present invention;

[0017] Figure 2 This is a schematic diagram of the secure PUF circuit in Example 1;

[0018] In the figure: APUF is used as a strong PUF component, and SRAM PUF is used as a weak PUF;

[0019] Figure 3 This is a schematic diagram of the secure PUF circuit in Example 2;

[0020] In the figure: The strong PUF component uses (x,y)-iPUF, and the weak PUF uses DRAM PUF. DETAILED DESCRIPTION

[0021] Example 1

[0022] like Figure 2 As shown, this embodiment relates to a lightweight, secure, and strong PUF circuit for resisting machine learning modeling attacks.

[0023] The strong PUF component used in this embodiment is improved on the basis of the arbiter PUF (APUF), and includes several cascaded sub-units and a dual arbiter. In particular, when the strong PUF component is working, it receives a step signal through the signal terminal, and the step signal is divided into two paths and passes through each level of sub-unit in turn. Each bit of the stimulus To control the i-th level subunit and determine whether two signals are transmitted along parallel paths (shown by dotted lines) or cross paths (shown by dashed stripes), the output of the n-th level subunit is connected to two arbiters. Because the delay of each path is different, the value of the stimulus determines the order in which the two signals arrive at the arbiter, and thus the response. The output of the first arbiter A serves as the response of the strong PUF component and is sent to the input of the XOR gate.

[0024] The dual arbiters both use latch circuits to prevent illegal users from obtaining the response of the APUF through power side channel analysis.

[0025] In this embodiment, the weak PUF component is implemented using an SRAM PUF circuit. When the SRAM is powered on, it generates an n-bit control vector. This control vector is dependent solely on the SRAM's internal parameters and does not change with other factors. Based on the control vector, the corresponding bit in the stimulus is selected to participate in the nonlinear logic operation. If the i-th bit of the control vector is 0, the i-th bit of the stimulus does not participate in the nonlinear logic operation. If it is 1, the i-th bit of the stimulus participates in the operation.

[0026] When this embodiment is working, the user can arbitrarily select an n-bit binary vector as the stimulus c. The stimulus is input into the secure PUF circuit and is simultaneously sent to the APUF and the nonlinear logic operation unit.

[0027] After all the participating bits in stimulus c are XORed, the output result of the nonlinear logic unit is generated. . Response from APUF XOR, generating the final response of the secure PUF circuit And export it externally.

[0028] To evaluate the effectiveness of the present invention against machine learning modeling attacks, we experimentally validated the robust PUF circuit using three representative machine learning modeling attack methods: the FNN attack, the LR attack, and the SVM attack.

[0029] In actual implementation, the PUF circuits were evaluated for their resistance to modeling attacks and their resource usage compared between PSpice simulation and FPGA implementation. All PUF circuits used 128 delay units, corresponding to a 128-bit stimulus. All generated datasets were divided into training data (80%) and test data (20%). The machine learning modeling attack method was implemented in Python 3.7.3, Keras 2.4.3, and TensorFlow 2.3.

[0030] Table 1 shows a comparison between this embodiment (Nonlinear Logic-assistant APUF), the original APUF, and the XOR APUF.

[0031] Table 1 Comparison of anti-modeling attack performance

[0032]

[0033] Table 2 Comparison of resource usage of strong PUF based on FPGA

[0034]

[0035] *Based on the resource usage of a single APUF.

[0036] By comparing the experimental data in Table 1, we can see that APUF itself cannot resist the three types of machine learning modeling attacks. Each attack only requires The APUF can be accurately modeled with just a few CRPs. XOR APUF is a classic type of PUF circuit that is resistant to machine learning attacks. The n-XOR APUF outputs the final response after XORing the responses of n APUFs. When the circuit contains fewer APUFs, the XOR APUF still cannot resist machine learning modeling attacks, such as the 4-XOR APUF. If more APUFs are used, such as the 8-XOR APUF, although it can resist machine learning modeling attacks, it greatly increases resource usage compared to the basic APUF, while reducing reliability (the reliability index represents the proportion of stable CRPs in the PUF), making the XOR APUF difficult to use. Other existing circuits also have similar problems, that is, they cannot simultaneously meet the two requirements of anti-modeling security and lightweight.

[0037] The experimental results shown in Table 1 show that this embodiment can resist three types of machine learning modeling attacks. For three CRPs, the three types of modeling attacks cannot model NLA-APUF, demonstrating its strong ability to resist machine learning modeling attacks.

[0038] The experimental results shown in Table 2 demonstrate that this embodiment, when implemented on an FPGA, only adds one 128-bit SRAM and two XOR gates to the basic APUF, resulting in a significantly lower resource footprint than comparable modeling-resistant PUF circuits. Furthermore, the reliability of this embodiment matches that of the original APUF, avoiding the problem of decreased reliability in n-XOR APUF circuits as the PUF scales and security increases.

[0039] Example 2

[0040] like Figure 3As shown, this embodiment relates to a secure strong PUF circuit for resisting machine learning modeling attacks.

[0041] In this embodiment, the strong PUF component is an intervening PUF ((x,y)-iPUF), which includes two layers of XOR APUFs. The upper layer x-XOR APUF consists of x APUFs, and the lower layer y-XOR APUF consists of y APUFs. The response of the upper layer x-XOR APUF is embedded in the stimulus after an XOR operation and participates in the control of the lower layer y-XOR APUF. The response of the lower layer y-XOR APUF is XORed and output as the response of the (x,y)-iPUF.

[0042] The x APUFs and y APUFs both use dual latches to prevent power consumption analysis.

[0043] In this embodiment, the weak PUF component is implemented using DRAM PUF, which generates an n-bit control vector after power-on. This control vector is only related to the DRAM chip manufacturing process and does not change with other factors.

[0044] The DRAM PUF response is read by software and written into a control register. The secure PUF circuit selects the corresponding bit from the stimulus to participate in nonlinear logic operations based on the control vector in the control register.

[0045] When this embodiment is working, the user can arbitrarily select an n-bit binary vector as the stimulus c to input into the secure strong PUF circuit. The stimulus is sent to the iPUF and the nonlinear logic operation unit at the same time. When the i-th bit of the control vector is 0, the i-th bit of the stimulus does not participate in the nonlinear logic operation. If it is 1, the i-th bit of the stimulus participates in the operation. All participating bits are XORed as the operation result of the nonlinear logic unit. Then the response of iPUF XOR, generating the final response of the secure and strong PUF circuit .

[0046] In actual implementation, the ability of secure PUF circuits to resist modeling attacks was evaluated using both PSpice simulations and FPGA implementations. The secure PUF circuits used 128-bit stimuli. All generated datasets were divided into training data (80%) and test data (20%). The machine learning modeling attack method was implemented in Python 3.7.3, Keras 2.4.3, and TensorFlow 2.3.

[0047] As shown in Table 3, an attack experiment is conducted to compare the anti-machine learning modeling performance of this embodiment (Nonlinear Logic-assistant iPUF) and the original iPUF.

[0048] Table 3 Comparison of anti-modeling attack performance

[0049]

[0050] Comparing the experimental data in Table 3 shows that (x,y)-iPUFs are vulnerable to machine learning modeling attacks at smaller scales. For example, the (2,2)-iPUF and (4,4)-iPUF can still be accurately modeled by all three attack methods. As the scale increases, the number of CRPs required for modeling also increases. However, when the scale reaches a certain level, such as with the (8,8)-iPUF, machine learning modeling attacks can be resisted.

[0051] The experimental results shown in Table 3 show that this embodiment can resist three types of machine learning modeling attacks. For three CRPs, the three types of modeling attacks are unable to model NLA-iPUF, demonstrating its strong ability to resist machine learning modeling attacks.

[0052] As shown in Table 4, when this embodiment is implemented on an FPGA, only one 128-bit DRAM (the DRAM is located outside the FPGA) and one XOR gate are added to the basic iPUF. Its resource usage is far lower than that of similar modeling-resistant PUF circuits. Furthermore, the reliability of this embodiment is consistent with that of the original iPUF, avoiding the problem of reliability degradation as the PUF scales up.

[0053] Table 4 Comparison of resource usage of strong PUF based on FPGA

[0054]

[0055] *Based on the resource usage of (2,2)-iPUF.

[0056] Compared to the existing technology, the present invention improves the resistance to machine learning modeling while maintaining low resource usage (i.e., the effect obtained by adopting the new response obfuscation technology) by using the nonlinear logic operation results of the stimulus to directly obfuscate the response, while resisting machine learning modeling attacks, avoiding the addition of additional complex obfuscation circuits. The data participating in the operation in the stimulus is determined by the response of the weak PUF component, which not only provides randomness but also ensures that the nonlinear logic operation has enough participating bits. Experimental results show that even if a sufficient number of CRPs are provided, existing machine learning modeling attack methods cannot predict the position of the bits participating in the nonlinear logic operation in the stimulus through training, and therefore cannot predict the correct response.

[0057] The above-mentioned specific implementation can be partially adjusted in different ways by those skilled in the art without departing from the principles and purpose of the present invention. The scope of protection of the present invention shall be based on the claims and shall not be limited by the above-mentioned specific implementation. All implementation schemes within its scope shall be subject to the constraints of the present invention.

Claims

1. A PUF circuit for defending against machine learning modeling attacks, characterized in that: include: A weak PUF component, a strong PUF component, a nonlinear logic operation unit, a control register, and an XOR gate, wherein: the input ends of the nonlinear logic operation unit and the strong PUF component serve as n input pins of the PUF circuit to receive stimulus c; the weak PUF component outputs an n-bit response To the control register, the control register outputs the control vector s to the nonlinear logic operation unit, and the nonlinear logic operation unit outputs a 1-bit logic operation result The response vector output by the strong PUF component The XOR operation is performed through the XOR gate, and the 1-bit output end of the XOR gate is used as the output pin of the PUF circuit and outputs the response .

2. The PUF circuit for resisting machine learning modeling attacks according to claim 1, characterized in that: The logic operation is: when the i-th bit in the control vector s is 1, the i-th bit in the stimulus c is selected. Perform XOR operation and get the result ; When the i-th bit in the control vector is 0, the i-th bit in the stimulus c is Does not participate in the operation, the selected bit is XORed in the nonlinear logic operation unit and the result is obtained .

3. The PUF circuit for resisting machine learning modeling attacks according to claim 2, wherein: The selection is to select the i-th position from the stimulus c The operations are: , where: superscript T is the transpose operation, is an n-bit control vector, where only the i-th bit is 1 and the rest of the bits are 0.

4. The PUF circuit for resisting machine learning modeling attacks according to claim 2, wherein: The XOR operation means that when the bits involved in the operation are equivalently converted: the value 1 remains unchanged and the value 0 becomes -1, the XOR operation can be equivalently converted into a multiplication operation; When the i-th bit in the control vector is 0, the i-th bit in the stimulus c is Does not participate in the operation, the selected bit is XORed in the nonlinear logic operation unit and the result is obtained , specifically: ,in: is the Kronecker product, for dimensional vector, for dimensional vector, and the parameter l is the number of bits involved in the XOR operation.

5. The PUF circuit for resisting machine learning modeling attacks according to claim 1, wherein: The strong PUF component adopts an arbiter PUF, a multiplexer PUF, a feedforward PUF, and an intervention PUF and satisfies n-bit excitation and 1-bit response.

6. The PUF circuit for resisting machine learning modeling attacks according to any one of claims 1 to 5, characterized in that: The strong PUF component includes several cascaded sub-units and a dual arbiter, wherein: when the strong PUF component is working, it receives a step signal through the signal end, and the step signal is divided into two paths and passes through each level of sub-unit in turn, and each bit of the stimulus To control the i-th level subunit and determine whether two signals are transmitted along parallel or cross paths, the output of the n-th level subunit is connected to two arbiters. Since the delay of each path is different, the value of the stimulus determines the order in which the two signals arrive at the arbiter, and thus the response. The output of the first arbiter A serves as the response of the strong PUF component and is sent to the input of the XOR gate.

7. The PUF circuit for resisting machine learning modeling attacks according to claim 6, wherein: The dual arbiters both use latch circuits to prevent illegal users from obtaining the response of the APUF through power side channel analysis.

8. The PUF circuit for resisting machine learning modeling attacks according to any one of claims 1 to 5, characterized in that: The strong PUF component is an intervening PUF ((x,y)-iPUF), which includes two layers of XOR APUFs. The upper layer x-XOR APUF consists of x APUFs, and the lower layer y-XOR APUF consists of y APUFs. The response of the upper layer x-XOR APUF is embedded in the stimulus after an XOR operation and participates in the control of the lower layer y-XOR APUF. The response of the lower layer y-XOR APUF is XORed and output as the response of the (x,y)-iPUF.

9. The PUF circuit for resisting machine learning modeling attacks according to claim 8, characterized in that: The x APUFs and y APUFs both use dual latches to prevent power consumption analysis.

10. The PUF circuit for resisting machine learning modeling attacks according to claim 1, wherein: The weak PUF component adopts SRAM PUF, DRAM PUF or RO PUF and satisfies the output of n bits.

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