A SiC trench etching method

Abstract

The present invention relates to a method for etching SiC trenches, belonging to the field of semiconductor processing technology. The method is used to address the problem that the sidewall roughness of the etched trench is much higher than that of an epitaxially grown and polished wafer surface, and that excessive roughness reduces the mobility of the conductive channel and the reliability of the gate oxide. The method comprises: preparing a patterned mask layer on the surface of a silicon carbide substrate; optimizing the pattern of the mask layer; and etching the silicon carbide substrate using the pattern-optimized mask layer. The technical solution provided by the present invention can reduce the sidewall roughness and surface waviness of the silicon carbide after etching, while ensuring the electrical performance of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor processing technology, and in particular to a SiC trench etching method. Background Art

[0002] Silicon carbide (SiC) is a typical representative of the third-generation wide bandgap semiconductor materials. Due to its excellent physical and chemical properties, it is in great demand in high-temperature and high-power applications.

[0003] The current etching technology for silicon carbide is to sequentially set a mask layer and a photoresist layer on the surface of a silicon carbide wafer, then generate a pattern on the photoresist layer, and then complete the processing of the silicon carbide wafer through two etchings.

[0004] However, the sidewall roughness formed after etching is much higher than that of the epitaxial and polished wafer surface. Excessive roughness will reduce the mobility of the conductive channel and the reliability of the gate oxide, thereby affecting the actual performance of the device. Summary of the Invention

[0005] In view of the above analysis, the present invention aims to provide a SiC trench etching method to solve the problem that the sidewall roughness formed after etching is much higher than the epitaxial and polished wafer surface. Excessive roughness will reduce the mobility of the conductive channel and the gate oxide reliability.

[0006] The purpose of the present invention is mainly achieved through the following technical solutions:

[0007] An embodiment of the present invention provides a SiC trench etching method, comprising:

[0008] preparing a patterned mask layer on the surface of the silicon carbide substrate;

[0009] performing graphic optimization on the mask layer;

[0010] The silicon carbide substrate is etched using the pattern-optimized mask layer.

[0011] Furthermore, in step 1, a mask layer is prepared on the silicon carbide substrate, and along a direction away from the surface of the silicon carbide substrate, the mask layer sequentially includes: a first mask dielectric layer and a second mask dielectric layer;

[0012] Step 2: patterning the second mask dielectric layer;

[0013] Step 3: Etching the first mask dielectric layer using the second mask dielectric layer as a mask to transfer the pattern on the second mask dielectric layer to the first mask dielectric layer; after completing the patterning of the first mask dielectric layer, removing the remaining second mask dielectric layer and cleaning the substrate;

[0014] Step 4: using a reflow process to adjust the morphology of the first mask dielectric layer;

[0015] Step 5: Etch the silicon carbide substrate using the first mask dielectric layer as a mask to form a desired trench structure.

[0016] Furthermore, the material of the first mask dielectric layer is amorphous, and the reflow temperature of the first mask dielectric layer is lower than the crystal reconstruction temperature of the silicon carbide matrix;

[0017] The etching selectivity ratio of the first mask dielectric layer to the silicon carbide substrate is 2-3.

[0018] Furthermore, the material of the first mask dielectric layer is phosphosilicate glass or borophosphosilicate glass.

[0019] Furthermore, a thickness ratio of the first mask dielectric layer to the second mask dielectric layer is 1:2-1:3.

[0020] Furthermore, an etching selectivity ratio of the first mask dielectric layer to the silicon carbide substrate is 2-3, and a thickness ratio of the first mask dielectric layer to the silicon carbide substrate is 1:2.

[0021] Furthermore, the thickness of the first mask dielectric layer is 0.5 μm-0.6 μm, and the first mask layer is formed by a CVD process.

[0022] Furthermore, the thickness of the second mask dielectric layer is 1.2 μm-1.8 μm, and the second mask layer is formed by spin coating and curing.

[0023] Furthermore, the step 4 includes:

[0024] Under the conditions of inert gas and heating temperature of 800℃-1200℃, heat for 30min-60min.

[0025] Furthermore, the bottom angle of the reflowed first mask dielectric layer is not less than 45°.

[0026] Furthermore, after etching is completed, the side surfaces of the silicon carbide trench are perpendicular to the bottom surface of the trench.

[0027] Furthermore, the crystal reconstruction temperature of the first mask dielectric layer is lower than the crystal reconstruction temperature of the silicon carbide matrix;

[0028] The etching selectivity ratio of the first mask dielectric layer to the silicon carbide substrate is 2-3;

[0029] The material of the first mask dielectric layer is a crystal having multiple crystal structures, and the crystal does not melt during the crystal reconstruction process.

[0030] The present invention can achieve at least one of the following beneficial effects:

[0031] 1. In the prior art, a post-etching treatment process is typically used to reduce the roughness introduced by etching. The present invention reduces the sidewall roughness and surface waviness of the mask layer by a reflow method before completing the silicon carbide etching, optimizes the pattern on the mask layer, and avoids the conduction of the mask sidewall waviness during the pattern transfer process of the etching process, thereby reducing the sidewall roughness and surface waviness of the silicon carbide after etching. Compared with the prior art, the present invention does not require a post-etching treatment process, and can reduce or completely avoid the impact of the sidewall roughness and surface waviness of the etching mask on the sidewall roughness of the SiC trench during the etching process. The silicon carbide trench etching method provided by the present invention can improve the impact of the sidewall roughness and surface waviness of the etching mask on the sidewall roughness of the SiC trench, saving the post-etching treatment process.

[0032] 2. The material of the first mask dielectric layer is phosphosilicate glass or borophosphosilicate glass, so that the reflow temperature of the first mask dielectric layer is lower than the reflow temperature of the silicon carbide substrate. The etching selectivity ratio of the first mask dielectric layer to the silicon carbide substrate is 2:1-3:1, which can not only ensure the etching effect, but also complete the reflow operation of the mask layer at a lower temperature.

[0033] 3. Under the conditions of inert atmosphere and heating temperature of 800℃-1200℃, heat for 30min-60min to ensure that the bottom angle of the mask layer is not less than 45°. After etching, the side of the silicon carbide trench is perpendicular to the bottom of the trench to ensure the electrical performance of the device.

[0034] 4. The SiC trench etching method provided by the present invention can effectively reduce the problem of large SiC etched sidewall roughness caused by the roughness and waviness of the etch mask sidewalls. Combined with an optimized etching process, the sidewall roughness after SiC trench etching can be minimized, thereby reducing the reliance on post-etching processing and reducing the high-temperature processes experienced by the SiC substrate. On the one hand, the risk of high-temperature process damage to the surface material structure is reduced, and on the other hand, the processing equipment requirements are reduced, thereby reducing process costs.

[0035] Other features and advantages of the present invention will be described in the following description, and part of them will become obvious from the description, or will be understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the written description and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The accompanying drawings are only for the purpose of illustrating particular embodiments and are not to be considered limiting of the present invention. Like reference symbols denote like parts throughout the drawings.

[0037] Figure 1 A schematic structural diagram of the first mask dielectric layer before and after reflow provided by an embodiment of the present invention;

[0038] Figure 2 for Figure 1 A partial enlarged view of the middle C section;

[0039] Figure 3 A flowchart of a SiC trench etching method provided in an embodiment of the present invention;

[0040] Figure 4 Schematic diagram of the mask structure of the SiC trench etching process provided by an embodiment of the present invention;

[0041] Figure 5 This is an electron microscope image of the SiC etching sidewall morphology of the comparative example;

[0042] Figure 6 The electron microscope images of the SiC etching sidewall morphology of Examples 1-5.

[0043] Reference numerals:

[0044] 1-first mask dielectric layer; 2-silicon carbide substrate; 3-second mask dielectric layer; A-bottom angle of mask before reflow; B-bottom angle of mask after reflow. DETAILED DESCRIPTION

[0045] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely illustrative and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0046] Among silicon carbide devices, the MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is one of the most important power device structures and is the key to SiC chip material technology and SiC power device applications. The latest development trend of silicon carbide MOSFET is to adopt a trench gate structure instead of a planar gate structure. This is because the trench gate device structure theoretically has lower on-resistance and higher integration density than the planar gate structure, so it has more important application prospects in high-voltage and high-power devices.

[0047] For SiC trench MOSFETs, the conductive channel is located on the sidewalls of the etched gate trench. This results in a sidewall roughness significantly higher than that of the epitaxially grown and polished wafer surface. Excessive roughness reduces the mobility of the conductive channel and gate oxide reliability, further impacting the actual performance of the SiC trench MOSFET. Therefore, reducing sidewall roughness is a key process in determining the performance of SiC trench MOSFETs.

[0048] The roughness of the trench sidewalls in the SiC etching process mainly comes from two aspects: first, the reactants react with the sidewall surface during the etching process, and the surface roughness increases due to the different reaction processes; second, during the pattern transfer process of the etching process, the sidewall roughness of the etching mask itself is transferred to the SiC trench sidewalls. In addition, the line width roughness (LWR) inherent in the photolithography process causes surface ripples on the surface of the etching mask. During the pattern transfer process of the etching process, these ripples are also transferred to the SiC trench sidewalls, thereby increasing the roughness of the SiC trench sidewalls.

[0049] Existing techniques for reducing trench sidewall roughness typically involve introducing elements such as C and H during the etching process to form a passivation layer on the sidewalls, reducing the impact of the etching reaction on the sidewalls. However, this approach cannot alter the effects of the etch mask's sidewall roughness and surface waviness on the SiC trench sidewall roughness.

[0050] To address the impact of the etch mask's sidewall roughness and surface waviness on SiC trench sidewall roughness, existing technologies typically employ a post-etch treatment process. This involves reconstructing the SiC material surface at high temperatures (typically 1500-1700°C) under a protective gas atmosphere to reduce the roughness introduced by etching. However, this method often requires temperatures that are critical to or exceed the sublimation temperature of Si, which can easily cause amorphization of the SiC surface structure. Furthermore, these high temperatures place higher demands on process equipment capabilities.

[0051] In order to better solve the problem of trench sidewall roughness in SiC etching process, an embodiment of the present invention provides a SiC trench etching method, such as Figure 3 Shown, including:

[0052] Step 1: Prepare a patterned mask layer on the surface of the silicon carbide substrate.

[0053] Step 2: Optimize the graphics of the mask layer.

[0054] Step 3: Etching the silicon carbide substrate using the pattern-optimized mask layer.

[0055] Specifically, the method includes the following steps:

[0056] Step 1: Prepare a mask layer on a silicon carbide substrate.

[0057] In the embodiment of the present invention, Figure 4 As shown, along the direction away from the upper surface of the silicon carbide substrate 2 , the mask layer upwards sequentially includes: a first mask dielectric layer 1 and a second mask dielectric layer 3 .

[0058] Step 2: patterning the second mask dielectric layer.

[0059] Step 3: Etch the first mask dielectric layer using the second mask dielectric layer as a mask to transfer the pattern on the second mask dielectric layer to the first mask dielectric layer; after completing the patterning of the first mask dielectric layer, remove the remaining second mask dielectric layer and clean the substrate.

[0060] Step 4: Use a reflow process to adjust the morphology of the first mask dielectric layer.

[0061] In an embodiment of the present invention, a reflow operation is used to eliminate the sidewall roughness of the mask itself, thereby controlling the transfer of the sidewall roughness from the mask to the sidewall of the silicon carbide trench from the source. To achieve the above purpose, the material of the first mask dielectric layer must meet the following requirements:

[0062] First, the first mask dielectric layer can be subjected to a reflow operation, and the reflow temperature is lower than the crystal reconstruction temperature of silicon carbide.

[0063] The ability to reflow means that the mask is made of an amorphous material or a crystalline material that does not melt during the crystal remodeling process, ensuring that the mask's morphology and the topography of the pattern on the mask remain unchanged during the reflow process. Because the reflow temperature is lower than the crystal remodeling temperature of silicon carbide, meaning it is far lower than the post-etching treatment temperature (1500-1700°C) typically used in prior art, the present invention also saves energy and production costs.

[0064] Specifically, for the crystalline material melted during the crystal reconstruction process, the physical form and surface atomic or molecular arrangement of the crystalline material remain unchanged until the temperature reaches the melting point, so the mask sidewall roughness does not change significantly. When the temperature reaches the melting point, the crystal changes from solid to liquid, and the mask sidewall roughness decreases. However, the pattern on the mask will also undergo uncontrollable changes as the physical form of the crystal changes, and may even affect the subsequent etching accuracy and pattern morphology.

[0065] From a microscopic perspective, the roughness of a material's surface is caused by the uneven distribution of atoms or molecules. Therefore, for crystalline materials that do not melt during the crystal reconstruction process, such as silicon carbide, although the physical morphology of the material does not change during the reflow process, the crystal reconstruction causes the atoms or molecules on the surface to rearrange themselves, making the distribution of atoms or molecules on the surface more uniform, thereby eliminating the sidewall roughness of the mask itself. At the same time, since the physical morphology of the material does not change, the pattern on the mask will not change at all. Therefore, in an embodiment of the present invention, a crystal that undergoes crystal reconstruction before melting can be used as a material for making a mask.

[0066] From a macroscopic perspective, the roughness of the mask layer's sidewalls is caused by internal stress in the material. Therefore, for amorphous materials, the rough areas on the surface resemble wrinkles. When the amorphous material softens, gravity and tension pull on the rough areas, eliminating the sidewall roughness. Furthermore, as long as the temperature is properly controlled, the amorphous material only softens, not melts. In this case, the pattern changes on the mask can be controlled, for example, by controlling the reflow temperature and time to control the bottom angle of the mask.

[0067] Second, the first mask dielectric layer and the silicon carbide substrate have a suitable etching selectivity ratio.

[0068] In the etching process, the main function of the mask layer is to protect the non-groove areas of the silicon carbide substrate from being etched. Therefore, the material of the mask layer must meet the requirements of the etching process in addition to meeting the first requirement.

[0069] Based on the above reasons, the present invention selects phosphosilicate glass or borophosphosilicate glass as the material for the first mask dielectric layer. Furthermore, the etching selectivity ratio of the first mask dielectric layer to the silicon carbide substrate is determined to be between 2 and 3, and the thickness ratio of the first mask dielectric layer to the silicon carbide substrate is determined to be 1:2.

[0070] Step 5: Etch the silicon carbide substrate using the first mask dielectric layer as a mask to form a desired trench structure.

[0071] For the reflow process based on crystal reconstruction, since the physical form of the crystal does not change, the reflow process will not change the form of the mask and the pattern on the mask will basically not change.

[0072] For the reflow process that eliminates internal stress, since the amorphous material softens due to heat, the reflow process will change the morphology of the mask and the pattern on the mask, thereby affecting the morphology of the groove on the silicon carbide. Specifically, Figure 1 and Figure 2 As shown, the first mask dielectric layer 1 is placed on the upper surface of the silicon carbide substrate 2. The solid line represents the morphology of the mask before reflow and the morphology of the pattern on the mask, and the dotted line represents the morphology of the mask after reflow and the morphology of the pattern on the mask. Figure 2 It can be seen that before reflow, the bottom angle of the mask is angle A, which is the angle formed by the solid line and the silicon carbide substrate 2. After reflow, the amorphous material softens, and under the action of gravity, the bottom angle of the mask changes to angle B, which is the angle formed by the dashed line and the silicon carbide substrate 2. Obviously, the pattern on the mask changes before and after reflow, which will result in not obtaining the preset pattern when etching on the wafer.

[0073] In an embodiment of the present invention, the sidewalls of the trench are required to be perpendicular to the bottom surface of the trench. However, the reflow process causes the pattern on the mask to change. Therefore, the bottom angle of the mask is controlled by controlling the reflow temperature and reflow time to obtain the above-mentioned trench. Specifically, when the material of the first mask dielectric layer is phosphosilicate glass or borophosphosilicate glass, under an inert atmosphere and a heating temperature of 800°C-1200°C (such as 850°C, 900°C, 950°C, 1000°C, 1050°C, 1100°C, etc.), heating for 30min-60min (such as 35min, 40min, 45min, 50min, etc.) obtains a first mask dielectric layer with a bottom angle of not less than 45° (such as 55°, 60°, 65°, 70°, 75°, 80°, 85°, etc.), thereby ensuring that a trench with sidewalls perpendicular to the bottom surface is obtained when silicon carbide is subsequently etched.

[0074] In addition, the prior art reconstructs the surface of the SiC material through high temperature after the etching of the silicon carbide matrix is ​​completed to reduce the roughness of the groove sidewalls. The above approach requires strict temperature requirements. Once the temperature is not well controlled, it will inevitably cause the pattern on the silicon carbide substrate to change. Once the pattern changes, it affects the electrical performance of the device and even makes the entire device unusable. Therefore, the prior art has extremely stringent requirements on temperature and time. Once improper, it will cause irreparable losses. The present invention only reflows the first mask dielectric layer. Once the temperature and time are not well controlled, only the mask layer will be lost. In comparison, the reflow process of the present invention is not so stringent in terms of temperature and time, so the applicability of the overall process is stronger than that of the prior art.

[0075] In order to demonstrate the feasibility of the above solution, the present invention provides the following examples: The following examples and comparative examples are all processes for etching a 1 μm deep SiC trench structure.

[0076] Example 1

[0077] Step 1: Grow a first mask dielectric layer and a second mask dielectric layer on a silicon carbide substrate. The first mask dielectric layer is made of borophosphosilicate glass (BPSG), and the second mask dielectric layer is made of photoresist (PR). The thickness of the first mask dielectric layer is 0.5 μm, and the thickness of the second mask dielectric layer is 1.2 μm. The first mask layer is formed by CVD, and the second mask layer is formed by spin-on curing.

[0078] Step 2: forming a desired pattern on the second mask dielectric layer through processes such as photolithography and development.

[0079] Step 3: Transfer the pattern on the second mask dielectric layer to the first mask dielectric layer through an etching process.

[0080] In the embodiment of the present invention, the first mask dielectric layer obtained in step 3 also has the problems of rough sidewalls and surface ripples.

[0081] Step 4: After removing the second mask dielectric layer, a high-temperature reflow process is performed, with a reflow temperature of 810° C. and a reflow time of 58 minutes. The reflow process is performed in an Ar atmosphere.

[0082] In the embodiment of the present invention, the morphology of the mask layer changes due to the tension of the fluid during the reflow process, and the lines on the sidewalls are smoothed until they disappear. At the same time, under the process conditions, the bottom angle of the mask is about 80 degrees.

[0083] Step 5: Using the first mask dielectric layer obtained in step 4 as a mask, SiC is etched to form a SiC trench structure.

[0084] Example 2

[0085] Step 1: Grow a first mask dielectric layer and a second mask dielectric layer on a silicon carbide substrate. The first mask dielectric layer is made of borophosphosilicate glass (BPSG), and the second mask dielectric layer is made of photoresist (PR). The thickness of the first mask dielectric layer is 0.6 μm, and the thickness of the second mask dielectric layer is 1.5 μm. The first mask layer is formed by CVD, and the second mask layer is formed by spin-on curing.

[0086] Step 2: forming a desired pattern on the second mask dielectric layer through processes such as photolithography and development.

[0087] Step 3: Transfer the pattern on the second mask dielectric layer to the first mask dielectric layer through an etching process.

[0088] In the embodiment of the present invention, the first mask dielectric layer obtained in step 3 also has the problems of rough sidewalls and surface ripples.

[0089] Step 4: After removing the second mask dielectric layer, a high-temperature reflow process is performed with a reflow temperature of 950° C. and a reflow time of 45 minutes. The reflow process is performed in an Ar atmosphere.

[0090] In the embodiment of the present invention, the morphology of the mask layer changes due to the tension of the fluid during the reflow process, and the lines on the sidewalls are smoothed until they disappear. At the same time, under the process conditions, the bottom angle of the mask is about 75 degrees.

[0091] Step 5: Using the first mask dielectric layer obtained in step 4 as a mask, SiC is etched to form a SiC trench structure.

[0092] Example 3

[0093] Step 1: Grow a first mask dielectric layer and a second mask dielectric layer on a silicon carbide substrate. The first mask dielectric layer is made of borophosphosilicate glass (BPSG), and the second mask dielectric layer is made of photoresist (PR). The thickness of the first mask dielectric layer is 0.7 μm, and the thickness of the second mask dielectric layer is 1.8 μm. The first mask layer is formed by CVD, and the second mask layer is formed by spin-on curing.

[0094] Step 2: forming a desired pattern on the second mask dielectric layer through processes such as photolithography and development.

[0095] Step 3: Transfer the pattern on the second mask dielectric layer to the first mask dielectric layer through an etching process.

[0096] In the embodiment of the present invention, the first mask dielectric layer obtained in step 3 also has the problems of rough sidewalls and surface ripples.

[0097] Step 4: After removing the second mask dielectric layer, a high-temperature reflow process is performed with a reflow temperature of 1090° C. and a reflow time of 33 minutes. The reflow process is performed in an Ar atmosphere.

[0098] In the embodiment of the present invention, the morphology of the mask layer changes due to the tension of the fluid during the reflow process, and the lines on the sidewalls are smoothed until they disappear. At the same time, under the process conditions, the bottom angle of the mask is about 70 degrees.

[0099] Step 5: Using the first mask dielectric layer obtained in step 4 as a mask, SiC is etched to form a SiC trench structure.

[0100] Example 4

[0101] Step 1: Grow a first mask dielectric layer and a second mask dielectric layer on a silicon carbide substrate. The first mask dielectric layer uses phosphosilicate glass (PSG), and the second mask dielectric layer uses photoresist (PR). The thickness of the first mask dielectric layer is 0.6 μm, and the thickness of the second mask dielectric layer is 1.5 μm. The first mask dielectric layer is formed by CVD, and the second mask dielectric layer is formed by spin-on curing.

[0102] Step 2: forming a desired pattern on the second mask dielectric layer through processes such as photolithography and development.

[0103] Step 3: Transfer the pattern on the second mask dielectric layer to the first mask dielectric layer through an etching process.

[0104] In the embodiment of the present invention, the first mask dielectric layer obtained in step 3 also has the problems of rough sidewalls and surface ripples.

[0105] Step 4: After removing the second mask dielectric layer, a high-temperature reflow process is performed, with a reflow temperature of 1010° C. and a reflow time of 59 minutes. The reflow process is performed in an Ar atmosphere.

[0106] In the embodiment of the present invention, the morphology of the mask layer changes due to the tension of the fluid during the reflow process, and the lines on the sidewalls are smoothed until they disappear. At the same time, under the process conditions, the bottom angle of the mask is about 75 degrees.

[0107] Step 5: Using the first mask dielectric layer obtained in step 4 as a mask, SiC is etched to form a SiC trench structure.

[0108] Example 5

[0109] Step 1: Grow a first mask dielectric layer and a second mask dielectric layer on a silicon carbide substrate. The first mask dielectric layer uses phosphosilicate glass (PSG), and the second mask dielectric layer uses photoresist (PR). The thickness of the first mask dielectric layer is 0.7 μm, and the thickness of the second mask dielectric layer is 1.8 μm. The first mask layer is formed by CVD, and the second mask layer is formed by spin-on curing.

[0110] Step 2: forming a desired pattern on the second mask dielectric layer through processes such as photolithography and development.

[0111] Step 3: Transfer the pattern on the second mask dielectric layer to the first mask dielectric layer through an etching process.

[0112] In the embodiment of the present invention, the first mask dielectric layer obtained in step 3 also has the problems of rough sidewalls and surface ripples.

[0113] Step 4: After removing the second mask dielectric layer, a high-temperature reflow process is performed. The reflow temperature is 1190° C., the reflow time is 32 minutes, and the reflow process is performed in an Ar atmosphere.

[0114] In the embodiment of the present invention, the morphology of the mask layer changes due to the tension of the fluid during the reflow process, and the lines on the sidewalls are smoothed until they disappear. At the same time, under the process conditions, the bottom angle of the mask is about 70 degrees.

[0115] Step 5: Using the first mask dielectric layer obtained in step 4 as a mask, SiC is etched to form a SiC trench structure.

[0116] Comparative Example

[0117] Step 1: growing a first mask dielectric layer and a second mask dielectric layer on a silicon carbide substrate, wherein the first mask dielectric layer is made of nickel and the second mask dielectric layer is made of photoresist (PR);

[0118] Step 2: forming a desired pattern on the second mask dielectric layer through processes such as photolithography and development;

[0119] Step 3: Transfer the pattern on the second mask dielectric layer to the mask layer through an etching process.

[0120] Step 4: using the first mask dielectric layer obtained in step 3 as a mask to etch SiC to form a SiC trench structure.

[0121] The groove sidewall surfaces of Examples 1-5 and the comparative example were observed respectively, and the morphology of the groove sidewall surface was as follows: Figure 5 and Figure 6 As shown. Figure 6 The morphology of the groove sidewall surface of Examples 1-5 is shown in FIG. Figure 5 This is the morphology of the trench sidewall surface in the comparative example. Figure 5 The obvious stripes and white spots in the sample indicate that the groove sidewalls of the comparative example are very rough and have surface ripples. Figure 6 The stripes are not obvious and there are almost no white spots. It can be seen that after the reflow process, the technical solution provided by the present invention can indeed reduce the roughness of the groove sidewalls and reduce the surface ripples compared to the groove sidewalls of the comparative example.

[0122] The above description is only a preferred specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with this technical field within the technical scope disclosed by the present invention should be covered by the scope of protection of the present invention.

Claims

1. A SiC trench etching method, characterized in that: include: Step 1: preparing a mask layer on a silicon carbide substrate, wherein the mask layer includes, in a direction away from the surface of the silicon carbide substrate, a first mask dielectric layer and a second mask dielectric layer; Step 2: patterning the second mask dielectric layer; Step 3: Etching the first mask dielectric layer using the second mask dielectric layer as a mask to transfer the pattern on the second mask dielectric layer to the first mask dielectric layer; after completing the patterning of the first mask dielectric layer, removing the remaining second mask dielectric layer and cleaning the substrate; Step 4: Adjust the morphology of the first mask dielectric layer using a reflow process; before completing the silicon carbide etching, the sidewall roughness and surface waviness of the mask layer are reduced by the reflow method, the pattern on the mask layer is optimized, and the conduction of the mask sidewall waviness during the pattern transfer process of the etching process is avoided, thereby reducing the sidewall roughness and surface waviness of the silicon carbide after etching; Step 5: etching the silicon carbide substrate using the first mask dielectric layer as a mask to form a desired trench structure; The etching selectivity ratio of the first mask dielectric layer to the silicon carbide substrate is 2-3; The thickness ratio of the first mask dielectric layer to the second mask dielectric layer is 1:2-1:3; The step 4 comprises: heating for 30 minutes to 60 minutes under the conditions of an inert atmosphere and a heating temperature of 800° C. to 1200° C.

2. The method according to claim 1, characterized in that The material of the first mask dielectric layer is amorphous, and the reflow temperature of the first mask dielectric layer is lower than the crystal reconstruction temperature of the silicon carbide matrix.

3. The method according to claim 2, characterized in that The material of the first mask dielectric layer is phosphosilicate glass or borophosphosilicate glass.

4. The method according to claim 1, wherein The etching selection ratio of the first mask dielectric layer to the silicon carbide substrate is 2-3, and the thickness ratio of the first mask dielectric layer to the silicon carbide substrate is 1:

2.

5. The method according to claim 1, wherein The bottom angle of the first mask dielectric layer after reflow is not less than 45°.

6. The method according to claim 1, characterized in that After etching is completed, the side surfaces of the silicon carbide trench are perpendicular to the bottom surface of the trench.

7. The method according to claim 1, characterized in that The material of the first mask dielectric layer is a crystal having multiple crystal structures, and the crystal does not melt during the crystal reconstruction process.

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