Method for forming embedded epitaxial layers

Abstract

This application discloses a method for forming an embedded epitaxial layer, comprising: forming a groove in a silicon substrate between gate structures, wherein the gate structures are formed on the silicon substrate and sidewall structures are formed on both sides of the gate structures; growing a silicon thin film layer on the silicon substrate between the gate structures, wherein the silicon thin film layer fills the groove; growing a silicon phosphate layer on the silicon thin film layer between the gate structures, wherein hydrogen chloride gas is introduced during the growth of the silicon phosphate layer to suppress the formation of the silicon phosphate layer on the sidewall structures. This application, by forming the gate structure and the sidewall structures on both sides of the gate structure, forming a groove in the silicon substrate between the gate structures, growing a silicon thin film layer between the gate structures, and growing a silicon phosphate layer between the gate structures, allows the silicon thin film layer to fill the groove and cover the bottom of the sidewalls, thereby protecting the bottom of the sidewalls from damage by the introduced hydrogen chloride gas during the growth of the silicon phosphate layer, thus improving the reliability of the device.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and specifically to a method for forming an embedded epitaxial layer. Background Technology

[0002] In the post-processing of high-k metal gates (hereinafter referred to as "high-k metal gates"), embedded epitaxial layers are usually formed between the gate structures to reduce the source-drain (SD) contact resistance of the device and increase the saturation drive current of the device.

[0003] In related technologies, the formation process of embedded epitaxial layers is divided into two stages: in the first stage, a thin silicon layer L1 without phosphorus (P) is grown on the silicon substrate between the gate structure; in the second stage, a silicon phosphide (SiP) layer L2 is grown.

[0004] Typically, hydrogen chloride (HCl) gas is used during the growth of the silicon phosphate layer to inhibit its formation on the protective layer. However, HCl gas can damage the bottom sidewalls of the gate structure, leading to an uncontrollable decrease in the distance between the silicon phosphate layer and the gate structure. This increases leakage current and the risk of source-drain punch-through, reducing device reliability.

[0005] Therefore, there is an urgent need to provide a method for forming an embedded epitaxial layer that can solve the problem of hydrogen chloride gas damaging the bottom of the sidewalls without reducing the amount of hydrogen chloride gas. Summary of the Invention

[0006] This application provides a method for forming an embedded epitaxial layer, which can solve the problem that the sidewall bottom is damaged due to the introduction of hydrogen chloride gas in the method for forming an embedded epitaxial layer provided in the related art. The method includes:

[0007] A recess is formed in a silicon substrate between gate structures, the gate structures being formed on the silicon substrate, and sidewall structures are formed on both sides of the gate structures;

[0008] A silicon thin film layer is grown on a silicon substrate between the gate structures, and the silicon thin film layer fills the groove.

[0009] A silicon phosphate layer is grown on the silicon thin film layer between the gate structures. During the growth of the silicon phosphate layer, hydrogen chloride gas is introduced to inhibit the formation of the silicon phosphate layer on the sidewall structure.

[0010] In some embodiments, after a groove is formed in the silicon substrate between the gate structures, the cross-section of the groove surface is arc-shaped.

[0011] In some embodiments, the thickness of the silicon thin film layer is less than 50 angstroms.

[0012] In some embodiments, the temperature during the growth of the phosphosilicate layer is 600 to 700 degrees Celsius.

[0013] In some embodiments, the sidewall structure includes a first sidewall, a second sidewall, and a third sidewall from the inside out.

[0014] The third sidewall includes a silicon nitride layer.

[0015] In some embodiments, the first sidewall includes a silicon carbide layer.

[0016] In some embodiments, the second sidewall includes a silicon dioxide layer.

[0017] In some embodiments, the gate structure comprises, from bottom to top, a gate dielectric layer, a polysilicon layer, a first hard mask layer, and a second hard mask layer.

[0018] In some embodiments, the first hard mask layer includes a silicon nitride layer.

[0019] In some embodiments, the second hard mask layer includes a silicon dioxide layer.

[0020] The technical solution of this application has at least the following advantages:

[0021] In the post-processing of high-k metal gates, after forming the gate structure and the sidewall structures on both sides of the gate structure, a groove is formed in the silicon substrate between the gate structures, a silicon thin film layer is grown between the gate structures, and a silicon phosphate layer is grown between the gate structures. Since the thickness of the silicon thin film layer can fill the groove, the silicon thin film layer can cover the bottom of the sidewall, thereby protecting the bottom of the sidewall from damage caused by the hydrogen chloride gas introduced during the growth of the silicon phosphate layer, thus improving the reliability of the device. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0023] Figure 1 This is a flowchart of a method for forming an embedded epitaxial layer provided in an exemplary embodiment of this application;

[0024] Figures 2 to 5 This is a schematic diagram illustrating the formation of an embedded epitaxial layer provided in an exemplary embodiment of this application. Detailed Implementation

[0025] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0027] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to the internal connection between two components; and they can refer to wireless connections or wired connections. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0028] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0029] refer to Figure 1 This document illustrates a flowchart of a method for forming an embedded epitaxial layer according to an exemplary embodiment of this application. This method is applied in a post-processing step involving a high-k metal gate, which is used in a metal-oxide-semiconductor field-effect transistor (MOSFET, hereinafter referred to as "MOS") device. Figure 1 As shown, the method includes:

[0030] Step S1: A groove is formed in the silicon substrate between the gate structures. The gate structures are formed on the silicon substrate, and sidewall structures are formed on both sides of the gate structures.

[0031] refer to Figure 2 It shows a schematic cross-sectional view prior to the formation of grooves in the silicon substrate between the gate structures; Reference Figure 3It shows a schematic cross-sectional view after a groove is formed in the silicon substrate between the gate structures.

[0032] For example, such as Figure 2 As shown: Multiple gate structures are formed on the silicon substrate 210. Figure 2 (Using two gate structures as an example), sidewall structures are formed on both sides of the gate structures, wherein the outermost layer of the sidewall structure is a silicon nitride (SiN) layer. Taking a sidewall structure with three sidewall layers as an example, the sidewall structure includes a first sidewall 261, a second sidewall 262, and a third sidewall 263 from the inside out, and the third sidewall 263 includes a silicon nitride layer. Optionally, the first sidewall 261 includes a silicon carbide nitride (SiCN) layer, and the second sidewall 262 includes a silicon dioxide (SiO2) layer.

[0033] Optional, such as Figure 2 As shown, the gate structure, from bottom to top, includes a gate dielectric layer 220 (which may include a silicon dioxide layer), a polysilicon layer 230, a first hard mask layer 240, and a second hard mask layer 250. The polysilicon layer 230 can serve as a dummy gate, which will be replaced by a high-k metal gate in subsequent processes. Optionally, the first hard mask layer 240 includes a silicon nitride layer, and the second hard mask layer 250 includes a silicon dioxide layer.

[0034] For example, such as Figure 3 As shown, a groove 300 can be formed in the silicon substrate 210 between the gate structures by an etching process, and the cross section of the surface of the groove 300 is arc-shaped.

[0035] Step S2: A silicon thin film layer is grown on the silicon substrate between the gate structures, and the silicon thin film layer fills the groove.

[0036] refer to Figure 4 This illustrates a cross-sectional schematic of a silicon thin film layer grown on a silicon substrate between gate structures. For example, such as... Figure 4 As shown, a silicon thin film layer can be grown on the silicon substrate between the gate structures using an epitaxial growth process in an atmosphere free of phosphorus (e.g., phosphine). (Since the silicon thin film layer and the silicon substrate 210 are made of the same material,) Figure 4 and Figure 5 (There is no distinction made by different fillers), because the thickness of the silicon thin film layer is sufficient to fill the groove 300, its thickness on both sides of the groove 300 can cover the bottom of the sidewall structure (e.g. Figure 4 (As shown by the dashed line). Optionally, the thickness of the silicon thin film layer is less than 50 angstroms.

[0037] Step S3: A silicon phosphate layer is grown on the silicon thin film layer between the gate structures. During the growth of the silicon phosphate layer, hydrogen chloride gas is introduced to inhibit the formation of the silicon phosphate layer on the sidewall structure.

[0038] refer to Figure 5 This illustrates a cross-sectional schematic of a silicon phosphide layer grown on a silicon thin film layer between gate structures. For example, such as... Figure 5 As shown, a silicon phosphorus layer 270 can be grown on a silicon thin film layer between the gate structures via an epitaxial growth process in an atmosphere containing phosphorus gas (e.g., phosphine). During the growth of the silicon phosphorus layer 270, hydrogen chloride gas is introduced to suppress the formation of the silicon phosphorus layer on the sidewall structures. Optionally, the temperature during the growth of the silicon phosphorus layer 270 is between 600 degrees Celsius and 700 degrees Celsius.

[0039] In summary, in the embodiments of this application, after forming the gate structure and the sidewall structures on both sides of the gate structure in the post-processing of the high-k metal gate, a groove is formed in the silicon substrate between the gate structures, a silicon thin film layer is grown between the gate structures, and a silicon phosphate layer is grown between the gate structures. Since the thickness of the silicon thin film layer can fill the groove, the silicon thin film layer can cover the bottom of the sidewall, thereby protecting the bottom of the sidewall from damage caused by the hydrogen chloride gas introduced during the growth of the silicon phosphate layer, thus improving the reliability of the device.

[0040] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A method for forming an embedded epitaxial layer, characterized in that, include: A recess is formed in a silicon substrate between gate structures, the gate structures being formed on the silicon substrate, and sidewall structures are formed on both sides of the gate structures; In a phosphorus-free gas atmosphere, a silicon thin film layer is grown on a silicon substrate between the gate structures, the silicon thin film layer filling the groove and the thickness of the silicon thin film layer on both sides of the groove covering the bottom of the sidewall structure; A silicon phosphate layer is grown on the silicon thin film layer between the gate structures. During the growth of the silicon phosphate layer, hydrogen chloride gas is introduced to inhibit the formation of the silicon phosphate layer on the sidewall structure.

2. The method according to claim 1, characterized in that, After a groove is formed in the silicon substrate between the gate structures, the cross-section of the groove surface is arc-shaped.

3. The method according to claim 2, characterized in that, The thickness of the silicon thin film layer is less than 50 angstroms.

4. The method according to any one of claims 1 to 3, characterized in that, The temperature during the growth of the phosphosilicate layer is 600 to 700 degrees Celsius.

5. The method according to claim 4, characterized in that, The side wall structure includes, from the inside out, a first side wall, a second side wall, and a third side wall; The third sidewall includes a silicon nitride layer.

6. The method according to claim 5, characterized in that, The first sidewall includes a silicon carbide layer.

7. The method according to claim 6, characterized in that, The second sidewall includes a silicon dioxide layer.

8. The method according to claim 5, characterized in that, The gate structure, from bottom to top, includes a gate dielectric layer, a polysilicon layer, a first hard mask layer, and a second hard mask layer.

9. The method according to claim 8, characterized in that, The first hard mask layer includes a silicon nitride layer.

10. The method according to claim 9, characterized in that, The second hard mask layer includes a silicon dioxide layer.

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