Self-aligned double-trench shield gate IGBT structure and method of manufacturing the same

Abstract

The application discloses a self-aligned double-groove shield gate IGBT structure and a manufacturing method thereof. After forming a body region layer of a second conductive type and a source region layer of a first conductive type on a front surface of a substrate, a plurality of self-aligned gate grooves and source grooves are formed in the substrate in an alternating manner by using different etching selectivity between a first hard mask and a fourth hard mask and combining with a side wall process. A shield gate and a gate electrode are formed in the gate groove, a semiconductor layer of the second conductive type is formed in the source groove, a side wall structure is formed on the front surface of the substrate between the gate groove and the source groove, a bonding layer is formed between the side walls, and a collector region layer and a buffer region layer are further formed on a back surface of the substrate. The application can save masks, reduce a device area, further reduce resistance and parasitic capacitance, increase current and switching speed, and improve device performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a self-aligned dual-slot shielded gate IGBT (Insulated Gate Bipolar Transistor) structure and its manufacturing method. Background Technology

[0002] Compared to planar MOSFETs, trench MOSFETs offer a shorter source-drain current path, reducing on-resistance and allowing more current to flow through the switch, thus significantly reducing power loss. The trench MOSFET structure can be further used to form trench-type IGBT devices. Reducing the spacing between structures in the IGBT device allows for a smaller die area, further reducing resistance per square meter and increasing current density. However, the continuous shrinkage of the device area also increases the number of processing steps and photomasks in the manufacturing process, undoubtedly increasing manufacturing costs. Furthermore, overlay errors also increase short-circuit resistance. Summary of the Invention

[0003] The purpose of this invention is to overcome the above-mentioned defects in the prior art and provide a self-aligned dual-slot shielded gate IGBT structure and its manufacturing method.

[0004] To achieve the above objectives, the technical solution of the present invention is as follows:

[0005] This invention provides a self-aligned dual-slot shielded gate IGBT structure, comprising:

[0006] A source region layer of a first conductivity type is formed on the front surface of a substrate of a first conductivity type, and a body region layer of a second conductivity type is located below the source region layer;

[0007] An array of multiple gate trenches and source trenches that enter the substrate side-by-side from the front surface of the substrate and are formed in an alternating manner, wherein a shielding gate, an isolation layer and a gate are formed from bottom to top in the gate trenches, a gate oxide layer is formed between the shielding gate and the inner wall of the gate trench and between the gate and the inner wall of the gate trench, and a semiconductor layer of a second conductivity type is formed in the source trenches.

[0008] Multiple sidewall structures are formed on the front surface of the substrate and located between every two adjacent gate trenches and source trenches, and an adhesive layer is formed between the sidewalls;

[0009] A collector region layer of a second conductivity type is formed on the back surface of the substrate, and a buffer layer of a first conductivity type is located below the collector region layer;

[0010] The source trench is formed between each two adjacent grid trenches through an opening between each two adjacent sidewalls in a self-aligned manner.

[0011] Furthermore, the bottom end of the gate trench is located in the substrate below the body region layer, and the bottom end of the source trench is flush with or not flush with the bottom end of the gate trench.

[0012] Furthermore, the top end of the gate protrudes from the front surface of the substrate and is located between the sidewalls, while the bottom end of the gate is located in the substrate below the body layer.

[0013] Furthermore, the sidewall includes a first sidewall and a second sidewall connected together; wherein, the first sidewall is disposed adjacent to both sides of the grid trench, the second sidewall is formed on the outside of the first sidewall and adjacent to both sides of the source trench, and the horizontal width of the source region layer located between the source trench and the grid trench is determined by the horizontal width of the second sidewall.

[0014] Furthermore, it also includes a collector layer formed on the upper surface of the collector region layer.

[0015] The present invention also provides a method for manufacturing a self-aligned dual-slot shielded IGBT structure, comprising:

[0016] A substrate of a first conductivity type is provided, wherein a source region layer of the first conductivity type is formed on the front surface of the substrate and located within the front surface of the substrate, and a body region layer of the second conductivity type is formed below the source region layer.

[0017] Multiple first hard mask layer patterns are formed on the front surface of the substrate;

[0018] A second hard mask layer is formed conformally on the first hard mask layer pattern and then etched back. Second hard mask layer patterns are formed on both sides of the first hard mask layer pattern, exposing the top of the first hard mask layer pattern and the front surface of the substrate between the two second hard mask layer patterns located on adjacent sides.

[0019] A third hard mask layer is formed on the exposed front surface of the substrate, and then etched back to form a third hard mask layer pattern between two second hard mask layer patterns located on adjacent sides.

[0020] Remove the second hard mask layer pattern, and then form first sidewall structures on both sides of the first hard mask layer pattern and on both sides of the third hard mask layer pattern, respectively;

[0021] Using the first sidewall as a mask, a gate trench is formed downward on the exposed front surface of the substrate, a gate oxide layer is formed on the inner wall of the gate trench, and a shielding gate, an isolation layer and a gate are formed from bottom to top in the gate trench within the gate oxide layer.

[0022] A fourth hard mask layer is formed over the gate trench and then etched back to form a fourth hard mask layer pattern between two first sidewalls located on adjacent sides.

[0023] Remove the first hard mask layer pattern and the third hard mask layer pattern, and then form a source trench downwardly aligned between the gate trenches on the exposed front surface of the substrate, and form a semiconductor layer of a second conductivity type in the source trenches;

[0024] Remove the fourth hard mask layer pattern and cover the exposed gate trench and source trench with an adhesive layer located between the first sidewalls;

[0025] The back side of the substrate is thinned, and a collector layer of a second conductivity type is formed on the back side surface of the thinned substrate, and a buffer layer of a first conductivity type is formed below the collector layer.

[0026] Further, the step of forming a gate trench downwards on the exposed front surface of the substrate using the first sidewall as a mask, forming a gate oxide layer on the inner wall of the gate trench, and forming a shielding gate, an isolation layer, and a gate electrode from bottom to top in the gate trench within the gate oxide layer specifically includes:

[0027] Using the first sidewall, the first hard mask layer pattern, and the third hard mask layer pattern as a common mask, a gate trench is etched downwards on the front surface of the substrate exposed between the first sidewalls, and the bottom end of the gate trench is located in the substrate below the bulk layer.

[0028] A first gate oxide layer material is deposited on the inner wall of the gate trench. A shielding gate material is filled in the gate trench within the first gate oxide layer, and then etched back to form a shielding gate. Then, an isolation layer material is filled in the gate trench, and etched back to form an isolation layer. Next, a second gate oxide layer material is deposited on the inner wall of the gate trench above the isolation layer, and a gate material is filled in the gate trench within the second gate oxide layer, and etched back to form a gate. The top end of the gate protrudes from the front surface of the substrate and is located between the first sidewalls, while the bottom end of the gate is located in the substrate below the body layer. The gate oxide layer includes the first gate oxide layer and the second gate oxide layer.

[0029] Further, the process of removing the first hard mask layer pattern and the third hard mask layer pattern, then forming a self-aligned source trench between the gate trenches on the exposed front surface of the substrate, and forming a semiconductor layer of a second conductivity type in the source trenches, specifically includes:

[0030] By etching back, the first hard mask layer pattern and the third hard mask layer pattern are removed. Then, using the first sidewall and the fourth hard mask layer pattern as a common mask, a source trench self-aligned between the gate trenches is formed downward on the front surface of the substrate exposed between the first sidewalls, and the bottom end of the source trench is either flush with or not flush with the bottom end of the gate trench.

[0031] Subsequently, a semiconductor layer material is filled into the source trench, and an etch is performed to form a second type of conductive semiconductor layer in the source trench, with the top of the semiconductor layer flush with the front surface of the substrate.

[0032] Further, the process of removing the first hard mask layer pattern and the third hard mask layer pattern, then forming a self-aligned source trench between the gate trenches on the exposed front surface of the substrate, and forming a semiconductor layer of a second conductivity type in the source trenches, specifically includes:

[0033] By etching back, the first hard mask layer pattern and the third hard mask layer pattern are removed, and a second sidewall structure is formed on the outside of the first sidewall located on both sides of the fourth hard mask layer pattern.

[0034] Then, using the second sidewall, the first sidewall, and the fourth hard mask layer pattern as a common mask, a source trench self-aligned between the gate trenches is formed downward on the front surface of the substrate exposed between the second sidewalls, and the bottom end of the source trench is either flush with or not flush with the bottom end of the gate trench.

[0035] Then, semiconductor layer material is filled into the source trench and etched back to form a second type of semiconductor layer in the source trench, and the top of the semiconductor layer is made flush with the front surface of the substrate.

[0036] Specifically, when forming the second sidewall, the horizontal width of the source region layer located between the source trench and the gate trench is adjusted by adjusting the horizontal width of the second sidewall.

[0037] Furthermore, it also includes: forming a collector layer on the upper surface of the collector region layer.

[0038] As can be seen from the above technical solution, the present invention forms a second hard mask layer conformally on the first hard mask layer pattern, and forms the second hard mask layer pattern on both sides of the first hard mask layer pattern by etching back. A third hard mask layer pattern can then be formed by self-alignment between the second hard mask layer patterns. This saves one photomask, reduces the pitch, and allows the IGBT device to have a smaller die area, thereby further reducing the resistance per square meter, increasing current density, and significantly reducing cost. Simultaneously, the absence of overlay error effectively reduces short-circuit resistance. Thus, by removing the second, first, and third hard mask layer patterns stepwise, the source trench can be precisely self-aligned between the gate trenches, effectively reducing resistance, parasitic capacitance, and increasing switching speed. Furthermore, when forming the source trench, an adjustable-width second sidewall can be added outside the first sidewall to adjust the width of the source trench, thereby adjusting the horizontal width of the source region layer between the source trench and the gate trench, further improving device performance. Attached Figure Description

[0039] Figure 1 This is a schematic diagram of a self-aligned dual-slot shielded IGBT structure according to a preferred embodiment of the present invention;

[0040] Figure 2 This is a flowchart illustrating a preferred embodiment of the manufacturing method of a self-aligned dual-slot shielded IGBT structure.

[0041] Figures 3-9 According to a preferred embodiment of the present invention Figure 2 A schematic diagram of the process steps for manufacturing a self-aligned dual-slot shielded IGBT structure. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art. The terms "comprising" and similar expressions used herein mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, but does not exclude other elements or objects.

[0043] Unless otherwise specified below, the various parts of an IGBT device may be made of materials known to those skilled in the art. Semiconductor materials may include, for example, group III-V semiconductors such as GaAs, InP, GaN, and SiC, and group IV semiconductors such as Si and Ge. The gate conductor may be formed of various conductive materials, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor comprising a metal layer and a doped polysilicon layer, or other conductive materials such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, and PtSi. x The gate dielectric can be composed of materials such as Ni3Si, Pt, Ru, W, and combinations thereof. The gate dielectric can be made of SiO2 or materials with a dielectric constant greater than SiO2, including, for example, oxides, nitrides, oxynitrides, silicates, aluminates, titanates, etc. Furthermore, the gate dielectric can be formed not only of materials known to those skilled in the art, but also of materials developed in the future for use as gate dielectrics.

[0044] The first conductivity type can be either N-type or P-type, and the second conductivity type can be the other of N-type and P-type. N-type conductivity can be formed by implanting N-type dopants (e.g., P, As, etc.) into the semiconductor material. P-type conductivity can be formed by implanting P-type dopants (e.g., B, etc.) into the semiconductor material. The above can be understood with reference to known technologies.

[0045] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0046] Please see Figure 1 , Figure 1 This is a schematic diagram of a self-aligned dual-slot shielded IGBT structure according to a preferred embodiment of the present invention. Figure 1 As shown, a self-aligned dual-slot shielded IGBT structure of the present invention includes:

[0047] A source region layer 14 of the first conductivity type is formed on the front surface 111 of the substrate 11 of the first conductivity type, and a body region layer 13 of the second conductivity type is located below the source region layer 14; an array of multiple gate trenches 12 and source trenches 19 are formed alternately and side by side from the front surface 111 of the substrate 11. A shielding gate 122, an isolation layer 123, and a gate 124 are formed from bottom to top in the gate trenches 12. The shielding gate 122 is connected to the inner wall of the gate trench 12, and the gate 124 is connected to the inner wall of the gate trench 12. A gate oxide layer 121 is formed between the inner walls of the trench 12, and a semiconductor layer 191 of a second conductivity type is formed in the source trench 19; a plurality of sidewall 15 structures protruding from the front surface 111 of the substrate 11 and located between every two adjacent gate trenches 12 and source trenches 19, and an adhesive layer 18 formed between the sidewalls 15; and a collector layer 21 of a second conductivity type formed on the back surface 112 of the substrate 11, and a buffer layer 20 of a first conductivity type located below the collector layer 21.

[0048] The source trench 19 is formed between each two adjacent grid trenches 12 through an opening between each two adjacent sidewalls 15.

[0049] The gate oxide layer 121 may include a first gate oxide layer 1211 formed between the shielding gate 122 and the inner wall of the gate trench 12, and a second gate oxide layer 1212 formed between the gate 124 and the inner wall (sidewall) of the gate trench 12.

[0050] Please see Figure 1 In a preferred embodiment, the substrate 11 may be a lightly doped N-type silicon substrate of the first conductivity type (N-substrate).

[0051] The body layer 13 can be a second conductivity type body layer 13 (P-body) with light P-type doping in the front side of the substrate 11.

[0052] The source layer 14 is located within the front surface 111 of the substrate 11 and is located above the bulk layer 13; the source layer 14 may be a first type of source layer 14 that is N+ type heavily doped in the substrate 11 by implantation.

[0053] In a preferred embodiment, the gate 124 may be an N+ type heavily doped polysilicon gate 124 of the first conductivity type.

[0054] In a preferred embodiment, the shielding gate 122 may be an N+ type heavily doped polysilicon shielding gate 122 of the first conductivity type (poly 1).

[0055] Semiconductor layer 191 serves as the source contact conductor and can be a second type of conductivity semiconductor layer 191 doped with P-type.

[0056] In a preferred embodiment, the semiconductor layer 191 may be an epitaxial single-crystal silicon layer grown in the source trench 19 and p-type doped, i.e., the semiconductor layer 191 may be a p-type doped epitaxial single-crystal silicon layer (PEPI).

[0057] In a preferred embodiment, the adhesive layer 18 may be made of at least one material selected from Ti, TiN and TaN.

[0058] The sidewall 15 can be made from conventional materials used in the sidewall process.

[0059] The buffer layer 20 may be a first conductivity type buffer layer 20 formed by N+ type heavy doping on the back side of the substrate 11. For example, the buffer layer 20 may be a first conductivity type buffer layer 20 (N+H) formed by H implantation on the back side of the substrate 11.

[0060] The collector layer 21 is located within the back surface 112 of the substrate 11 and is located above the buffer layer 20. The collector layer 21 can be a second conductivity type collector layer 21 that is heavily doped with P+ type in the substrate 11 by implantation. For example, the collector layer 21 can be a second conductivity type collector layer 21 that is heavily doped with P+ type by B implantation.

[0061] In a preferred embodiment, a collector layer 22 is further formed on the upper surface of the collector region layer 21. The collector layer 22 may be fabricated using at least one of Al, Ti, NiV, Ag, etc.

[0062] In a preferred embodiment, other structures of the device may also be formed on the front surfaces of the sidewall 15 and the adhesive layer 18, as can be understood with reference to the prior art.

[0063] Please see Figure 1 In a preferred embodiment, the bottom ends of the gate trench 12 and the source trench 19 are disposed in the substrate 11 below the body layer 13. The bottom end of the source trench 19 may be flush with the bottom end of the gate trench 12 in the horizontal direction. Alternatively, the bottom ends of the source trench 19 and the bottom ends of the gate trench 12 may not be flush in the horizontal direction.

[0064] Gate 124 and shielding gate 122 are isolated from substrate 11 by gate oxide layer 121, and gate 124 and shielding gate 122 are isolated by isolation layer 123. A semiconductor layer 191, serving as a source contact conductor of a second conductivity type, is connected to substrate 11 to enhance the reduction of resistance and parasitic capacitance. The above-described structure of the present invention can reduce device area, provide a shorter source-drain current path, further reduce resistance per square square area, and increase current density, thereby reducing on-resistance, allowing more current to travel through the switch, and thus significantly reducing power loss.

[0065] In a preferred embodiment, the top of the gate 124 may protrude from the front surface 111 of the substrate 11 and be located between the sidewalls 15.

[0066] In a preferred embodiment, the bottom end of the gate 124 may be located in the substrate 11 below the body layer 13.

[0067] In a preferred embodiment, the sidewall 15 may include a first sidewall 16 and a second sidewall 17 connected in the horizontal direction. The first sidewall 16 is disposed adjacent to both sides of the gate trench 12; the second sidewall 17 is located outside the first sidewall 16 and adjacent to both sides of the source trench 19. Thus, the horizontal width of the source layer 14 located between the source trench 19 and the gate trench 12 can be determined by the horizontal width of the second sidewall 17. Whether to include the second sidewall 17 structure and the width of the second sidewall 17 can be determined according to design requirements.

[0068] The following describes in detail, with reference to the accompanying drawings, a method for manufacturing a self-aligned dual-slot shielded IGBT structure according to the present invention.

[0069] The present invention provides a method for manufacturing a self-aligned dual-slot shielded IGBT structure, which can be used to manufacture the aforementioned... Figure 1 A self-aligned dual-slot shielded IGBT structure, the method may include the following steps:

[0070] Step S1: Provide a substrate of a first conductivity type, form a source region layer of the first conductivity type located within the front surface of the substrate on the front surface of the substrate, and form a body region layer of the second conductivity type located below the source region layer.

[0071] Please see Figure 3 In a preferred embodiment, a silicon substrate 11 of the first conductivity type, lightly doped with N-type, may be used. The silicon substrate 11 may be lightly doped with N-type, for example, by an ion implantation process.

[0072] In a preferred embodiment, an ion implantation process can be used to perform P-type light doping from the front surface 111 of the substrate 11 into the substrate 11 to form a bulk layer 13 of the second conductivity type.

[0073] Next, an ion implantation process can be used to perform N+ type heavy doping from the front surface 111 of the substrate 11 to the substrate 11, forming a source layer 14 of the first conductivity type on the front surface 111 of the substrate 11 above the bulk layer 13.

[0074] Step S2: Form multiple first hard mask layer patterns on the front surface of the substrate.

[0075] Please see Figure 3 In a preferred embodiment, a first hard mask layer material is deposited all over the front surface 111 of the substrate 11. Then, a photoresist layer is formed on the first hard mask layer. Next, a plurality of first hard mask layer patterns 23 (HM1) are formed on the front surface 111 of the substrate 11 by photolithography and etching. Afterward, any remaining photoresist on the first hard mask layer patterns 23 is removed.

[0076] The first hard mask layer material can be a conventional hard mask layer material. For example, the first hard mask layer material can be one or more of silicon nitride, silicon carbide, silicon oxynitride, and silicon carbonitride.

[0077] Step S3: Conformally form a second hard mask layer on the first hard mask layer pattern, and perform an etch-back process to form second hard mask layer patterns on both sides of the first hard mask layer pattern, exposing the top of the first hard mask layer pattern and the front surface of the substrate between the two second hard mask layer patterns located on adjacent sides.

[0078] Please see Figure 4 In a preferred embodiment, a conformal CVD process can be used to conformally deposit a second hard mask layer material on the first hard mask layer pattern 23 and on the exposed front surface 111 of the substrate 11. Then, the second hard mask layer is etched back to form second hard mask layer patterns 24 (HM2) on both sides of each first hard mask layer pattern 23, exposing the top of the first hard mask layer pattern 23 and two second hard mask layer patterns 24 located on adjacent sides, that is, the front surface 111 of the substrate 11 located between two second hard mask layer patterns 24 located inside two adjacent first hard mask layer patterns 23.

[0079] When depositing the second hard mask layer, the thickness during deposition can be controlled to reserve the width for the subsequent deposition of the third hard mask layer.

[0080] The second hard mask layer material can be a conventional hard mask layer material. For example, the second hard mask layer material can be one or more of silicon nitride, silicon carbide, silicon oxynitride, and silicon carbonitride.

[0081] Step S4: A third hard mask layer is formed on the exposed front surface of the substrate, and then etched back to form a third hard mask layer pattern between two second hard mask layer patterns located on adjacent sides.

[0082] Please see Figure 4 In a preferred embodiment, a conventional process can be used to deposit a third hard mask layer material on the exposed front surface 111 of the substrate 11 between two adjacent second hard mask layer patterns 24, completely filling the gap between the two adjacent second hard mask layer patterns 24, forming a third hard mask layer covering the first hard mask layer pattern 23, the second hard mask layer pattern 24, and the front surface 111 of the substrate 11. Then, by etching back the third hard mask layer material, a third hard mask layer pattern 25 (HM3) can be formed between the two adjacent second hard mask layer patterns 24. By conformally forming the second hard mask layer on the first hard mask layer pattern 23 and forming the second hard mask layer patterns 24 on both sides of the first hard mask layer pattern 23 by etching back, the third hard mask layer pattern 25 can be formed by self-alignment between the second hard mask layer patterns 24, achieving a reduction in pitch while saving one photomask.

[0083] The third hard mask layer material can be a conventional hard mask layer material. For example, the third hard mask layer material can be one or more of silicon nitride, silicon carbide, silicon oxynitride, and silicon carbonitride.

[0084] Step S5: Remove the second hard mask layer pattern, and then form the first sidewall structure on both sides of the first hard mask layer pattern and the third hard mask layer pattern respectively.

[0085] Please see Figure 5 In a preferred embodiment, the second hard mask pattern 24 located between the first hard mask pattern 23 and the third hard mask pattern 25 can be removed by utilizing the different etching selectivity ratios between the second hard mask layer material and the first hard mask layer material and the third hard mask layer material, thereby exposing the front surface 111 of the substrate 11 located between the first hard mask pattern 23 and the third hard mask pattern 25.

[0086] Then, a sidewall process can be used to deposit sidewall material on the front surface 111 of the first hard mask layer pattern 23, the third hard mask layer pattern 25 and the exposed substrate 11, and then etch back to form a first sidewall 16 structure on both sides of each first hard mask layer pattern 23 and each third hard mask layer pattern 25.

[0087] When forming the first sidewall 16, the horizontal width of the first sidewall 16 formed by the back etching can be adjusted by controlling the deposition thickness of the first sidewall material, so as to adjust the spacing between the two first sidewalls 16 located inside the two adjacent first hard mask layer patterns 23 and third hard mask layer patterns 25, thereby realizing the adjustment of the horizontal width of the gate trench 12 formed by subsequent etching.

[0088] The sidewall 15 material can be a conventional sidewall material with a different etching selectivity ratio between the first hard mask layer material and the third hard mask layer material.

[0089] Step S6: Using the first sidewall as a mask, a gate trench is formed downward on the exposed front surface of the substrate, a gate oxide layer is formed on the inner wall of the gate trench, and a shielding gate, an isolation layer and a gate are formed from bottom to top in the gate trench inside the gate oxide layer.

[0090] Please see Figure 5 In a preferred embodiment, after the first sidewall 16 is formed, the first sidewall 16 can be used as a mask, that is, the combined pattern of the first sidewall 16 and the first hard mask layer pattern 23, and the combined pattern of the first sidewall 16 and the third hard mask layer pattern 25 can be used as a common mask to etch downwards on the front surface 111 of the substrate 11 exposed between every two adjacent first sidewalls 16, forming a plurality of deep trenches in parallel in the substrate 11 as gate trenches 12, and the bottom end of the gate trenches 12 is located in the substrate 11 below the bulk layer 13.

[0091] Then, the first gate oxide layer material is deposited on the inner wall surface of the gate trench 12 and on the surface of the first sidewall 16 and the first hard mask layer pattern 23 and the third hard mask layer pattern 25. Furthermore, the gate trench 12 within the first gate oxide layer material is filled with shielding gate material, which can fill the gap between the first sidewall 16 until the shielding gate material covers the first gate oxide layer material.

[0092] Next, a first gate oxide layer 1211 can be formed on the inner wall of the gate trench 12 by etching back the shielding gate material, and a shielding gate 122 (poly1) can be formed in the lower part of the gate trench 12 within the first gate oxide layer 1211.

[0093] When the material of the shielding gate 122 is etched back, the top of the shielding gate 122 can be positioned in the substrate 11 below the bulk layer 13 by controlling the etch-back time.

[0094] Then, the isolation layer material is filled into the gate trench 12 and etched back to form an isolation layer 123 on the top surface of the shielding gate 122.

[0095] When the material of the isolation layer 123 is etched back, the top surface of the isolation layer 123 can be positioned in the substrate 11 below the bulk layer 13 by controlling the etch-back time.

[0096] Please see Figure 6 Next, a second gate oxide layer material is deposited on the inner wall of the gate trench 12 above the isolation layer 123. Then, gate material is filled in the remaining upper part of the gate trench 12 within the second gate oxide layer material, and etched back is performed to form a second gate oxide layer 1212 on the sidewall of the gate trench 12 above the isolation layer 123, and a gate 124 (Gate poly 2) is formed in the remaining upper part of the gate trench 12 on the isolation layer 123.

[0097] When etching back the gate material, the top edges of the gate 124 and the second gate oxide layer 1212 can be controlled to protrude from the front surface 111 of the substrate 11 and be located between the first sidewalls 16, i.e., the top edges of the gate 124 and the second gate oxide layer 1212 are located below the upper end of the first sidewall 16. For example, the top edges of the gate 124 and the second gate oxide layer 1212 can be located at the middle of the height of the first sidewall 16. However, this is not a limitation.

[0098] Meanwhile, by controlling the deposition thickness of the isolation layer 123 material, the bottom end of the formed gate 124 can be located in the substrate 11 below the body layer 13.

[0099] The gate oxide layer 121 in the gate trench 12 may include a first gate oxide layer 1211 and a second gate oxide layer 1212.

[0100] The gate 124 material can be, for example, N+ heavily doped polysilicon.

[0101] Step S7: A fourth hard mask layer is formed over the grid trench and etched back to form a fourth hard mask layer pattern between two first sidewalls located on adjacent sides.

[0102] Please see Figure 6 In a preferred embodiment, a fourth hard mask layer material is deposited all over the surface of the device structure formed in the previous step to fill the gap between two adjacent first sidewalls 16 above the gate trench 12, thereby completely covering the top of the exposed gate 124 and gate oxide layer 121 on the gate trench 12.

[0103] Then, the fourth hard mask layer material is etched back to form a fourth hard mask layer pattern 26 (HM4) between the two first sidewalls 16 located on adjacent sides, that is, between the two first sidewalls 16 located inside the two adjacent first hard mask layer patterns 23 and the third hard mask layer pattern 25.

[0104] The fourth hard mask layer material can be TEOS oxide (tetraethoxysilane oxide).

[0105] Step S8: Remove the first hard mask layer pattern and the third hard mask layer pattern, and then form a self-aligned source trench between the gate trenches on the exposed front surface of the substrate, and form a semiconductor layer of a second conductivity type in the source trenches.

[0106] Please see Figure 7 In a preferred embodiment, the first hard mask layer pattern 23 and the third hard mask layer pattern 25 can be removed by etching back by utilizing the different etching selectivity ratios between the first hard mask layer material and the third hard mask layer material and the first sidewall 16 and the fourth hard mask layer material.

[0107] Then, a sidewall process can be used to further form a second sidewall 17 structure on the outside of the two first sidewalls 16 located on both sides of each fourth hard mask layer pattern 26, i.e., on both sides of each gate trench 12. The first sidewalls 16 and the second sidewalls 17 together form the sidewall 15 structure.

[0108] Next, using the second sidewall 17, the first sidewall 16, and the fourth hard mask layer pattern 26 as a common mask, multiple deep trenches self-aligned between the gate trenches 12 are formed downward on the front surface 111 of the substrate 11 exposed between every two adjacent second sidewalls 17, forming source trenches 19, and the bottom end of the source trenches 19 is either flush with or not flush with the bottom end of the gate trenches 12.

[0109] Next, semiconductor layer material is filled into the source trench 19. Then, the semiconductor layer material is etched back to form a semiconductor layer 191 in the source trench 19, and the top of the semiconductor layer 191 is flush or substantially flush with the front surface 111 of the substrate 11.

[0110] In a preferred embodiment, the semiconductor layer 191 may be filled with an epitaxial single-crystal silicon layer grown in the source trench 19 and P-type doped to have a second conductivity type.

[0111] After forming a substrate 11 of a first conductivity type, a body layer 13 of a second conductivity type, and a source layer 14 of a first conductivity type, this invention utilizes different etching selectivity ratios between a first to a fourth hard mask, combined with sidewall processes, to achieve the alternating formation of an array of self-aligned gate trenches 12 and source trenches 19 in the substrate 11. This invention not only saves on photomasks and reduces processing steps, significantly lowering manufacturing costs, but also reduces device area and eliminates overlay errors, resulting in reduced on-resistance. This allows more current to travel through the switch, thereby significantly reducing power loss.

[0112] Specifically, during the formation of the second sidewall 17, the horizontal width of the second sidewall 17 formed by the etch-back process is adjusted by controlling the deposition thickness of the second sidewall material. This adjusts the spacing between the two second sidewalls 17 located inside the two adjacent first sidewalls 16, thereby enabling the adjustment of the horizontal width of the source layer 14 located between the source trench 19 and the gate trench 12. Simultaneously, it also allows for fine-tuning of the device area.

[0113] As another specific implementation, depending on design requirements, the step of forming the second sidewall 17 can be omitted, and the width of the first sidewall 16 can be adjusted as a means of adjusting the device structure. In this case, after removing the first hard mask layer pattern 23 and the third hard mask layer pattern 25, the first sidewall 16 and the fourth hard mask layer pattern 26 are used as a common mask, and a source trench 19 self-aligned between the gate trenches 12 is formed downward on the front surface 111 of the substrate 11 exposed between the first sidewalls 16.

[0114] Step S9: Remove the fourth hard mask layer pattern and cover the exposed gate trench and source trench with an adhesive layer located between the first sidewalls.

[0115] Please see Figure 7 In a preferred embodiment, the top of the gate 124 can be exposed by etching back the fourth hard mask layer pattern 26 using the different etching selectivity ratio between the fourth hard mask layer material and the first and second sidewall materials.

[0116] Please see Figure 8 Then, an adhesive layer material is deposited all over the surface of the device structure formed above to fill the gaps between the second sidewalls 17, and then etched back to form an adhesive layer 18 between the first sidewalls 16 on the gate 124 of the exposed gate trench 12 and the conductive semiconductor layer 191 of the source trench 19.

[0117] The adhesive layer 18 located above the grid trench 12 is in direct contact with the first sidewall 16, and the adhesive layer 18 located above the source trench 19 is in direct contact with the second sidewall 17.

[0118] The adhesive layer 18 may be made of at least one material selected from Ti, TiN and TaN.

[0119] Step S10: Thin the back side of the substrate and form a collector layer of a second conductivity type on the back side surface of the thinned substrate, and form a buffer layer of a first conductivity type located below the collector layer.

[0120] Please see Figure 9In a preferred embodiment, the front side of the substrate 11 can be inverted, with the back side of the substrate 11 facing up and the front side facing down. Then, the front side of the substrate 11 can be fixed using existing techniques. For example, blue tape can be used to fix the front side of the substrate 11.

[0121] Next, the back side of the substrate 11 can be thinned using existing techniques. For example, a combination of chemical etching and mechanical polishing can be used to thin the back side of the substrate 11.

[0122] In a preferred embodiment, the back side of the substrate 11 may be thinned to the extent that the substrate 11 retains a thickness of 60 to 190 μm.

[0123] Then, a P+ type heavily doped collector layer 21 of the second conductivity type can be formed on the back surface 112 of the substrate 11 using a conventional implantation method. For example, a P+ type heavily doped collector layer 21 of the second conductivity type (P+imp) can be formed on the back surface of the substrate 11 using B implantation.

[0124] Next, a buffer layer 20 of the first conductivity type, heavily doped with N+ type, can be formed on the back side of the substrate 11 below the collector layer 21 using a conventional implantation method, progressing from deep to shallow. For example, a multi-step implantation process involving H-imp deep and H-imp shallow can be used on the back side of the substrate 11 to form the buffer layer 20 of the first conductivity type, heavily doped with N+ type. Afterward, annealing is performed. For example, furnace annealing can be used.

[0125] Finally, a collector layer 22 may be formed on the upper surface of the collector region layer 21 on the back side of the substrate 11.

[0126] In a preferred embodiment, conventional metal electrode fabrication processes can be used to deposit and pattern electrode metal on the current collector layer 21 to form the current collector layer 22. For example, at least one of Al, Ti, NiV, Ag, etc., can be used to fabricate the current collector layer 22. The final IGBT device structure is as follows: Figure 1 As shown.

[0127] In summary, this invention forms a second hard mask layer conformally on the first hard mask layer pattern 23, and forms second hard mask layer patterns 24 on both sides of the first hard mask layer pattern 23 by etching back. A third hard mask layer pattern 25 can then be formed by self-alignment between the second hard mask layer patterns 24. This saves one photomask, reduces the pitch, and allows the IGBT device to have a smaller die area, thereby further reducing the resistance per square meter, increasing current density, and significantly reducing cost. Simultaneously, the absence of overlay error effectively reduces short-circuit current. Thus, by removing the second hard mask layer pattern 24, the first hard mask layer pattern 23, and the third hard mask layer pattern 25 in stages, the source trench 19 can be precisely self-aligned between the gate trenches 12, which can effectively reduce resistance, decrease parasitic capacitance, and increase switching speed. In addition, when forming the source trench 19, an adjustable width second sidewall 17 can be added outside the first sidewall 16 to adjust the formation width of the source trench 19, thereby adjusting the horizontal width of the source region layer 14 located between the source trench 19 and the gate trench 12, thereby further improving device performance.

[0128] While embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations fall within the scope and spirit of the invention as defined in the claims. Furthermore, the invention described herein may have other embodiments and can be implemented or carried out in various ways.

Claims

1. A method for manufacturing a self-aligned dual-slot shielded IGBT structure, characterized in that, include: A substrate of a first conductivity type is provided, wherein a source region layer of the first conductivity type is formed on the front surface of the substrate and located within the front surface of the substrate, and a body region layer of the second conductivity type is formed below the source region layer. Multiple first hard mask layer patterns are formed on the front surface of the substrate; A second hard mask layer is formed conformally on the first hard mask layer pattern and then etched back. Second hard mask layer patterns are formed on both sides of the first hard mask layer pattern, exposing the top of the first hard mask layer pattern and the front surface of the substrate between the two second hard mask layer patterns located on adjacent sides. A third hard mask layer is formed on the exposed front surface of the substrate, and then etched back to form a third hard mask layer pattern between two second hard mask layer patterns located on adjacent sides. Remove the second hard mask layer pattern, and then form first sidewall structures on both sides of the first hard mask layer pattern and on both sides of the third hard mask layer pattern, respectively; Using the first sidewall as a mask, a gate trench is formed downward on the exposed front surface of the substrate, a gate oxide layer is formed on the inner wall of the gate trench, and a shielding gate, an isolation layer and a gate are formed from bottom to top in the gate trench within the gate oxide layer. A fourth hard mask layer is formed over the gate trench and then etched back to form a fourth hard mask layer pattern between two first sidewalls located on adjacent sides. Remove the first hard mask layer pattern and the third hard mask layer pattern, and then form a source trench downwardly aligned between the gate trenches on the exposed front surface of the substrate, and form a semiconductor layer of a second conductivity type in the source trenches; Remove the fourth hard mask layer pattern and cover the exposed gate trench and source trench with an adhesive layer located between the first sidewalls; The back side of the substrate is thinned, and a collector layer of a second conductivity type is formed on the back side surface of the thinned substrate, and a buffer layer of a first conductivity type is formed below the collector layer.

2. The manufacturing method of the self-aligned dual-slot shielded IGBT structure according to claim 1, characterized in that, The method of forming a gate trench downwards on the exposed front surface of the substrate using the first sidewall as a mask, forming a gate oxide layer on the inner wall of the gate trench, and forming a shielding gate, an isolation layer, and a gate electrode from bottom to top in the gate trench within the gate oxide layer, specifically includes: Using the first sidewall, the first hard mask layer pattern, and the third hard mask layer pattern as a common mask, a gate trench is etched downwards on the front surface of the substrate exposed between the first sidewalls, and the bottom end of the gate trench is located in the substrate below the bulk layer. A first gate oxide layer material is deposited on the inner wall of the gate trench. A shielding gate material is filled in the gate trench within the first gate oxide layer, and then etched back to form a shielding gate. Then, an isolation layer material is filled in the gate trench, and etched back to form an isolation layer. Next, a second gate oxide layer material is deposited on the inner wall of the gate trench above the isolation layer, and a gate material is filled in the gate trench within the second gate oxide layer, and etched back to form a gate. The top end of the gate protrudes from the front surface of the substrate and is located between the first sidewalls, while the bottom end of the gate is located in the substrate below the body layer. The gate oxide layer includes the first gate oxide layer and the second gate oxide layer.

3. The manufacturing method of the self-aligned dual-slot shielded IGBT structure according to claim 1, characterized in that, The process of removing the first hard mask layer pattern and the third hard mask layer pattern, then forming a self-aligned source trench between the gate trenches on the exposed front surface of the substrate, and forming a semiconductor layer of a second conductivity type in the source trenches, specifically includes: By etching back, the first hard mask layer pattern and the third hard mask layer pattern are removed. Then, using the first sidewall and the fourth hard mask layer pattern as a common mask, a source trench self-aligned between the gate trenches is formed downward on the front surface of the substrate exposed between the first sidewalls, and the bottom end of the source trench is either flush with or not flush with the bottom end of the gate trench. Subsequently, a semiconductor layer material is filled into the source trench, and an etch is performed to form a second type of conductive semiconductor layer in the source trench, with the top of the semiconductor layer flush with the front surface of the substrate.

4. The manufacturing method of the self-aligned dual-slot shielded IGBT structure according to claim 1, characterized in that, The process of removing the first hard mask layer pattern and the third hard mask layer pattern, then forming a self-aligned source trench between the gate trenches on the exposed front surface of the substrate, and forming a semiconductor layer of a second conductivity type in the source trenches, specifically includes: By etching back, the first hard mask layer pattern and the third hard mask layer pattern are removed, and a second sidewall structure is formed on the outside of the first sidewall located on both sides of the fourth hard mask layer pattern. Then, using the second sidewall, the first sidewall, and the fourth hard mask layer pattern as a common mask, a source trench self-aligned between the gate trenches is formed downward on the front surface of the substrate exposed between the second sidewalls, and the bottom end of the source trench is either flush with or not flush with the bottom end of the gate trench. Then, semiconductor layer material is filled into the source trench and etched back to form a second type of semiconductor layer in the source trench, and the top of the semiconductor layer is made flush with the front surface of the substrate. Specifically, when forming the second sidewall, the horizontal width of the source region layer located between the source trench and the gate trench is adjusted by adjusting the horizontal width of the second sidewall.

5. The manufacturing method of the self-aligned dual-slot shielded IGBT structure according to claim 1, characterized in that, Also includes: A current collector layer is formed on the upper surface of the current collector layer.

6. A self-aligned dual-slot shielded IGBT structure, characterized in that, The self-aligned dual-slot shielded IGBT structure, prepared using the method described in any one of claims 1-5, comprises: A source region layer of a first conductivity type is formed on the front surface of a substrate of a first conductivity type, and a body region layer of a second conductivity type is located below the source region layer; An array of multiple gate trenches and source trenches that enter the substrate side-by-side from the front surface of the substrate and are formed in an alternating manner, wherein a shielding gate, an isolation layer and a gate are formed from bottom to top in the gate trenches, a gate oxide layer is formed between the shielding gate and the inner wall of the gate trench and between the gate and the inner wall of the gate trench, and a semiconductor layer of a second conductivity type is formed in the source trenches. Multiple sidewall structures are formed on the front surface of the substrate and located between every two adjacent gate trenches and source trenches, and an adhesive layer is formed between the sidewalls; A collector region layer of a second conductivity type is formed on the back surface of the substrate, and a buffer layer of a first conductivity type is located below the collector region layer; The source trench is formed between each two adjacent grid trenches through an opening between each two adjacent sidewalls in a self-aligned manner.

7. The self-aligned dual-slot shielded IGBT structure according to claim 6, characterized in that, The bottom end of the gate trench is located in the substrate below the body region, and the bottom end of the source trench is either flush with or not flush with the bottom end of the gate trench.

8. The self-aligned dual-slot shielded IGBT structure according to claim 6, characterized in that, The top end of the gate protrudes from the front surface of the substrate and is located between the sidewalls, while the bottom end of the gate is located in the substrate below the body layer.

9. The self-aligned dual-slot shielded IGBT structure according to claim 6, characterized in that, The sidewall includes a first sidewall and a second sidewall connected together; wherein the first sidewall is disposed adjacent to both sides of the grid trench, the second sidewall is formed on the outside of the first sidewall and adjacent to both sides of the source trench, and the horizontal width of the source region layer located between the source trench and the grid trench is determined by the horizontal width of the second sidewall.

10. The self-aligned dual-slot shielded IGBT structure according to claim 6, characterized in that, Also includes: A collector layer formed on the upper surface of the collector region layer.

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