Image sensor readout load current source module, readout system and imaging equipment

Abstract

This invention discloses a load current source module, readout system, and imaging device for image sensor readout, relating to the field of image sensor technology. It includes: a current mirror circuit; a negative impedance transformation circuit, which generates negative resistance or capacitance to cancel out the parasitic resistance or capacitance of the VSL itself; and a charge / discharge acceleration circuit. This invention allows the load current source module to internally incorporate a negative impedance transformation circuit and a charge / discharge acceleration circuit. On one hand, the negative impedance transformation circuit generates negative impedance to cancel out the parasitic capacitance and resistance present in the VSL signal establishment, thereby accelerating the small signal establishment speed. On the other hand, the charge / discharge acceleration circuit provides a larger transient current to accelerate the large signal establishment speed. In other words, the load current source module in this application does not change the operating point design of the main current mirror circuit, effectively accelerating the VSL establishment time.

Description

Technical Field

[0001] This invention relates to the field of image sensor technology, and in particular to a load current source module, readout system and imaging device for image sensor readout. Background Technology

[0002] In existing CMOS image sensors, the ADC (A / D Converter) consists of a load current source array, a comparator array, and a counter array. The load current source array provides constant current to the source followers of the pixel array. During the signal readout process of the pixel array, the charge in the PD (PhotonDiode) needs to be transferred to the FD (FloatingDiffusion), causing the FD voltage to drop. This is further reduced by the pixel SF (SourceFollower), causing the pixel array output signal VSL (VerticalSignalLine) to decrease.

[0003] During the readout process described above, the VSL descent process is affected by the parasitic resistance and capacitance of the metal traces and the equivalent output impedance of SF, which slows down the VSL descent process. This means that the entire image sensor needs to wait for the VSL to completely drop to a stable level during the readout process. The time consumed in this process is called the VSL settling time.

[0004] Currently, in traditional image sensor configurations, to accelerate VSL establishment time, the bias current of the load current source is often increased: on the one hand, the transconductance of the SF of the pixel array is increased to reduce its equivalent output impedance; on the other hand, during the establishment of large signals, increasing the bias current of the load current source can accelerate the establishment speed of large signals.

[0005] However, the above methods have problems such as increasing the bias current of the load current source often leading to increased power consumption of the overall analog circuit and increased difficulty in designing the DC operating point of the load current source. Summary of the Invention

[0006] The purpose of this invention is to address the drawback of existing technologies where increasing the bias current of the load current source can easily lead to increased power consumption. This invention proposes a load current source module, readout system, and imaging device for image sensor readout.

[0007] To achieve the above objectives, the present invention adopts the following technical solution:

[0008] In a first aspect, the present invention provides a load current source module for image sensor readout, the load current source module being electrically connected to a pixel array in a pixel driving module, comprising:

[0009] A current mirror circuit, which is electrically connected to the pixel driving module, is used to provide bias current.

[0010] The current mirror circuit includes: a common-source cascode current mirror or two N-channel field-effect transistors;

[0011] A negative impedance transformation circuit is used to generate negative resistance or negative capacitance to cancel out the parasitic resistance or parasitic capacitance of the VSL itself.

[0012] The negative impedance transformation circuit includes an amplifier, which is in a negative feedback state.

[0013] A charge / discharge acceleration circuit is provided to provide charge / discharge current during VSL establishment.

[0014] In some feasible solutions, the current mirror circuit further includes:

[0015] Two N-channel field-effect transistors are connected via a common source and common gate. The gate of the N-channel field-effect transistor connected via the common source and common gate is connected to a bias voltage. The source of the N-channel field-effect transistor connected via the common source and common gate is electrically connected to the pixel driving module, the negative impedance conversion circuit, and the charge-discharge acceleration circuit, respectively.

[0016] In some feasible solutions, the charge / discharge acceleration circuit includes:

[0017] A voltage-to-current conversion circuit, one end of which is connected to a drain power supply voltage, is used to perform voltage-to-current conversion.

[0018] A current amplification circuit is electrically connected to the voltage-to-current conversion circuit, and the current amplification circuit is used to amplify the voltage-to-current conversion current.

[0019] In some feasible solutions, the voltage-to-current conversion circuit includes:

[0020] The first P-channel field-effect transistor has a drain power supply voltage connected to one end, and is used to provide a current source.

[0021] The second P-channel field-effect transistor is also connected to a drain power supply voltage at one end, and is used to provide bias current.

[0022] A capacitor is disposed on one side of the second P-channel field-effect transistor and is electrically connected to the second P-channel field-effect transistor. The capacitor is a bypass capacitor of the second P-channel field-effect transistor.

[0023] The third P-channel field-effect transistor has a gate connected to a vertical signal line signal output node, and its source is connected to the second P-channel field-effect transistor.

[0024] The first N-channel field-effect transistor is connected to the second P-channel field-effect transistor, and the drain of the first N-channel field-effect transistor is connected to the third P-channel field-effect transistor.

[0025] The second N-channel field-effect transistor and the first N-channel field-effect transistor form a current mirror.

[0026] In some feasible solutions, the amplifier is an operational amplifier, and the negative impedance transformation circuit further includes:

[0027] A first resistor is electrically connected to the non-inverting input terminal of the amplifier.

[0028] The second resistor is electrically connected to the inverting input terminal of the amplifier;

[0029] The third resistor is electrically connected to the inverting input terminal of the amplifier, and the third resistor is connected in parallel with the second resistor.

[0030] In some feasible solutions, the negative impedance transformation circuit further includes:

[0031] The first capacitor replaces the first resistor and is electrically connected to the non-inverting input of the amplifier.

[0032] In some feasible solutions, the amplifier is a common-gate amplifier, and the negative impedance transformation circuit further includes:

[0033] A first capacitor, one end of which is electrically connected to the pixel driving module;

[0034] The fourth P-channel field-effect transistor has its source electrically connected to the pixel driving module and to the first capacitor, and its gate is connected to a bias voltage.

[0035] The third N-channel field-effect transistor has a gate electrically connected to a bias voltage, and its source is electrically connected to the drain of the fourth P-channel field-effect transistor.

[0036] In some feasible solutions, the common-gate amplifier is replaced with a source follower, and the negative impedance transformation circuit further includes:

[0037] The fourth N-channel field-effect transistor replaces the fourth P-channel field-effect transistor. The gate of the fourth N-channel field-effect transistor is electrically connected to the pixel driving module. The drain of the fourth N-channel field-effect transistor is connected to a power supply. The source of the fourth N-channel field-effect transistor is electrically connected to the drain of the third N-channel field-effect transistor.

[0038] One end of the first capacitor is electrically connected to the source of the fourth N-channel field-effect transistor, and the other end of the first capacitor is electrically connected to the current mirror circuit.

[0039] In a second aspect, the present invention provides an image sensor readout system employing a load current source module for image sensor readout as described in any one of the first aspects, the readout system further comprising:

[0040] A pixel noise detection module is electrically connected to the pixel driving module, and the pixel noise detection module is used to detect the pixel array in the pixel driving module;

[0041] A reference ramp generation module, which is electrically connected to the pixel driving module;

[0042] The comparator is electrically connected to both the load current source module and the reference ramp generation module.

[0043] A counter, which is electrically connected to the comparator;

[0044] A data transmission module is electrically connected to the counter.

[0045] In a third aspect, the present invention also provides an imaging device that employs a load current source module for image sensor readout as described in any one of the first aspects or an image sensor readout system as described in the second aspect.

[0046] The beneficial effects of this invention are as follows:

[0047] This invention incorporates a negative impedance transformation circuit and a charge / discharge acceleration circuit within the load current source module. On one hand, the negative impedance transformation circuit generates negative impedance to cancel out the parasitic capacitance and resistance present during VSL signal establishment, thereby accelerating the small-signal establishment speed. On the other hand, the charge / discharge acceleration circuit provides a larger transient current to accelerate the large-signal establishment speed. In other words, the load current source module in this application does not alter the operating point design of the main current mirror circuit, effectively accelerating the VSL establishment time. Attached Figure Description

[0048] Figure 1 This is a schematic diagram of the working connection of a load current source module for image sensor readout provided in an embodiment of the present invention;

[0049] Figure 2 This is a schematic diagram of the pixel array portion structure in the pixel driving module provided in an embodiment of the present invention;

[0050] Figure 3 This is a schematic diagram of the VSL reduction process of the vertical signal line node provided in an embodiment of the present invention;

[0051] Figure 4 This is a schematic diagram showing the connection between the load current source module for image sensor readout and the pixel array in the pixel driving module provided in an embodiment of the present invention;

[0052] Figure 5 This is a schematic diagram of the current mirror circuit connection of a load current source module for image sensor readout provided in an embodiment of the present invention;

[0053] Figure 6 This is a schematic diagram of the negative impedance transformation circuit that generates negative resistance in the load current source module for image sensor readout provided in an embodiment of the present invention.

[0054] Figure 7 This is a schematic diagram of the negative impedance transformation circuit that generates negative capacitance in the load current source module for image sensor readout provided in an embodiment of the present invention;

[0055] Figure 8 This is a schematic diagram of the negative impedance transformation circuit containing a common-gate amplifier in an image sensor readout load current source module provided in an embodiment of the present invention;

[0056] Figure 9 This is a schematic diagram of the negative impedance transformation circuit containing a source follower in a load current source module for image sensor readout provided in an embodiment of the present invention. Detailed Implementation

[0057] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0058] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0059] In this invention, unless otherwise explicitly specified and limited, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "fixed" can mean a fixed connection, a detachable connection, or an integral part; it can mean a mechanical connection or an electrical connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0060] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the meaning of "and / or" throughout the text includes three parallel solutions; for example, "A and / or B" includes solution A, solution B, or a solution where both A and B are satisfied simultaneously. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0061] Reference Figures 1 to 9 The purpose of this invention is to address the drawback of existing technologies where increasing the bias current of the load current source easily leads to increased power consumption. This invention proposes a load current source module for image sensor readout. The load current source module internally incorporates a negative impedance transformation circuit 1062 and a charge / discharge acceleration circuit 1063. On one hand, the negative impedance transformation circuit 1062 generates negative impedance to cancel out parasitic capacitance and resistance that affect the VSL (Voltage-Side Array) setup speed, thereby accelerating the small-signal setup speed. On the other hand, the charge / discharge acceleration circuit 1063 provides a larger transient current to accelerate the large-signal setup speed. In other words, the load current source module in this application does not change the operating point design of the main current mirror circuit, effectively accelerating the VSL setup time.

[0062] Reference Figure 1 , Figure 2 , Figure 3 and Figure 4As shown, an image sensor readout load current source module 106 is electrically connected to the pixel array 100 in the pixel driving module 101. The load current source module 106 is used to cooperate with the pixel array 100 in the pixel driving module 101 to establish large signals and small signals. The pixel array 100 in the pixel driving module 101 can be composed of multiple pixel units, including: a photodiode 1001, an N-channel field-effect transistor 1002, an N-channel field-effect transistor 1003, an N-channel field-effect transistor 1004, and an N-channel field-effect transistor 1005. When exposed to light, the photodiode 1001 performs photoelectric conversion, generating photoelectrons. During reset, the gate connection signal RST of N-channel MOSFET 1003 is set high, turning on N-channel MOSFET 1003. The potential of floating diffusion point FD (Floating Diffusion) 1006 is reset to a level slightly lower than the power supply VDD. Subsequently, the RST signal is set low, ending the reset operation. During signal reading, the gate connection signal TX of N-channel MOSFET 1002 is set high, turning on N-channel MOSFET 1002. Since the potential of floating diffusion point FD 1006 is higher than that of the positive terminal of photodiode 1001, photoelectrons generated by photodiode 1001 move towards floating diffusion point FD 1006 through N-channel MOSFET 1002, causing its voltage to drop. At this time, if the pixel row containing the pixel unit is in the readout state, the gate connection signal SEL of the N-channel field-effect transistor 1005 is set high. The N-channel field-effect transistor 1004 operates as a source follower when the N-channel field-effect transistor 1005 is turned on. When the potential of the floating diffusion point FD1006 decreases, it causes the voltage at the vertical signal line node VSL1007 to decrease slightly less than the voltage change at the floating diffusion point FD1006. At this time, the voltage change at the vertical signal line node VSL1007 corresponds to the signal quantity generated by photogenerated electrons. Therefore, in Figure 2 The timing diagram of the operation of the gate connection signal TX of the N-channel field-effect transistor 1002 and the vertical signal line node VSL1007 during the pixel unit readout process is as follows: Figure 3As shown. When TX is high, the N-channel MOSFET 1002 turns on, and the vertical signal line node VSL1007 begins to decline. The establishment period of this decline can be divided into two parts: a large-signal establishment period and a small-signal establishment period. Here, to facilitate the circuit connection description of the load current source module and the pixel unit in the pixel driving module of this application, a set of pixel units is used as an example connection. Furthermore, the parasitic resistance 1101 of the metal trace of the vertical signal line node VSL1007 can be represented by resistor R0, its parasitic capacitance 1102 can be represented by capacitor C0, the load current source can be represented by ideal current source 1104, and the vertical signal line node connected to the load current source 1104 is VSL_OUT1103.

[0063] Reference Figures 5 to 6 As shown, specifically, the load current source module includes: a current mirror circuit 1061, a negative impedance transformation circuit 1062, and a charge / discharge acceleration circuit 1063. The current mirror circuit 1061 is electrically connected to the pixel driving module 101 and is used to provide bias current. The current mirror circuit 1061 includes: a common-source, common-gate current mirror or two N-channel field-effect transistors. Specifically, the current mirror circuit can be composed of two N-channel field-effect transistors (i.e., N-channel field-effect transistors 10611 and 10612) connected via a common-source, common-gate connection. The gate of the common-source, common-gate N-channel field-effect transistor is connected to a bias voltage, and the source of the common-source, common-gate N-channel field-effect transistor is electrically connected to the pixel driving module 101, the negative impedance transformation circuit 1062, and the charge / discharge acceleration circuit 1063, respectively. That is, the gates of the two common-source, common-gate N-channel field-effect transistors are respectively connected to VB2 and VB1, serving as the bias voltage for the common-source, common-gate current mirror. The vertical signal line output node VSL_OUT1103 is then connected to the negative impedance transformation circuit 1062 and the charge / discharge acceleration circuit 1063. It should be noted that the negative impedance transformation circuit 1062 and the charge / discharge acceleration circuit 1063 can be connected to the vertical signal line output node VSL_OUT1103 simultaneously, or only one of them can be connected to the vertical signal line output node VSL_OUT1103. Specifically, the negative impedance transformation circuit 1062 generates a negative resistance or negative capacitance to cancel out the parasitic resistance 1101 or parasitic capacitance 1102 of the VSL itself; the charge / discharge acceleration circuit 1063 provides charging / discharging current during VSL establishment. This allows the negative impedance generated by the negative impedance transformation circuit 1062 to cancel out the parasitic capacitance 1101 and parasitic resistance 1102 present during VSL signal establishment, thereby accelerating the establishment speed of small signals; and allows the charge / discharge acceleration circuit 1063 to provide a larger transient current, thereby accelerating the establishment speed of large signals.

[0064] Reference Figure 6 As shown, when the negative impedance transformation circuit 1062 generates a negative resistance to cancel out the parasitic resistance generated during VSL establishment, the negative impedance transformation circuit 1062 includes: a first resistor 10621, a second resistor 10623, a third resistor 10624, and an operational amplifier 10622. The first resistor 10621 is electrically connected to the non-inverting input terminal of the operational amplifier 10622; the second resistor 10623 is electrically connected to the inverting input terminal of the operational amplifier 10622; the third resistor 10624 is electrically connected to the inverting input terminal of the operational amplifier 10622, and the third resistor 10624 is connected in parallel with the second resistor 10623. In the negative impedance transformation circuit 1062 of this embodiment, the operational amplifier 10622, the second resistor 10623, and the third resistor 10624 form a negative feedback connection, with a closed-loop gain of (R1+R2) / R2, where R1 is the second resistor 10623 and R2 is the third resistor 10624. Therefore, when the voltage change at the positive input terminal of the operational amplifier 10622 is Vin=V1, the voltage change at its output terminal is: Vout=(R1+R2) / R2*V1; at this time, the input current flowing through the first resistor 10621 is:

[0065] Iin=(Vin-Vout) / R_NI=-R1 / R2*V1 / R_NI, where R_NI is the first resistor, 10621;

[0066] Therefore, in this embodiment, the negative impedance transformation circuit 1062 has an equivalent input resistance of -R2 / R1 times R_NI. When the value of R2 / R1*R_NI is equal to the parasitic resistance 1101 of the vertical signal line node VSL1007, the equivalent input impedance of the negative impedance transformation circuit 1062 cancels out the parasitic resistance 1101.

[0067] To facilitate understanding of the above, an example is provided: when the parasitic resistance R0 = 20KΩ, and we take R2 = 10KΩ, R1 = 500Ω, and R_NI = 1KΩ, the equivalent input impedance of the negative impedance transformation circuit 1062 is Zin = -20KΩ. This effectively reduces the load on the vertical signal line node VSL1007 and accelerates the small signal establishment speed. It should be noted that when R2 / R1 > 1, the equivalent input impedance of the negative impedance transformation circuit 1062 is a negative resistance; when R2 / R1 < 1, the equivalent input impedance of the negative impedance transformation circuit 1062 is a positive resistance.

[0068] Reference Figure 6In this embodiment of the charge / discharge acceleration circuit 1063, all field-effect transistors operate in saturation. Specifically, the charge / discharge acceleration circuit 1063 includes a voltage-to-current conversion circuit and a current amplification circuit. One end of the voltage-to-current conversion circuit is connected to a drain power supply voltage, and the voltage-to-current conversion circuit is used to perform voltage-to-current conversion. The current amplification circuit is electrically connected to the voltage-to-current conversion circuit, and the current amplification circuit is used to amplify the voltage-to-current conversion current. In this embodiment, the voltage-to-current conversion circuit includes a first P-channel field-effect transistor 10636, a second P-channel field-effect transistor 10631, a capacitor 10632, a third P-channel field-effect transistor 10633, a first N-channel field-effect transistor 10634, and a second N-channel field-effect transistor 10635. One end of the first P-channel field-effect transistor 10636 is connected to the drain power supply voltage, and the first P-channel field-effect transistor 10636 is used to provide a current source; one end of the second P-channel field-effect transistor 10631 is also connected to the drain power supply voltage, and the second P-channel field-effect transistor 10631 is used to provide bias current; the capacitor 10632 is disposed on one side of the second P-channel field-effect transistor 10631, and the capacitor 10632 is electrically connected to the second P-channel field-effect transistor 10631. The capacitor 10632 is a bypass capacitor of the second P-channel field-effect transistor 10631 (i.e., reducing the capacitance of the second P-channel field-effect transistor 10631). (Noise and voltage fluctuations generated by 31); the gate of the third P-channel field-effect transistor 10633 is connected to the vertical signal line signal output node VSL_OUT1103, and the source of the third P-channel field-effect transistor 10633 is connected to the second P-channel field-effect transistor 10631; the first N-channel field-effect transistor 10634 is connected to the second P-channel field-effect transistor 10631, and the drain of the first N-channel field-effect transistor 10634 is connected to the third P-channel field-effect transistor 10633; the second N-channel field-effect transistor 10635 and the first N-channel field-effect transistor 10634 form a current mirror. In this embodiment, the first P-channel field-effect transistor 10636 and the second P-channel field-effect transistor 10631 can act as current sources, and the capacitor 10632 can act as a bypass capacitor for the second P-channel field-effect transistor 10631. The second P-channel field-effect transistor 10631 provides bias current to the third P-channel field-effect transistor 10633 and the first N-channel field-effect transistor 10634.The gate of the third P-channel field-effect transistor 10633 is connected to the vertical signal line output node VSL_OUT1103. The drain of the third P-channel field-effect transistor 10633 and the first N-channel field-effect transistor 10634, together with the second N-channel field-effect transistor 10635, form a current mirror. The current mirror ratio is determined by the ratio of the width-to-length ratio of the second N-channel field-effect transistor 10635 to that of the first N-channel field-effect transistor 10634. The current of the first P-channel field-effect transistor 10636, acting as a current source, is set to be slightly equal to the saturation current of the second N-channel field-effect transistor 10635. During the fall-out setup of the vertical signal line output node VSL_OUT1103, the gate voltage of the third P-channel field-effect transistor 10633 drops by ΔV. At this time, the third P-channel field-effect transistor 10633 acts as a source follower, and its source voltage will drop. At this time, the capacitor 10632, which acts as a bypass capacitor, acts as a current source to provide a transient current ΔI=C1*dΔV / dt for the second P-channel field-effect transistor 10631. This transient current is amplified by the current mirror composed of the first N-channel field-effect transistor 10634 and the second N-channel field-effect transistor 10635. The amplification factor is as described above, which is the ratio of the width-to-length ratio of the second N-channel field-effect transistor 10635 to the first N-channel field-effect transistor 10634.

[0069] K = (W / L)_10635 / (W / L)_10634.

[0070] Therefore, it can be known that the transient output current generated by the drain of the second N-channel field-effect transistor 10635 is K*ΔI. Since the first P-channel field-effect transistor 10636 is set to a constant current operating state, this transient current K*ΔI will be provided by the load capacitor through the vertical signal line output node VSL_OUT1103. If the current source current is set to I, then in this embodiment, the current flowing out of the load capacitor during the large signal establishment period can be expressed as I+K*ΔI, and its magnitude can be adjusted by adjusting the capacitance value and the current mirror ratio K. Therefore, in this embodiment, the charge-discharge acceleration circuit 1063 accelerates the large signal establishment speed of the vertical signal line output node VSL_OUT1103 by increasing the transient current flowing out of the load capacitor during the large signal establishment period.

[0071] Reference Figure 7As shown, when the negative impedance transformation circuit 1062 generates a negative resistance to cancel the parasitic resistance during VSL establishment, the introduction of the first resistor 10621 may increase thermal noise on the vertical signal line input node VSL, and the negative resistance of the first resistor 10621 may cause circuit oscillation. Therefore, in some feasible solutions, the negative impedance transformation circuit further includes a first capacitor 10625, which replaces the first resistor 10621, and is electrically connected to the non-inverting input terminal of the operational amplifier 10622. That is, by setting the first capacitor 10625 in the negative impedance transformation circuit 1062, the first capacitor 10625 generates a negative capacitance to cancel the parasitic capacitance during VSL establishment, thereby accelerating VSL establishment. The remaining structures are similar to... Figure 6 As shown in the previous example, it will not be elaborated further here. In this embodiment, during the establishment of the descent of the vertical signal line node VSL1007, when the voltage change at the positive input terminal of the operational amplifier 10622 is Vin=V1, its output terminal Vout=(R1+R2) / R2*V1. As can be seen from the first embodiment, the equivalent input current flowing through the first capacitor 10625 at this time is:

[0072] Iin=(Vin-Vout)*s*C_NI=-R1 / R2*V1*s*C_NI;

[0073] Where s represents a complex variable, and its unit is rad / s, and C_NI is the first capacitor 10625.

[0074] Therefore, the equivalent input impedance of the negative impedance transformation circuit 1062 at this time can be calculated as follows:

[0075] Zin=Vin / Iin=-R2 / R1*(1 / (s*C_NI));

[0076] As can be seen from the above formula, in this embodiment, the negative impedance transformation circuit 1062 has an equivalent input capacitance of -R2 / R1 times the first capacitor 10625. When the value of R2 / R1*C_NI is equal to the parasitic capacitance 1102 of the vertical signal line node VSL1007, the equivalent input impedance of the negative impedance transformation circuit 1062 cancels out the parasitic capacitance 1102.

[0077] To facilitate understanding of the above, an example is provided: when the parasitic capacitance C0 = 2pF, and R2 = 10KΩ, R1 = 500Ω, and C_NI = 100fF, the equivalent input impedance of the negative impedance transformation circuit 1062 is Zin = -(1 / s*2p)Ω, and the impedance of the parasitic capacitance 1102 is Zc0 = (1 / s*2p)Ω. By canceling out Zin and Zc0, the load on the vertical signal line node VSL1007 is effectively reduced, accelerating the small signal establishment process. It should be noted that when R2 / R1 > 1, the equivalent input impedance of the negative impedance transformation circuit 1062 is a negative capacitor; when R2 / R1 < 1, the equivalent input impedance of the negative impedance transformation circuit 1062 is a positive capacitor. In this embodiment, by replacing the negative resistor in the negative impedance transformation circuit 1062 with a negative capacitor, the same acceleration of the small signal establishment process is achieved, but the risk of image quality degradation due to thermal noise from the resistor is avoided.

[0078] Reference Figure 8 ,exist Figure 6 and Figure 7 In the present invention, the operational amplifier 10622 using the negative feedback connection achieves the cancellation of the negative resistance or negative capacitance of the negative impedance transformation circuit 1062 with the parasitic resistance 1101 or parasitic capacitance 1102; however, in practical applications, the operational amplifier 10622 itself may introduce noise, and also increase the circuit area and power consumption. In some feasible solutions, the amplifier can be a common-gate amplifier. Specifically, in this embodiment, the negative impedance transformation circuit 1062 can consist of a first capacitor 10625, a fourth P-channel field-effect transistor 10626, and a third N-channel field-effect transistor 10627. One end of the first capacitor 10625 is electrically connected to the pixel driving module 101. The source of the fourth P-channel field-effect transistor 10626 is electrically connected to the pixel driving module 101 and to the first capacitor 10625. The gate of the fourth P-channel field-effect transistor 10626 is connected to a bias voltage. The gate of the third N-channel field-effect transistor 10627 is electrically connected to a bias voltage. The source of the third N-channel field-effect transistor 10627 is electrically connected to the drain of the fourth P-channel field-effect transistor 10626. In this embodiment, a negative impedance transformation circuit 1062 can be formed by a first capacitor 10625, a fourth P-channel field-effect transistor 10626, and a third N-channel field-effect transistor 10627. The charging and discharging acceleration circuit 1063 can be connected with... Figure 6 and Figure 7The details are not elaborated here as they are the same. Specifically, in the negative impedance transformation circuit 1062, the source of the fourth P-channel field effect transistor 10626 is connected to one end of the vertical signal line output node VSL_OUT1103 and the first capacitor 10625, the gate is connected to the bias voltage VB5, and the drain is connected to the third N-channel field effect transistor 10627 and the other end of the first capacitor 10625. The gate of the third N-channel field effect transistor 10627 is connected to the bias voltage VB6 and is used as a current source. The DC current of the fourth P-channel field effect transistor 10626 is set to be slightly equal to that of the third N-channel field effect transistor 10627. At this time, the fourth P-channel field effect transistor 10626 is used as a common-gate amplifier with a current source load. Then, when the vertical signal line output node VSL_OUT1103 drops by Vin = V1, the transconductance of the fourth P-channel field effect transistor 10626 is gm1. Ignoring its body effect, the small-signal resistance of the third N-channel field effect transistor 10627 is ro2. Then, due to the drop in the source voltage of the fourth P-channel field effect transistor 10626, its drain voltage will also drop: Vout = gm1 * ro2 * V1; and then the input current flowing through the first capacitor can be obtained as:

[0079] Iin=(Vin - Vout)*s*C_NI=(1 - gm1*ro2)*V1*s*C_NI;

[0080] At this time, the equivalent input impedance of the negative impedance transformation circuit 1062 is:

[0081] Zin = Vin / Iin = 1 / (1 - gm1*ro2)*(1 / (s*C_NI));

[0082] When designing 1 < gm1*ro2, it can be obtained that the negative impedance transformation circuit 1062 has an equivalent input capacitance that is (1 - gm1*ro2) times that of the first capacitor 10625, and the first capacitor 10625 exhibits a negative capacitance. By reasonably designing gm1 and ro2, the negative impedance transformation circuit 1062 can have a negative capacitance that can cancel the parasitic capacitance 1102, thereby achieving the acceleration of the small-signal establishment speed.

[0083] Refer to Figure 9 In Figure 8In this circuit, the negative impedance transformation circuit 1062 uses a common-gate amplifier with an active load to generate negative capacitance to offset the load parasitic capacitance 1102 of the vertical signal line node VSL1007, thereby accelerating the small signal setup speed. However, when using a common-gate amplifier, the drain swing of the fourth P-channel field-effect transistor 10626 limits the operating point of the negative impedance transformation circuit 1062. For example, when the voltage drop at the vertical signal line output node VSL_OUT1103 is large, it forces the fourth P-channel field-effect transistor 10626 to turn off, thus causing the negative impedance transformation circuit 1062 to fail. Therefore, in some feasible solutions, the common-gate amplifier can be replaced with a source follower, with other circuit structures remaining the same. Figure 8The same applies, so further details will not be elaborated here. In this embodiment, the negative impedance transformation circuit 1062 further includes: a fourth N-channel field-effect transistor 10628, which replaces the fourth P-channel field-effect transistor 10626. The gate of the fourth N-channel field-effect transistor 10628 is electrically connected to the pixel driving module 101, the drain of the fourth N-channel field-effect transistor 10628 is connected to a power supply, and the source of the fourth N-channel field-effect transistor 10628 is electrically connected to the drain of the third N-channel field-effect transistor 10627. One end of the first capacitor 10625 is electrically connected to the source of the fourth N-channel field-effect transistor 10628, and the other end of the first capacitor 10625 is electrically connected to the current mirror circuit 1061. In this embodiment, in the negative impedance transformation circuit 1062, the third N-channel field-effect transistor 10627 serves as the bias current source for the fourth N-channel field-effect transistor 10628; the fourth N-channel field-effect transistor 10628 is used as a source follower, with its gate connected to the vertical signal line output node VSL_OUT1103, its drain connected to the power supply, and its source connected to the drain of the third N-channel field-effect transistor 10627 and one end of the first capacitor 10625. The other end of the first capacitor 10625 is connected to the source of an N-channel field-effect transistor 10611 in the common-source common-gate current mirror circuit 1061. Therefore, in this embodiment, when the vertical signal line output node VSL_OUT1103 decreases to Vin=V1, assuming the input current is Iin and ignoring the body effect of the fourth N-channel field-effect transistor 10628 (e.g., connecting its substrate to the source), it can be considered that the transfer gain of the source follower is approximately 1. At this time, for the negative impedance transformation circuit 1062 in this embodiment, the transconductance of one N-channel field-effect transistor 10611 in the common-source cascode current mirror circuit 1061 is gm1, and its source voltage change is Vx. The source voltage change of the fourth N-channel field-effect transistor 10628 is Vy, the output impedance of the third N-channel field-effect transistor 10627 is Ro, and the transconductance of the fourth N-channel field-effect transistor 10628 is gm2. Then, according to Kirchhoff's current-voltage theorem, we can obtain:

[0084] gm2*(Vin-Vy)+(Vx-Vy) / (1 / (s*C_NI))=Vy / Ro;

[0085] Iin=-gm1*Vx=(Vx-Vy) / (1 / (s*C_NI));

[0086] After transforming and simplifying the above system of equations, we can approximate the following:

[0087] Zin=Vin / Iin=[gm1+gm1*gm2*Ro+s*C_NI*(gm2*Ro+gm1*Ro)] / gm1*gm2*Ro*s*C_NI;

[0088] As can be seen from the above formula, at this time, the equivalent input impedance of the negative impedance transformation circuit 1062 at low frequency is the sum of negative resistance and negative capacitance, and at high frequency, the equivalent input impedance is negative resistance, but the resistance value is small. Therefore, gm2 and Ro can be reasonably designed according to the actual situation, so that the negative impedance transformation circuit 1062 has a negative capacitance that can cancel the parasitic capacitance 1102, thereby accelerating the establishment speed of small signals.

[0089] Reference Figure 1 The present invention provides an image sensor readout system in a second aspect, employing a load current source module for image sensor readout as described in any one of the first aspects. The readout system further includes: a pixel noise detection module 102, a reference ramp generation module 103, a comparator 107, a counter 108, and a data transmission module 109. The pixel noise detection module 102 is electrically connected to the pixel driving module 101 and is used to detect the pixel array 100 in the pixel driving module 101. The reference ramp generation module 103 is electrically connected to the pixel driving module 101 via a signal input terminal 104. The comparator 107 is electrically connected to both the load current source module 106 and the reference ramp generation module via a signal output terminal 105. The counter 108 is electrically connected to the comparator 107. The data transmission module 109 is electrically connected to the counter 108. By employing the load current source module 106 described in the first aspect, the readout system can effectively accelerate the establishment of small and large signals in the image sensor sensor (VSL).

[0090] It should be noted that in this readout system, it is possible to use separate methods... Figure 6 , Figure 7 , Figure 8 , Figure 9 The negative impedance transformation circuit in the load current source module performs the readout operation. That is, in the readout system, Figure 6 , Figure 7 , Figure 8 , Figure 9 The negative impedance transformation circuits in the load current source module can be used in combination to generate negative impedance and cancel out the parasitic capacitance or resistance of the VSL itself.

[0091] In some implementations, the readout system can communicate using any currently known or future-developed network protocol such as HTTP (Hypertext Transfer Protocol) and can interconnect with digital data communication (e.g., communication networks) of any form or medium. Examples of communication networks include local area networks (“LANs”), wide area networks (“WANs”), the Internet (e.g., the Internet of Things), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks), as well as any currently known or future-developed networks. The functionality described above herein can be performed at least in part by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-chips (SOCs), complex programmable logic devices (CPLDs), etc.

[0092] In a third aspect, the present invention also provides an imaging device that employs an image sensor readout load current source module 106 as described in any one of the first aspects or an image sensor readout system as described in the second aspect. Specifically, in the imaging device, the VSL signal can be established by employing the current mirror circuit 1061, negative impedance transformation circuit 1062, and charge / discharge acceleration circuit 1063 of the aforementioned load current source module 106, thereby achieving the desired imaging performance.

[0093] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0094] The above description is merely a selection of preferred embodiments of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in the embodiments of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in the embodiments of this disclosure.

Claims

1. An image sensor readout load current source module electrically connected to a pixel array in a pixel drive module, the load current source module comprising: a load current source; a load current source control circuit; a load current source control circuit input; and a load current source control circuit output, wherein the load current source control circuit input is electrically connected to the load current source control circuit output. The application relates to a pixel driving circuit, which comprises the following parts: a current mirror circuit, which is electrically connected with a pixel driving module and is used for providing a bias current; wherein the current mirror circuit comprises a common-source common-gate current mirror or two N-channel field effect transistors; a negative impedance conversion circuit, which is used for generating a negative resistance or a negative capacitance to offset the parasitic resistance or the parasitic capacitance of the VSL itself; wherein the negative impedance conversion circuit comprises an amplifier in a negative feedback state; a charge and discharge acceleration circuit, which is used for providing a charge and discharge current during VSL establishment; Specifically, the amplifier is a common-gate amplifier, and the negative impedance conversion circuit further comprises: a first capacitor, one end of which is electrically connected with the pixel driving module; a fourth P-channel field effect transistor, the source electrode of which is electrically connected with the pixel driving module and the first capacitor, and the gate electrode of which is connected with a bias voltage; a third N-channel field effect transistor, the gate electrode of which is electrically connected with a bias voltage, and the source electrode of which is electrically connected with the drain electrode of the fourth P-channel field effect transistor; Specifically, the charge and discharge acceleration circuit comprises: a voltage-current conversion circuit, one end of which is connected with a drain electrode power voltage, and which is used for voltage-current conversion; a current amplification circuit, which is electrically connected with the voltage-current conversion circuit and is used for amplifying the voltage-current conversion current.

2. The load current source module for readout of an image sensor according to claim 1, wherein The current mirror circuit further comprises: two N-channel field effect transistors which are connected through a common-source common-gate connection, the gate electrodes of the N-channel field effect transistors connected through the common-source common-gate connection are connected with a bias voltage, and the source electrodes of the N-channel field effect transistors connected through the common-source common-gate connection are electrically connected with the pixel driving module, the negative impedance conversion circuit and the charge and discharge acceleration circuit respectively.

3. The load current source module for readout of an image sensor according to claim 2, wherein The voltage-current conversion circuit comprises: a first P-channel field effect transistor, one end of which is connected with a drain electrode power voltage, and which is used for providing a current source; a second P-channel field effect transistor, one end of which is also connected with a drain electrode power voltage, and which is used for providing a bias current; a capacitor, which is arranged on one side of the second P-channel field effect transistor, is electrically connected with the second P-channel field effect transistor, and is a bypass capacitor of the second P-channel field effect transistor; a third P-channel field effect transistor, the gate electrode of which is connected with a vertical signal line signal output node, and the source electrode of which is connected with the second P-channel field effect transistor; a first N-channel field effect transistor, which is connected with the second P-channel field effect transistor and is connected with the drain electrode of the third P-channel field effect transistor. A second N-channel field effect transistor, which, together with the first N-channel field effect transistor, forms a current mirror.

4. The load current source module for readout of an image sensor according to claim 3, wherein The common-gate amplifier is replaced by a source follower, and the negative impedance conversion circuit further comprises: A fourth N-channel field effect transistor, which replaces a fourth P-channel field effect transistor, has a gate electrically connected to a pixel driving module, a drain connected to a power supply, and a source electrically connected to a drain of the third N-channel field effect transistor. One end of the first capacitor is electrically connected to the source of the fourth N-channel field effect transistor, and the other end of the first capacitor is electrically connected to the current mirror circuit.

5. An image sensor readout system, characterized by, An image sensor readout system comprises the load current source module of any one of claims 1 to 4. A pixel noise detection module is electrically connected to the pixel driving module and is used to detect a pixel array in the pixel driving module. A reference ramp generation module is electrically connected to the pixel driving module. A comparator is electrically connected to the load current source module and the reference ramp generation module. A counter is electrically connected to the comparator. A data transmission module is electrically connected to the counter.

6. An image forming apparatus characterized by comprising: The image sensor readout system of claim 5 or the load current source module of any one of claims 1 to 4 is adopted.

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