Solar cells and photovoltaic modules

Abstract

The present application provides a solar cell and a photovoltaic module. The solar cell includes: a semiconductor substrate, wherein the rear surface of the semiconductor substrate has a first texture structure, and the first texture structure presents a non-pyramid-shaped microstructure morphology, including two or more first sub-structures that are at least partially stacked, and the top surface of the first sub-structure is a polygonal plane; among the two or more first sub-structures that are at least partially stacked, the one-dimensional dimension of the top surface of the outermost first sub-structure is less than or equal to 45 μm; a first passivation layer located on the front surface of the semiconductor substrate; a tunneling oxide layer located on the first texture structure; a doped conductive layer located on the surface of the tunneling oxide layer; and a second passivation layer located on the surface of the doped conductive layer. The solar cell and the photovoltaic module of the present application can improve the open-circuit voltage of the solar cell and reduce the contact resistance.

Description

[0001] This application is a divisional application of a Chinese patent application with the application number 202110895225.8 and the application title "Solar Cell and Its Preparation Method, Photovoltaic Module". Technical Field

[0002] This application relates to the technical field of photovoltaic cells, and specifically, to solar cells and photovoltaic modules. Background Art

[0003] The N-type TOPCon (Tunnel Oxide Passivated Contact) cell realizes the passivated contact of the rear surface by relying on the "tunneling effect". When preparing the TOPCon cell, boron-silicate glass will be formed after boron diffusion on the silicon wafer surface, and its cleaning and removal are more difficult than the phosphosilicate glass of the conventional PERC cell; generally, the boron-silicate glass on the rear surface of the N-type cell is removed by using an oxidizing mixed acid solution; after the surface is cleaned, dried, and then subjected to acidic additive-assisted rear surface polishing in a tank type or chain type. The rear surface of the silicon wafer after polishing has a flat structure, but the rear surface structure after polishing will directly affect the preparation of the tunneling oxide layer and the polysilicon layer, and further affect the passivation performance and conversion efficiency of the cell. Summary of the Invention

[0004] In view of this, this application proposes a solar cell and a photovoltaic module, which can improve the open-circuit voltage of the solar cell, reduce the metal electrode contact resistance, and enhance the cell conversion efficiency through the matching of the surface texture structure of the cell substrate.

[0005] In a first aspect, this application provides a solar cell, which includes:

[0006] A semiconductor substrate, wherein the rear surface of the semiconductor substrate has a first texture structure, the first texture structure presents a non-pyramid-shaped microstructural morphology, including two or more first sub-structures that are at least partially stacked, and the top surface of the first sub-structure is a polygonal plane; among the two or more first sub-structures that are at least partially stacked, the one-dimensional size of the top surface of the outermost first sub-structure is less than or equal to 45 μm; the front surface of the semiconductor substrate has a second texture structure, the second texture structure includes pyramid-shaped microstructures, the pyramid-shaped microstructures include a top away from the front surface of the semiconductor substrate and a bottom close to the front surface of the semiconductor substrate, and in a direction away from the front surface and perpendicular to the front surface, the distance between the top and the bottom of the pyramid-shaped microstructures is less than or equal to 5 μm;

[0007] A first passivation layer located on the second texture structure of the front surface of the semiconductor substrate;

[0008] A tunneling oxide layer on a first texture structure on the back surface of the semiconductor substrate;

[0009] A doped conductive layer on the surface of the tunneling oxide layer; and

[0010] A second passivation layer on the surface of the doped conductive layer.

[0011] Combined with the first aspect, in some feasible embodiments, for the two or more first substructures that are at least partially stacked, in a direction away from the back surface and perpendicular to the back surface, the distance between the top surface of the outermost first substructure and the top surface of the first substructure adjacent thereto is less than or equal to 2 μm.

[0012] Combined with the first aspect, in some feasible embodiments, the shape of the polygon plane includes at least one of a rhombus, a square, a trapezoid, an approximate rhombus, an approximate square, and an approximate trapezoid.

[0013] Combined with the first aspect, in some feasible embodiments, the thickness of the tunneling oxide layer on the top surface of the outermost first substructure is less than the thickness of the tunneling oxide layer on the side surface of the outermost first substructure.

[0014] Combined with the first aspect, in some feasible embodiments, the first texture structure further includes two or more second substructures arranged adjacently and non-stacked, and the one-dimensional dimension of the top surface of the second substructure away from the back surface is less than or equal to 45 μm.

[0015] Combined with the first aspect, in some feasible embodiments, the top surface of the second substructure is a polygon plane.

[0016] Combined with the first aspect, in some feasible embodiments, the tunneling oxide layer includes at least one of a silicon oxide layer, an aluminum oxide layer, a silicon oxynitride layer, a molybdenum oxide layer, and a hafnium oxide layer.

[0017] Combined with the first aspect, in some feasible embodiments, the thickness of the tunneling oxide layer is 0.8 nm to 2 nm.

[0018] Combined with the first aspect, in some feasible embodiments, the second passivation layer includes at least one of a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer.

[0019] Combined with the first aspect, in some feasible embodiments, the thickness of the second passivation layer is 70 nm - 120 nm.

[0020] Combined with the first aspect, in some feasible embodiments, the first passivation layer includes at least one of a silicon oxide layer, a silicon nitride layer, an aluminum oxide layer, and a silicon oxynitride layer.

[0021] In combination with the first aspect, in some feasible embodiments, the first passivation layer is a stacked passivation structure of an alumina layer and a silicon nitride layer.

[0022] In combination with the first aspect, in some feasible embodiments, the thickness of the silicon nitride layer is 50 nm - 110 nm.

[0023] In combination with the first aspect, in some feasible embodiments, the first passivation layer is a stacked passivation structure of an alumina layer, a silicon nitride layer, and a silicon oxynitride layer stacked in sequence.

[0024] In combination with the first aspect, in some feasible embodiments, the thickness range of the alumina layer is 2 nm to 10 nm.

[0025] In combination with the first aspect, in some feasible embodiments, the thickness of the silicon nitride layer is 40 nm - 80 nm.

[0026] In combination with the first aspect, in some feasible embodiments, the thickness of the silicon nitride layer is 10 nm - 60 nm.

[0027] In combination with the first aspect, in some feasible embodiments, the semiconductor substrate is an N-type single-crystalline silicon substrate, and the doped conductive layer is an N-type doped polysilicon layer, an N-type doped microcrystalline silicon layer, or an N-type doped amorphous silicon layer.

[0028] In combination with the first aspect, in some feasible embodiments, the thickness of the doped conductive layer is 60 nm - 200 nm.

[0029] In a second aspect, the present application provides a photovoltaic module, which includes a plurality of solar cell strings, and the solar cell strings include the solar cells described in the first aspect above.

[0030] In a third aspect, the present application provides a method for manufacturing a solar cell, including the following steps:

[0031] Texturing the semiconductor substrate, and a second texture structure is formed on the front surface of the semiconductor substrate, and the second texture structure includes pyramid-shaped microstructures;

[0032] Doping the front surface of the textured semiconductor substrate to form a doped layer;

[0033] The back surface of the semiconductor substrate is polished with an alkaline solution to form a first texture structure on the back surface of the semiconductor substrate. The first texture structure includes two or more first sub-structures that are at least partially stacked. For the two or more first sub-structures that are at least partially stacked, in a direction away from the back surface and perpendicular to the back surface, the distance between the top surface of the outermost first sub-structure and the top surface of the adjacent first sub-structure is less than or equal to 2 μm, and the one-dimensional size of the top surface of the outermost first sub-structure is less than or equal to 45 μm;

[0034] A tunneling oxide layer is formed on the first texture structure of the back surface of the semiconductor substrate;

[0035] A polysilicon layer is deposited on the surface of the tunneling oxide layer and doped to form a doped conductive layer. The doped conductive layer has a doping element of the same conductivity type as the semiconductor substrate;

[0036] A first passivation layer is formed on the front surface of the semiconductor substrate; and

[0037] A second passivation layer is formed on the surface of the doped conductive layer.

[0038] In a feasible implementation, the step of polishing the back surface of the semiconductor substrate with an alkaline solution includes:

[0039] The back surface of the semiconductor substrate is cleaned with an alkaline solution with a mass fraction of 5% - 15% to remove porous silicon;

[0040] The micro-droplets of the alkaline solution are dripped onto the back surface of the semiconductor substrate by a spraying method for roughening treatment, and then pre-cleaned with hydrofluoric acid with a mass fraction of 5% - 10%;

[0041] The back surface of the semiconductor substrate is polished with a polishing solution. The polishing temperature is 70°C - 80°C, and the polishing time < 260 s. The polishing solution includes NaOH with a mass fraction of 1% - 15%, KOH with a mass fraction of 1% - 15%, and an additive with a mass fraction of 0.5% - 2.5%;

[0042] The organic components in the polishing solution are removed with a mixed solution of potassium hydroxide with a mass fraction of 5% - 15% and hydrogen peroxide with a mass fraction of 15% - 40%;

[0043] The polished semiconductor substrate is washed and dried.

[0044] In a feasible implementation, the step of forming the tunneling oxide layer satisfies at least one of the following characteristics:

[0045] (1) A tunneling oxide layer is deposited and formed on the first texture structure on the back surface of the semiconductor substrate by using a variable temperature process and chemical vapor deposition method;

[0046] (2) During the deposition and formation of the tunneling oxide layer, the heating rate is controlled to be 0.5 °C / min to 3 °C / min, the deposition temperature is 560 °C to 620 °C, and the deposition time is 3 min to 10 min;

[0047] (3) The deposition temperature of the tunneling oxide layer is lower than the deposition temperature of the polysilicon layer;

[0048] (4) The tunneling oxide layer includes at least one of a silicon oxide layer, an aluminum oxide layer, a silicon oxynitride layer, a molybdenum oxide layer, and a hafnium oxide layer;

[0049] (5) The thickness of the tunneling oxide layer is 0.8 nm to 2 nm.

[0050] The technical solution of this application has at least the following beneficial effects:

[0051] By controlling the distance between sub-structures in the first texture structure on the back surface of the semiconductor substrate within an ideal range, the roughness of the back surface of the semiconductor substrate can be ensured within a suitable range, which is beneficial to improving the uniformity of the tunneling oxide layer formed on the first texture structure. The formed tunneling oxide layer has better performance, further inhibits the local doping concentration of the doped conductive layer from being too high, reduces the contact resistivity, increases the open-circuit voltage of the solar cell, and improves the fill factor and photoelectric conversion efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solutions of the embodiments of this application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0053] Figure 1 It is a schematic structural diagram of a solar cell preparation method provided by an embodiment of this application.

[0054] Figure 2 It is a scanning electron microscope schematic diagram of the second texture structure on the front surface of the semiconductor substrate of the solar cell provided by an embodiment of this application.

[0055] Figure 3 It is a scanning electron microscope schematic diagram of the first texture structure on the back surface of the semiconductor substrate of the solar cell provided by an embodiment of this application.

[0056] Figure 4aSchematic diagram of the first sub-structure in the first texture structure on the rear surface of the semiconductor substrate of the solar cell provided by the embodiment of the present application.

[0057] Figure 4b Schematic diagram of another first sub-structure in the first texture structure on the rear surface of the semiconductor substrate of the solar cell provided by the embodiment of the present application.

[0058] Figure 5 Schematic diagram of the sub-structure in the first texture structure on the rear surface of the semiconductor substrate of the solar cell provided by the embodiment of the present application.

[0059] Figure 6 Schematic diagram of the tunneling oxide layer on the first texture structure on the rear surface of the semiconductor substrate of the solar cell provided by the embodiment of the present application.

[0060] Figure 7a Schematic diagram of the photovoltaic module provided by the embodiment of the present application.

[0061] Figure 7b Top view of the photovoltaic module provided by the embodiment of the present application.

[0062] Figure 8 Flow chart of the method for manufacturing a solar cell provided by the embodiment of the present application. Detailed implementation manners

[0063] For a better understanding of the technical solutions of the present application, the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0064] It should be clear that the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the scope of protection of the present application.

[0065] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms of "a", "the" and "said" used in the embodiments of the present application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0066] It should be understood that the term " / and / " used herein is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " herein generally represents an "or" relationship between the associated objects before and after.

[0067] TOPCon cells rely on the "tunneling effect" to achieve back surface passivation. The existing back surface structure of TOPCon cells from the inside out is a semiconductor substrate, a tunneling oxide layer, a doped conductive layer, and a back surface passivation layer. In N-type TOPCon (contact passivation cells), BSG borosilicate glass is formed by boron diffusion, and the removal of borosilicate glass is more difficult than that of phosphosilicate glass; generally, an oxidizing mixed acid solution is used for removal; after the surface is cleaned, dried, and then back surface polishing is carried out. At present, the polished state of the back surface of the semiconductor substrate has a certain impact on the ultrathin tunneling oxide layer with a nanometer thickness, which is likely to cause an increase in the contact resistivity between the tunneling oxide layer and the semiconductor substrate, and is likely to lead to fluctuations in the fill factor of the solar cell, affecting the photoelectric conversion efficiency of the cell.

[0068] Based on this, in a first aspect, the present application provides a solar cell, as Figure 1 shown, the solar cell includes:

[0069] A semiconductor substrate 10, the back surface of the semiconductor substrate 10 has a first texture structure 12, the first texture structure 12 includes two or more first sub-structures that are at least partially stacked, wherein, for the two or more first sub-structures that are at least partially stacked, in a direction away from the back surface and perpendicular to the back surface, the distance between the top surface of the outermost first sub-structure and the top surface of the adjacent first sub-structure is less than or equal to 2 μm, and the one-dimensional size of the top surface of the outermost first sub-structure is less than or equal to 45 μm; the front surface of the semiconductor substrate 10 has a second texture structure 11, and the second texture structure 11 may include pyramid-shaped microstructures;

[0070] A first passivation layer 20 located on the front surface of the semiconductor substrate 10;

[0071] A tunneling oxide layer 30 located on the first texture structure on the back surface of the semiconductor substrate 10;

[0072] A doped conductive layer 40 located on the surface of the tunneling oxide layer 30, and the doped conductive layer has a doping element of the same conductive type as the semiconductor substrate;

[0073] And a second passivation layer 50 located on the surface of the doped conductive layer 40.

[0074] The front surface of the semiconductor substrate 10 may refer to the light-receiving surface, that is, the surface (light-receiving surface) that receives sunlight irradiation, and the back surface of the semiconductor substrate 10 refers to the surface opposite to the front surface. In some embodiments, the formed solar cell is a single-sided cell, the front surface may refer to the light-receiving surface, and the back surface may refer to the backlight surface. In some embodiments, the formed solar cell is a double-sided cell, and both the front surface and the back surface may be light-receiving surfaces.

[0075] As an optional technical solution of the present application, the semiconductor substrate 10 is an N-type crystalline silicon substrate (or silicon wafer), and any one or more of high-temperature diffusion, paste doping, or ion implantation processes can be used to form a P-type doping layer on the front surface of the semiconductor substrate, so as to form a PN junction in the semiconductor substrate 10. In some embodiments, the semiconductor substrate 10 may be one of a single-crystalline silicon substrate, a polycrystalline silicon substrate, a microcrystalline silicon substrate, or a silicon carbide substrate.

[0076] In some embodiments, the P-type doping layer is a boron-doped diffusion layer. The boron-doped diffusion layer is a P-type doping layer (i.e., P+ layer) formed by diffusing boron atoms to a certain depth on the front surface by using a boron source through a diffusion process. For example, the boron source may be liquid boron tribromide.

[0077] In some embodiments, as Figure 2 shown, the front surface of the semiconductor substrate 10 has a second texture structure 11, and the second texture structure 11 includes pyramidal microstructures 111. The pyramidal microstructures 111 may be tetrahedrons, approximate tetrahedrons, pentahedrons, approximate pentahedrons, etc. The pyramidal microstructures 111 can be formed by performing a texturing process on the semiconductor substrate. The ways of the texturing process may be chemical etching, laser etching, mechanical method, plasma etching, etc. The pyramidal microstructures enable better filling in the microstructures when screen-printing metal paste to form electrodes, obtaining better electrode contact, effectively reducing the series resistance of the battery, and improving the fill factor.

[0078] In some embodiments, the pyramidal microstructures 111 include a top away from the front surface of the semiconductor substrate and a bottom close to the front surface of the semiconductor substrate. In a direction away from the front surface and perpendicular to the front surface, the distance (or height) between the top and the bottom of the pyramidal microstructures is less than or equal to 5 μm. Preferably, the range of the distance is 2 μm - 5 μm. Specifically, it may be 2 μm, 2.5 μm, 2.8 μm, 3 μm, 3.5 μm, 3.8 μm, 4 μm, 4.2 μm, 4.5 μm, 4.8 μm, or 5 μm, etc. When the distance range of the pyramidal microstructures 111 is controlled within 5 μm, for example, 2 μm - 5 μm, the pyramidal microstructures 111 have the characteristics of low reflection, low recombination, and easy filling, so that the photoelectric conversion efficiency of the battery is improved.

[0079] It can be understood that due to the anisotropy of the crystal orientation of the front surface silicon crystal, the number of pyramid-shaped microstructures formed on the front surface cannot be exhausted. The distance of the pyramid-shaped microstructure 111 referred to here can be the distance between the highest protruding point and the lowest concave point of the randomly selected pyramid-shaped microstructure 111 within a specific area. For example, the distance of the pyramid-shaped microstructure 111 can be determined by measuring the surface shape of the semiconductor substrate using an atomic force microscope (AFM). For example, a scanning range of about 40μm×40μm is selected on the front surface, and the front surface of the semiconductor substrate is scanned within the selected range by the atomic force microscope to measure the morphological size of the pyramid microstructure on the front surface, and the height value h is calculated. Specifically, from the measured morphological size (AFM image), the highest protruding point h of the pyramid-shaped microstructure is selected a , and the lowest point of the bottom corresponding to the top is h b , and h = h a -h b is obtained. In other embodiments, the heights of multiple pyramid-shaped microstructures in the second texture structure are randomly collected, and the average value is calculated, and the average value is defined as the height of the pyramid-shaped microstructure. For example, 4 pyramid-shaped microstructures 111 are randomly selected, and their heights are h1, h2, h3, and h4 respectively. Then the height value of the pyramid-shaped microstructure 111 is (h1 + h2 + h3 + h4) / 4. That is to say, the average distance of multiple pyramid-shaped microstructures 111 can be regarded as the distance of the pyramid-shaped microstructure on the front surface, which is used to characterize the texture characteristics of the front surface.

[0080] As an optional technical solution of the present application, the first passivation layer 20 includes a stacked structure of at least one or more of a silicon oxide layer, a silicon nitride layer, an aluminum oxide layer, and a silicon oxynitride layer.

[0081] In some embodiments, the thickness range of the first passivation layer 20 is 10nm - 120nm, specifically it can be 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm or 120nm, etc. Of course, it can also be other values within the above range, which are not limited here.

[0082] Optionally, the first passivation layer 20 is a stacked passivation structure of an alumina layer and a silicon nitride layer. The alumina layer is disposed on the front surface of the semiconductor substrate 10, and the silicon nitride layer is disposed on the surface of the alumina layer. In some embodiments, the thickness of the alumina layer is 2 nm to 10 nm, and the refractive index of the alumina layer is 1.5 - 1.8; the thickness of the silicon nitride layer is 50 nm - 110 nm, and the refractive index of the silicon nitride layer is 1.65 - 2.25. The overall refractive index of the first passivation layer 20 is 1.9 - 2.0. In some embodiments, the alumina layer or the silicon nitride layer may include multiple sub-layers. For example, the silicon nitride layer is composed of 2 to 5 silicon nitride sub-layers.

[0083] Optionally, the first passivation layer is a stacked passivation structure of an alumina layer, a silicon nitride layer, and a silicon oxynitride layer stacked in sequence, wherein the thickness range of the alumina layer is 2 nm to 10 nm, the refractive index range of the alumina layer is 1.5 - 1.8, the thickness range of the silicon nitride layer is 40 nm - 80 nm, the refractive index range of the silicon nitride layer is 1.9 - 2.3, the thickness range of the silicon oxynitride layer is 10 nm - 60 nm, and the refractive index range of the silicon oxynitride layer is 1.5 - 1.75.

[0084] Furthermore, the back surface of the semiconductor substrate 10 has a first texture structure 12. Specifically, the first texture structure 12 can be formed by alkaline polishing treatment.

[0085] As an alternative technical solution of the present application, Figure 3 is a SEM schematic diagram of the first texture structure 12 on the back surface of the semiconductor substrate provided in the embodiment of the present application, as Figure 3 shown, the first texture structure 12 includes two or more first sub-structures 121 that are at least partially stacked. The first texture structure 12 presents a non-pyramid-shaped microstructure morphology. For example, the first texture structure can present a morphology similar to a "step" shape, and the first sub-structure 121 can be regarded as the steps of the "step".

[0086] Figure 4a is a schematic diagram of three partially stacked first sub-structures for example, Figure 4b is a schematic diagram of two partially stacked first sub-structures for example.

[0087] For two or more first sub-structures 121 that are at least partially stacked, in a direction away from the rear surface and perpendicular to the rear surface (which can also be understood as the stacking direction), the distance H between the top surface 121a of the outermost first sub-structure and the top surface 121b of the first sub-structure adjacent to it is less than or equal to 2 μm. Specifically, it can be 2 μm, 1.8 μm, 1.5 μm, 1.2 μm, 1.1 μm, 1.0 μm, 0.8 μm, 0.5 μm, 0.3 μm, 0.2 μm, 0.1 μm, etc. When the distance H exceeds 2 μm, the roughness of the first texture structure is too large, and the thickness of the tunneling oxide layer 30 formed on the first texture structure is greater, which is not conducive to forming a tunneling oxide layer with high density and high uniformity, and further affects the tunneling and passivation effects of the tunneling oxide layer 30; when the roughness of the first texture structure is too small, the thickness of the tunneling oxide layer formed on the first texture structure is smaller, which is not conducive to the contact with the electrode paste. Preferably, in a direction away from the rear surface and perpendicular to the rear surface, the distance H between the top surface 121a of the outermost first sub-structure and the top surface 121b of the first sub-structure adjacent to it is within 0.3 μm to 1.2 μm.

[0088] It should be noted that when three first sub-structures are stacked, the distance H between the top surface 121a of any one first sub-structure and the top surface 121b of the adjacent first sub-structure is less than or equal to 2 μm.

[0089] It can be understood that controlling the distance between the top surface 121a of the outermost first sub-structure and the top surface 121b of the first sub-structure adjacent to it to be less than or equal to 2 μm can control the roughness of the first texture structure within the required range, which is beneficial to improving the uniformity of the tunneling oxide layer formed on the first texture structure, resulting in better performance of the formed tunneling oxide layer, further suppressing the local high phosphorus concentration caused by phosphorus diffusion, reducing the contact resistivity, increasing the open-circuit voltage of the solar cell, and improving the fill factor and photoelectric conversion efficiency.

[0090] The one-dimensional dimension L of the top surface 121a of the outermost first sub-structure is less than or equal to 45 μm, that is, 0 < L ≤ 45 μm. Optionally, the one-dimensional dimension L is within the range of 2 μm to 45 μm. Here, the one-dimensional dimension L of the top surface may specifically be the length, width, diagonal length of the surface, the diameter of a circle, etc., which is not limited herein. In some embodiments, the one-dimensional dimension may refer to the average value of the one-dimensional dimensions of the top surfaces of multiple outermost first sub-structures within a preset range area on the back surface of the substrate. The average one-dimensional dimension of the top surface of the outermost first sub-structure may specifically be 2 μm, 5 μm, 8 μm, 12 μm, 15 μm, 18 μm, 20 μm, 25 μm, 28 μm, 30 μm, 35 μm, 40 μm, 42 μm, 40 μm or 45 μm, etc. Preferably, the average one-dimensional dimension of the top surface of the outermost first sub-structure is within the range of 10 μm to 15 μm.

[0091] In a specific embodiment, as Figure 3 shown, the first texture structure further includes two or more second sub-structures 122 arranged adjacently and non-stacked. The one-dimensional dimension L of the top surface of the second sub-structure 122 away from the back surface is less than or equal to 45 μm, that is, 0 < L ≤ 45 μm. Optionally, the one-dimensional dimension L of the second sub-structure 122 is within the range of 2 μm to 45 μm, and may specifically be 2 μm, 5 μm, 8 μm, 12 μm, 15 μm, 18 μm, 20 μm, 25 μm, 28 μm, 30 μm, 32 μm, 35 μm or 45 μm, etc.

[0092] Different from the pyramid-shaped microstructures on the front surface, the top surfaces of the first sub-structure and / or the second sub-structure on the back surface are polygonal planes, and the shapes of the polygonal planes include at least one of a rhombus, a square, a trapezoid, an approximate rhombus, an approximate square, and an approximate trapezoid. It can be understood that during the actual manufacturing process, the top surface morphology of the first sub-structure or the second sub-structure presents an irregular polygonal plane, but generally presents morphological characteristics similar to a rhombus, a square, or a trapezoid.

[0093] In some instances, due to the preparation of subsequent passivation film layers, such as the first passivation layer 20, the tunneling oxide layer 30, the doped conductive layer 40, etc., it may cause certain damage to the initial structures of the second texture structure and the first texture structure. For example, in mass-produced solar cells, the second texture structure may also include a small number of non-pyramid-shaped microstructures, and the non-pyramid-shaped microstructures are formed due to the damage of the tips of the pyramid-shaped microstructures.

[0094] In some examples, when measuring the texture size features characterizing the second texture structure or the first texture structure of the solar cell, such as the one-dimensional size of the top surface of the first sub-structure and the distance between the surfaces of adjacent first sub-structures, the calibration of the film layer surface can be directly measured by a testing instrument (optical microscope, atomic force microscope, scanning electron microscope, transmission electron microscope, etc.). In one case, since the film layer thickness is at the nanometer level, it can be directly obtained using the film layer measurement data corresponding to the second texture structure or the first texture structure, and the film layer measurement data is the sum of the film layer thickness and the texture size. In another case, it can also be obtained by subtracting the film layer thickness data from the aforementioned film layer measurement data. The above measurement means are only examples, and the present application does not limit this.

[0095] As Figure 1 and Figure 6 shown, the tunneling oxide layer 30 on the first texture structure 12 on the back surface of the semiconductor substrate 10. The tunneling oxide layer 30 can be a stacked structure of one or more of a silicon oxide layer, an aluminum oxide layer, a silicon oxynitride layer, a molybdenum oxide layer, and a hafnium oxide layer. In other embodiments, the tunneling oxide layer 30 can also be an oxygen-containing silicon nitride layer, an oxygen-containing silicon carbide layer, etc. The thickness of the tunneling oxide layer 30 is 0.8 nm to 2 nm. Specifically, the thickness of the tunneling oxide layer 30 is 0.8 nm, 0.9 nm, 1.0 nm, 1.2 nm, 1.4 nm, 1.6 nm, 1.8 nm, or 2 nm, etc. The thickness of the tunneling oxide layer 30 refers to the thickness of the tunneling oxide layer relative to the formation surface. The thickness of the tunneling oxide layer 30 formed on the first texture structure can be obtained by performing cross-sectional observation and calculation with the normal direction of the inclined surface of the sub-structure as the thickness direction. If the thickness of the tunneling oxide layer 30 is too large, it is not conducive to reducing the contact resistance of the tunneling oxide layer. By controlling the thickness of the tunneling oxide layer, the reduction of the fill factor caused by the contact resistance can be suppressed.

[0096] Specifically, the bandgap width of the tunneling oxide layer 30 > 3.0 eV. It is generally difficult for carriers to be transmitted through the tunneling oxide layer 30 by thermal emission. However, since the tunneling oxide layer 30 is very thin, carriers can pass through the tunneling oxide layer 30 by tunneling effect. Therefore, the tunneling oxide layer with a thickness of 0.8 nm to 2 nm has no hindrance to the transmission of majority carriers. As the thickness of the tunneling oxide layer gradually increases, the tunneling effect of majority carriers is affected, and it is difficult for carriers to be transmitted through the tunneling oxide layer 30, and the photoelectric conversion efficiency of the battery will gradually decrease. When the thickness of the tunneling oxide layer is too small, it cannot play a passivation role. Preferably, the tunneling oxide layer 30 is a silicon oxide layer, and the thickness of the tunneling oxide layer 30 is 0.8 nm to 1.5 nm.

[0097] As an alternative technical solution of the present application, as Figure 6As shown, the thickness D1 of the tunneling oxide layer on the top surface of the outermost first sub-structure is less than the thickness D2 of the tunneling oxide layer formed on the side surface of the outermost first sub-structure. Specifically, the thickness difference (D2 - D1) between the tunneling oxide layer on the top surface of the outermost first sub-structure and the tunneling oxide layer formed on the side surface of the outermost sub-structure is less than or equal to 0.15 nm. The thickness difference can specifically be 0.14 nm, 0.13 nm, 0.12 nm, 0.11 nm, 0.10 nm, 0.09 nm, 0.08 nm, 0.07 nm, 0.06 nm, 0.05 nm, 0.04 nm, etc. When the thickness difference between the tunneling oxide layer on the top surface of the outermost first sub-structure and the tunneling oxide layer formed on the side surface of the outermost sub-structure is too large, the thickness uniformity of the tunneling oxide layer is poor, the current density of the solar cell is easily affected, and the open-circuit voltage of the solar cell circuit decreases.

[0098] In some embodiments, by setting texture structures with different morphologies on the front and back surfaces of the semiconductor substrate, forming a pyramid-shaped texture structure on the front surface and a non-pyramid texture structure on the back surface, the formed battery can have trapping light structures at different levels, increasing the effective contact area of light. Moreover, for the first texture structure formed on the back surface, the distance between the top surface of the outermost first sub-structure and the top surface of the first sub-structure adjacent to it is controlled within 2 μm, which is beneficial to reducing the hole density (pinhole) in the tunneling oxide layer, thereby improving the density and uniformity of the tunneling oxide layer, further suppressing the local doping concentration of the doped conductive layer on the surface of the tunneling oxide layer from being too high, reducing the contact resistivity, increasing the open-circuit voltage of the solar cell, and improving the fill factor and photoelectric conversion efficiency.

[0099] In some embodiments, the doped conductive layer 40 can be a doped polysilicon layer, a doped microcrystalline silicon layer, or a doped amorphous silicon layer, and the doped conductive layer 40 has a doping element of the same conductive type as the semiconductor substrate.

[0100] When the semiconductor substrate 10 is an N-type single-crystalline silicon substrate and the doped conductive layer 40 is an N-type doped polysilicon layer, an N-type doped microcrystalline silicon layer, or an N-type doped amorphous silicon layer, the doping element can be an N-type doping element such as phosphorus.

[0101] In some embodiments, the thickness range of the doped conductive layer 40 is 60 nm - 200 nm. For example, for an N-type doped polysilicon layer, the refractive index range of the doped conductive layer 40 is 3.5 - 4.5.

[0102] As an alternative technical solution of the present application, the second passivation layer 50 includes at least one of a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer. The thickness of the second passivation layer 50 is 70 nm - 120 nm. For example, the second passivation layer 50 is a silicon nitride layer, the silicon nitride layer has a low silicon-nitrogen ratio, the refractive index range of the silicon nitride layer is 1.7 - 2.1, the refractive index of the silicon nitride layer can be 1.7, 1.8, 1.9, 2.0, 2.1, etc., and of course it can also be other values within the above range, which is not limited herein. By controlling the refractive index of the silicon nitride layer to have a low silicon-nitrogen ratio, the formed second passivation layer 50 can reduce the contact resistivity during metallization treatment, thereby further reducing the contact resistivity of the solar cell.

[0103] In some embodiments, when the second passivation layer 50 is a stacked silicon nitride layer and silicon oxide layer or a stacked silicon nitride layer and silicon oxynitride layer, the silicon nitride layer is located on the surface of the doped conductive layer, and the silicon oxide layer or the silicon oxynitride layer is located on the surface of the silicon nitride layer.

[0104] Furthermore, the solar cell further includes a first electrode 60 and a second electrode 70. The first electrode 60 forms an ohmic contact with the P-type doped layer (e.g., boron-doped diffusion layer) on the front surface of the semiconductor substrate 10 through the first passivation layer 20, and the second electrode 70 forms an ohmic contact with the doped conductive layer 40 through the second passivation layer 50. The doped conductive layer 40 and the tunneling oxide layer 30 form a passivated contact structure. The first electrode 60 and the second electrode 70 can be formed by sintering a metal conductive paste coated on the surfaces of the first passivation layer and the second passivation layer. In some embodiments, the materials of the first electrode 60 or the second electrode 70 include metal materials such as silver, aluminum, copper, and nickel.

[0105] For the solar cell formed as Figure 1 shown, that is, a second texture structure with pyramid-shaped microstructures is formed on the front surface of the semiconductor substrate 10, a first texture structure with non-pyramid-shaped microstructures is formed on the back surface of the semiconductor substrate, a matching first passivation layer 20 (e.g., a stacked passivation structure of an alumina layer and a silicon nitride layer) is formed on the second texture structure, and a matching tunneling oxide layer 30, doped conductive layer 40, and second passivation layer 50 (e.g., a silicon nitride layer) are formed on the first texture structure. The solar cell structure has a high photoelectric conversion efficiency.

[0106] In a second aspect, an embodiment of the present application provides a photovoltaic module, and the photovoltaic module includes a plurality of solar cell strings.

[0107] As Figure 7a and Figure 7b shown, the photovoltaic module includes a first cover plate 1, a first encapsulation adhesive layer 2, a solar cell string 3, a second encapsulation adhesive layer 4, and a second cover plate 5.

[0108] Among them, the solar cell string 3 includes a plurality of solar cells (such as Figure 1 the described solar cells), and the solar cells are connected by conductive bands (not shown in the figure). The connection method between the solar cells can be partial lamination or splicing.

[0109] The first cover plate 1 and the second cover plate 5 can be transparent or opaque cover plates, such as glass cover plates and plastic cover plates.

[0110] Both sides of the first encapsulation adhesive layer 2 are respectively in contact and fit with the first cover plate 1 and the cell 3, and both sides of the second encapsulation adhesive layer 4 are respectively in contact and fit with the second cover plate 1 and the cell 3. Among them, the first encapsulation adhesive layer 2 and the second encapsulation adhesive layer 4 can be ethylene-vinyl acetate copolymer (EVA) film, polyethylene octene co-elastic body (POE) film or polyethylene terephthalate (PET) film respectively.

[0111] The photovoltaic module can also adopt side full-enclosure encapsulation, that is, use encapsulation tape to completely cover and encapsulate the sides of the photovoltaic module to prevent the phenomenon of lamination deviation during the lamination process of the photovoltaic module.

[0112] Furthermore, the photovoltaic module ( Figure 7b the shown photovoltaic module 100) also includes an edge-sealing component 6, and this edge-sealing component 6 is fixedly encapsulated on part of the edge of the photovoltaic module. As Figure 7b shown, this edge-sealing component 6 is fixedly encapsulated on the edge near the corner of the photovoltaic module. This edge-sealing component 6 can be a high-temperature resistant tape. This high-temperature resistant tape has relatively excellent high-temperature resistance characteristics, will not decompose or fall off during the lamination process, and can ensure the reliable encapsulation of the photovoltaic module. Among them, both ends of the high-temperature resistant tape are respectively fixed to the second cover plate 5 and the first cover plate 1. Both ends of this high-temperature resistant tape can be respectively adhered to the second cover plate 5 and the first cover plate 1, and the middle part thereof can realize the limit of the side of the photovoltaic module to prevent the photovoltaic module from having lamination deviation during the lamination process.

[0113] Thirdly, the present application also provides a preparation method for a solar cell, which is used to prepare the above-mentioned solar cell. As Figure 8 shown, the preparation method includes the following steps:

[0114] Step S10, perform texturing treatment on the semiconductor substrate, and a second texture structure is formed on the front surface of the semiconductor substrate. The second texture structure can include pyramid-shaped microstructures;

[0115] Step S20, perform doping treatment on the front surface of the texturing-treated semiconductor substrate to form a doped layer;

[0116] Step S30, polish the back surface of the semiconductor substrate with an alkaline solution to form a first texture structure on the back surface of the semiconductor substrate. The first texture structure includes two or more first sub-structures that are at least partially stacked. For the two or more first sub-structures that are at least partially stacked, in a direction away from the back surface and perpendicular to the back surface, the distance between the top surface of the outermost first sub-structure and the top surface of the adjacent first sub-structure is less than or equal to 2 μm, and the one-dimensional size of the top surface of the outermost first sub-structure is less than or equal to 45 μm;

[0117] Step S40, form a tunneling oxide layer on the first texture structure on the back surface of the semiconductor substrate;

[0118] Step S50, deposit a polysilicon layer on the surface of the tunneling oxide layer and perform doping treatment on the polysilicon layer to form a doped conductive layer. The doped conductive layer has a doping element of the same conductivity type as the semiconductor substrate;

[0119] Step S60, form a first passivation layer on the front surface of the semiconductor substrate; and

[0120] Step S70, form a second passivation layer on the surface of the doped conductive layer.

[0121] In the above solution, the back surface of the semiconductor substrate is polished with an alkaline solution to form texture structures with different morphologies on the front and back surfaces of the semiconductor substrate. A pyramidal texture structure is formed on the front surface and a non-pyramidal texture structure is formed on the back surface, which can make the formed battery have trapping light structures at different levels and increase the effective contact area of light. Moreover, for the first texture structure formed on the back surface, the distance between the top surface of the outermost first sub-structure and the top surface of the adjacent first sub-structure is controlled within 2 μm, which is beneficial to reducing the hole density (pinhole) in the tunneling oxide layer, thereby improving the density and uniformity of the tunneling oxide layer, further suppressing the local doping concentration of the doped conductive layer on the surface of the tunneling oxide layer from being too high, reducing the contact resistivity, increasing the open circuit voltage of the solar cell, and improving the fill factor and photoelectric conversion efficiency.

[0122] The following specifically introduces this solution:

[0123] Step S10, perform texturing treatment on the semiconductor substrate to form a second texture structure on the front surface of the semiconductor substrate. The second texture structure includes pyramidal microstructures.

[0124] The semiconductor substrate can be a crystalline silicon substrate (silicon substrate), such as a polysilicon substrate, a monocrystalline silicon substrate, a microcrystalline silicon substrate, or a silicon carbide substrate. The specific type of the semiconductor substrate is not limited in the embodiments of the present application. In some embodiments, the semiconductor substrate is an N-type crystalline silicon substrate (or silicon wafer), and the thickness of the semiconductor substrate is 60 um to 240 um, specifically, it can be 60 um, 80 um, 90 um, 100 um, 120 um, 150 um, 200 um, or 240 um, etc., which is not limited herein. The doping elements of the semiconductor substrate can be phosphorus, nitrogen, etc.

[0125] It should be noted that the specific operation method of texturing in the present application is not limited. For example, a wet texturing process can be selected, but not limited to, to texture the N-type substrate. When the N-type semiconductor substrate is an N-type monocrystalline silicon substrate, an alkaline solution such as potassium hydroxide solution can be used for texturing. Since the corrosion of the NaOH solution is anisotropic, pyramid-shaped microstructures can be prepared.

[0126] As Figure 2 shown, the front surface of the semiconductor substrate 10 has a second texture structure 11, and the second texture structure 11 includes pyramid-shaped microstructures 111. The pyramid-shaped microstructures 111 can be tetrahedrons, approximate tetrahedrons, pentahedrons, approximate pentahedrons, etc. The pyramid-shaped microstructures 111 can be formed by performing a texturing process on the semiconductor substrate. The method of the texturing process can be chemical etching, laser etching, mechanical method, plasma etching, etc. The pyramid-shaped microstructures enable the metal paste to be better filled in the microstructures when screen-printing the electrodes, obtaining better electrode contact, effectively reducing the series resistance of the battery, and improving the fill factor.

[0127] Step S20: Perform doping treatment on the front surface of the textured semiconductor substrate to form a doping layer.

[0128] In the specific implementation manner, when the semiconductor substrate 10 is an N-type substrate, any one or more of high-temperature diffusion, paste doping, or ion implantation can be used to form a P-type doping layer on the front surface of the semiconductor substrate, so as to form a PN junction in the semiconductor substrate 10.

[0129] In some embodiments, the P-type doping layer is a boron-doped diffusion layer. The boron-doped diffusion layer is a P-type doping layer (i.e., P+ layer) formed by diffusing boron atoms to a certain depth on the front surface by using a boron source through a diffusion process. For example, the boron source can be liquid boron tribromide. The microcrystalline silicon phase of the boron-diffused treated substrate is transformed into a polysilicon phase. Due to the high concentration of boron on the surface of the semiconductor substrate, a boron-silicate glass layer (BSG) is usually formed.

[0130] Further, before the back surface of the semiconductor substrate is polished with an alkaline solution in step S30, the method further includes:

[0131] Removing the borosilicate glass layer on the back surface of the semiconductor substrate with the prepared mixed acid, where the mixed acid includes a hydrofluoric acid solution with a mass fraction of 0.1% - 10%, a sulfuric acid solution with a mass fraction of 10% - 20%, and a nitric acid solution with a mass fraction of 25% - 50%;

[0132] Washing and drying the back surface of the pickled semiconductor substrate.

[0133] It can be understood that during the boron diffusion process, partial borosilicate glass will be formed by overplating on the back surface of the semiconductor substrate, and this part of the borosilicate glass needs to be removed. It should be noted that a porous structure will appear on the back surface of the semiconductor substrate after pickling.

[0134] Specifically, the pickling time is 10s - 180s, and the pickling temperature is 7°C - 20°C, that is, the borosilicate glass on the back surface of the semiconductor substrate is pickled and removed at room temperature to expose the semiconductor substrate body.

[0135] In step S30, the back surface of the semiconductor substrate is polished with an alkaline solution, and the back surface of the semiconductor substrate is polished with an alkaline solution to form a first texture structure on the back surface of the semiconductor substrate.

[0136] Specifically, the back surface of the semiconductor substrate is cleaned with an alkaline solution with a mass fraction of 5% - 15% to remove the porous silicon;

[0137] Then, the micro-droplets of the alkaline solution are dripped onto the back surface of the semiconductor substrate by spraying for roughening treatment, and then pre-cleaned with a hydrofluoric acid with a mass fraction of 5% - 10%;

[0138] The back surface of the semiconductor substrate is polished with a polishing solution, the polishing temperature is 70°C - 80°C, and the polishing time < 260s. Among them, the polishing solution includes NaOH with a mass fraction of 1% - 15%, KOH with a mass fraction of 1% - 15%, and an additive with a mass fraction of 0.5% - 2.5%;

[0139] Removing the organic components in the etching solution with a mixed solution of potassium hydroxide with a mass fraction of 5% - 15% and hydrogen peroxide with a mass fraction of 15% - 40%;

[0140] Washing and drying the polished semiconductor substrate.

[0141] In some embodiments, when performing the back surface polishing treatment, it is necessary to protect the borosilicate glass layer on the front surface of the semiconductor substrate, such as protecting the borosilicate glass layer through a mask.

[0142] In a specific embodiment, since the boron concentration on the back surface of the semiconductor substrate is relatively low, etching with an alkali solution can effectively improve the etching efficiency. The alkali solution contains an organic base and / or an inorganic base. The inorganic base can be NaOH, KOH, Ga(OH) 2 , NH 3 .H 2 O, and the organic base can be triethylamine, nitrophenol, pyridine, quinine, colchicine, etc. The additive in the polishing solution can be a buffer solution composed of sodium sulfonate, maleic anhydride, alkyl glycoside, etc.

[0143] The polishing temperature can specifically be 70°C, 72°C, 74°C, 75°C, 78°C, 79°C, 80°C, etc., and the polishing time can be 250 s, 240 s, 230 s, 220 s, 200 s, 180 s, 160 s, 140 s, 120 s, 100 s, 80 s, etc. Of course, it can also be other values within the above ranges.

[0144] In some embodiments, the weight loss of the semiconductor substrate during polishing is less than 0.3 g.

[0145] By controlling the polishing time and the polishing temperature, the shape of the sub-structures in the first texture structure after polishing can be adjusted, such that in at least two or more stacked first sub-structures, in a direction away from the back surface and perpendicular to the back surface, the distance between the top surface of the outermost first sub-structure and the top surface of the adjacent first sub-structure is less than or equal to 2 μm, thereby increasing the roughness of the back surface of the semiconductor substrate.

[0146] In some embodiments, the surface of the semiconductor substrate can be dried with hot air to form a first texture structure including non-pyramid-shaped microstructures.

[0147] As an alternative technical solution of the present application, Figure 3 is a scanning electron microscope schematic diagram of the first texture structure 12 on the back surface of the semiconductor substrate provided by the embodiment of the present application. As Figure 3 shown, the first texture structure 12 includes at least two or more stacked first sub-structures 121.

[0148] Figure 4a is a schematic diagram of three partially stacked first sub-structures as an example, Figure 4b is a schematic diagram of two partially stacked first sub-structures as an example.

[0149] For two or more first sub-structures 121 that are at least partially stacked, in a direction away from and perpendicular to the rear surface, the distance H between the top surface 121a of the outermost first sub-structure and the top surface 121b of the adjacent first sub-structure is less than or equal to 2 μm. Specifically, it can be 2 μm, 1.8 μm, 1.5 μm, 1.2 μm, 1.1 μm, 1.0 μm, 0.8 μm, 0.5 μm, 0.3 μm, 0.2 μm, 0.1 μm, etc. When the distance H exceeds 2 μm, the roughness of the first texture structure is too large, and the thickness of the tunneling oxide layer 30 formed on the first texture structure is greater, which is not conducive to forming a tunneling oxide layer with high density and high uniformity, and further affects the tunneling and passivation effects of the tunneling oxide layer 30; when the roughness of the first texture structure is too small, the thickness of the tunneling oxide layer formed on the first texture structure is smaller, which is not conducive to the contact with the electrode paste. Preferably, in a direction away from and perpendicular to the rear surface, the distance H between the top surface 121a of the outermost first sub-structure and the top surface 121b of the adjacent first sub-structure is within 0.3 μm to 1.2 μm.

[0150] It should be noted that when three first sub-structures are stacked, the distance H between the top surface 121a of any one first sub-structure and the top surface 121b of the adjacent first sub-structure is less than or equal to 2 μm.

[0151] It can be understood that controlling the distance between the top surface 121a of the outermost first sub-structure and the top surface 121b of the adjacent first sub-structure to be less than or equal to 2 μm can control the roughness of the first texture structure within the required range, which is beneficial to improving the uniformity of the tunneling oxide layer formed on the first texture structure, resulting in better performance of the formed tunneling oxide layer, further inhibiting the locally high phosphorus concentration caused by phosphorus diffusion, reducing the contact resistivity, increasing the open-circuit voltage of the solar cell, and improving the fill factor and photoelectric conversion efficiency.

[0152] The one-dimensional dimension L of the top surface 121a of the outermost first sub-structure is less than or equal to 45 μm. Optionally, the one-dimensional dimension L is within the range of 2 μm to 45 μm. Here, the one-dimensional dimension L of the top surface may specifically be the length, width, diagonal length of the surface, the diameter of a circle, etc., which is not limited herein. In some embodiments, the one-dimensional dimension may refer to the average value of the one-dimensional dimensions of the top surfaces of multiple outermost first sub-structures within a preset range area on the back surface of the substrate. The average one-dimensional dimension of the top surface of the outermost first sub-structure may specifically be 2 μm, 5 μm, 8 μm, 12 μm, 15 μm, 18 μm, 20 μm, 25 μm, 28 μm, 30 μm, 35 μm, 40 μm, 42 μm, 40 μm or 45 μm, etc. Preferably, the average one-dimensional dimension of the top surface of the outermost first sub-structure is within the range of 10 μm to 15 μm.

[0153] In a specific embodiment, as Figure 3 shown, the first texture structure further includes two or more second sub-structures 122 arranged adjacently and non-stacked. The one-dimensional dimension L of the top surface of the second sub-structure 122 away from the back surface is less than or equal to 45 μm. Optionally, the one-dimensional dimension L of the first sub-structure 122 is within the range of 2 μm to 45 μm, and may specifically be 2 μm, 5 μm, 8 μm, 12 μm, 15 μm, 18 μm, 20 μm, 25 μm, 28 μm, 30 μm, 32 μm, 35 μm or 45 μm, etc.

[0154] Different from the typical pyramid-shaped micro-structures on the front surface, the top surfaces of the first sub-structure and / or the second sub-structure on the back surface are polygonal planes, and the shape of the polygonal plane includes at least one of a rhombus, a square, a trapezoid, an approximate rhombus, an approximate square, and an approximate trapezoid. It can be understood that in the actual manufacturing process, the top surface morphology of the first sub-structure or the second sub-structure presents an irregular polygonal plane, but generally presents morphological characteristics similar to a rhombus, a square, and a trapezoid.

[0155] Step S40, forming a tunneling oxide layer on the first texture structure on the back surface of the semiconductor substrate.

[0156] In some feasible implementation manners, after performing back surface etching on the semiconductor substrate, ozone oxidation method, high-temperature thermal oxidation method, nitric acid oxidation method, chemical vapor deposition method, low-pressure chemical vapor deposition method can be used for treatment to form the tunneling oxide layer 30.

[0157] In some embodiments, a temperature-variable process and chemical vapor deposition are used to deposit and form a tunneling oxide layer 30 on the back surface of a semiconductor substrate. During the deposition process, the heating rate is controlled to be 0.5°C / min to 3°C / min, the deposition temperature is 560°C to 620°C, and the deposition time is 3 min to 10 min.

[0158] Specifically, during the deposition process, the deposition temperature can be 560°C, 570°C, 580°C, 590°C, 600°C, 610°C, 615°C, 620°C, etc., the deposition time can be 3 min, 4 min, 5 min, 6 min, 7 min, 8 min, 9 min, 10 min, etc., and the heating rate can be 0.5°C / min, 0.8°C / min, 1.0°C / min, 1.2°C / min, 1.5°C / min, 2.0°C / min, 2.5°C / min, 3°C / min, etc. Of course, it can also be other values within the above ranges, which are not limited herein.

[0159] Preferably, a low-pressure chemical vapor deposition method is used to deposit and form the tunneling oxide layer 30 on the back surface of the semiconductor substrate, which can reduce the influence of excessive local doping concentration of the relatively thin tunneling oxide layer 30 during subsequent high-temperature doping treatment and reduce the fluctuation of the open-circuit voltage. The tunneling oxide layer 30 deposited by the temperature-variable process and low-pressure chemical vapor deposition method can increase the open-circuit voltage of the solar cell by 4 mV to 6 mV.

[0160] The tunneling oxide layer 30 can be a single-layer or multi-layer stacked structure of a silicon oxide layer, an aluminum oxide layer, a silicon oxynitride layer, a molybdenum oxide layer, a hafnium oxide layer, etc. In other embodiments, the tunneling oxide layer 30 can also be an oxygen-containing silicon nitride layer, an oxygen-containing silicon carbide layer, etc. The thickness of the tunneling oxide layer 30 is 0.8 nm to 2 nm. Specifically, the thickness of the tunneling oxide layer 30 is 0.8 nm, 0.9 nm, 1.0 nm, 1.2 nm, 1.4 nm, 1.6 nm, 1.8 nm, 2 nm, etc. The thickness of the tunneling oxide layer 30 refers to the thickness of the tunneling oxide layer relative to the formation surface. The thickness of the tunneling oxide layer 30 formed on the first texture structure can be obtained by performing cross-sectional observation and calculation with the normal direction of the inclined plane of the sub-structure as the thickness direction. If the thickness of the tunneling oxide layer 30 is too large, it is not conducive to reducing the contact resistance of the tunneling oxide layer. By controlling the thickness of the tunneling oxide layer, the reduction of the fill factor caused by the contact resistance can be suppressed.

[0161] Specifically, the bandgap width of the tunneling oxide layer 30 > 3.0 eV. It is generally difficult for carriers to be transported through the tunneling oxide layer 30 by thermal emission. However, due to the very thin tunneling oxide layer 30, carriers can pass through the tunneling oxide layer 30 through the tunneling effect. Therefore, the tunneling oxide layer with a thickness within 0.8 nm to 2 nm does not hinder the transport of majority carriers. As the thickness of the tunneling oxide layer gradually increases, the tunneling effect of majority carriers is affected, and it is difficult for carriers to be transported through the tunneling oxide layer 30, and the photoelectric conversion efficiency of the battery will gradually decrease. When the thickness of the tunneling oxide layer is too small, it cannot play a passivation role. Preferably, the tunneling oxide layer 30 is a silicon oxide layer, and the thickness of the tunneling oxide layer 30 is 0.8 nm to 1.5 nm.

[0162] As an alternative technical solution of the present application, as Figure 6 shown, the thickness D1 of the tunneling oxide layer on the top surface of the outermost first sub-structure is less than the thickness D2 of the tunneling oxide layer formed on the side surface of the outermost first sub-structure. Specifically, the thickness difference (D2 - D1) between the tunneling oxide layer on the top surface of the outermost first sub-structure and the tunneling oxide layer formed on the side surface of the outermost sub-structure is less than or equal to 0.15 nm. The thickness difference can specifically be 0.14 nm, 0.13 nm, 0.12 nm, 0.11 nm, 0.10 nm, 0.09 nm, 0.08 nm, 0.07 nm, 0.06 nm, 0.05 nm, 0.04 nm, etc. When the thickness difference between the tunneling oxide layer on the top surface of the outermost first sub-structure and the tunneling oxide layer formed on the side surface of the outermost sub-structure is too large, the thickness uniformity of the tunneling oxide layer is poor, and the current density of the solar cell is easily affected, and the open-circuit voltage of the solar cell decreases.

[0163] Step S50, deposit a polysilicon layer on the surface of the tunneling oxide layer and perform doping treatment on the polysilicon layer to form a doped conductive layer, and the conductive type of the doped conductive layer is the same as that of the semiconductor substrate.

[0164] In some feasible embodiments, any one of physical vapor deposition, chemical vapor deposition, plasma-enhanced chemical vapor deposition, and atomic layer deposition is used to deposit a polysilicon layer on the surface of the tunneling oxide layer. The chemical vapor deposition method can be low-pressure chemical vapor deposition or atmospheric pressure chemical vapor deposition.

[0165] In a specific embodiment, the deposition of the tunneling oxide layer and the polysilicon layer and the doping of the polysilicon layer are all formed in a low-pressure chemical vapor deposition device.

[0166] The specific steps include:

[0167] First, place the alkali-polished semiconductor substrate in a deposition device, introduce 20L to 60L of an oxygen source (such as oxygen, nitrous oxide, ozone), heat the temperature in the deposition device to 560°C to 620°C at a heating rate of 0.5°C / min to 3°C / min, and the deposition time is 3min to 10min to form a tunneling oxide layer 30;

[0168] After the oxygen introduction ends, enter a constant temperature stage, and then introduce an appropriate amount of silane gas to form a polysilicon layer;

[0169] Finally, perform in-situ doping on the polysilicon layer to form a doped conductive layer 40.

[0170] In some embodiments, the doped conductive layer 40 may be a doped polysilicon layer, and the doped conductive layer 40 and the semiconductor substrate have doping elements of the same conduction type.

[0171] In other embodiments, a microcrystalline silicon layer or an amorphous silicon layer may also be deposited on the surface of the tunneling oxide layer 30 and in-situ doped to form a doped microcrystalline silicon layer or a doped amorphous silicon layer, that is, the doped conductive layer 40.

[0172] When the semiconductor substrate 10 is an N-type single-crystalline silicon substrate, the doped conductive layer 40 is an N-type doped polysilicon layer, an N-type doped microcrystalline silicon layer or an N-type doped amorphous silicon layer, and the doping element may be an N-type doping element such as phosphorus.

[0173] In some embodiments, the thickness range of the doped conductive layer 40 is 60nm - 200nm. For example, for an N-type doped polysilicon layer, the refractive index range of the doped conductive layer 40 is 3.5 - 4.5.

[0174] After step S50 and before step S60, the above method further includes:

[0175] After depositing the in-situ doped polysilicon layer, a high-temperature annealing treatment and a cleaning treatment are performed.

[0176] The present application embodiment does not limit the specific operation manner of this high-temperature annealing treatment and cleaning treatment. Exemplarily, the high-temperature annealing treatment is performed on the deposited polysilicon layer, which can make the polysilicon layer crystallize better, and the annealing temperature range can be 700°C to 1000°C.

[0177] Through the high-temperature annealing treatment, the diffusion of pentavalent phosphorus atoms forms a doped polysilicon layer. After the annealing treatment, the microcrystalline silicon phase of the crystalline silicon is transformed into the polysilicon phase, and phosphorus is deposited on the surface of the semiconductor substrate to form phosphorus silicate glass (PSG).

[0178] The cleaning process is to remove the phosphosilicate glass layer (PSG) formed during the phosphorus doping process. Understandably, during phosphorus diffusion, due to the high concentration of phosphorus on the surface of the semiconductor substrate, a phosphosilicate glass layer (PSG) is usually formed. This phosphosilicate glass layer has a metal gettering effect and will affect the normal operation of the solar cell, so it needs to be removed.

[0179] In a specific embodiment, the back surface of the semiconductor substrate can be placed downward in a chain pickling device (the belt speed of the chain device is 1.0 m / min to 2.0 m / min). The semiconductor substrate enters the acid tank, and the phosphosilicate glass layer (PSG) formed by phosphorus diffusion on the back surface is etched off. A prepared mixed acid is provided in the acid tank. The mixed acid includes a hydrofluoric acid solution with a mass concentration of 2% to 10% and a hydrochloric acid solution with a mass concentration of 2% to 10%. The pickling temperature is 15°C to 25°C, and the pickling time is about 30 s to 60 s. There is a water film covering the front surface of the semiconductor substrate, and the borosilicate glass layer (BSG) on the front surface of the semiconductor substrate can also serve as a protective layer to prevent the front surface of the semiconductor substrate from reacting with the mixed acid during the process of removing the phosphosilicate glass layer (PSG).

[0180] It should be noted that after pickling, water washing is required. The water washing time is 10 to 20 s, and the water washing temperature can be 15°C to 25°C. Of course, after water washing, the semiconductor substrate can also be dried.

[0181] Step S60, form a first passivation layer on the front surface of the conductor substrate.

[0182] In some embodiments, the first passivation layer 20 can be deposited by plasma-enhanced chemical vapor deposition. Of course, other methods can also be used, such as organic chemical vapor deposition. The specific implementation manner of the first passivation layer 20 in the embodiments of the present application is not limited.

[0183] The first passivation layer 20 can include, but is not limited to, single-layer or stacked structures such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, etc. Of course, other types of passivation layers can also be used for the first passivation layer. The specific material of the first passivation layer in the present application is not limited. For example, in other embodiments, the first passivation layer can also be a stack of silicon dioxide and silicon nitride. The above first passivation layer can produce a good passivation effect on the semiconductor substrate and help improve the conversion efficiency of the battery.

[0184] Step S70, form a second passivation layer on the surface of the doped conductive layer.

[0185] The second passivation layer 50 can be deposited by plasma-enhanced chemical vapor deposition. Of course, other methods can also be used, such as organic chemical vapor deposition. The specific implementation manner of the second passivation layer 50 in the embodiments of the present application is not limited.

[0186] As an alternative technical solution of the present application, the second passivation layer 50 includes at least one of a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer. The thickness of the second passivation layer 50 is 70 nm - 120 nm. For example, the second passivation layer 50 is a silicon nitride layer, the silicon nitride layer has a low silicon-nitrogen ratio, the refractive index range of the silicon nitride layer is 1.7 - 2.1, the refractive index of the silicon nitride layer can be 1.7, 1.8, 1.9, 2.0, 2.1, etc., and of course it can also be other values within the above range, which is not limited herein. By controlling the refractive index of the silicon nitride layer to have a low silicon-nitrogen ratio, the formed second passivation layer 50 can reduce the contact resistivity during metallization treatment, thereby further reducing the contact resistivity of the solar cell.

[0187] In some embodiments, when the second passivation layer 50 is a stacked silicon nitride layer and a silicon oxide layer or a stacked silicon nitride layer and a silicon oxynitride layer, the silicon nitride layer is located on the surface of the doped conductive layer, and the silicon oxide layer or the silicon oxynitride layer is located on the surface of the silicon nitride layer.

[0188] Further, after step S70, the method further includes:

[0189] Screen-printing and sintering the semiconductor substrate to form electrodes.

[0190] In some embodiments, the solar cell further includes a first electrode 60 and a second electrode 70. The first electrode 60 forms an ohmic contact with the P-type doped layer (e.g., boron-doped diffusion layer) on the front surface of the semiconductor substrate 10 through the first passivation layer 20, and the second electrode 70 forms an ohmic contact with the doped conductive layer 40 through the second passivation layer 50. The doped conductive layer 40 and the tunneling oxide layer 30 form a passivated contact structure. The first electrode 60 and the second electrode 70 can be formed by sintering a metal conductive paste coated on the surfaces of the first passivation layer and the second passivation layer. In some embodiments, the materials of the first electrode 60 or the second electrode 70 include metal materials such as silver, aluminum, copper, and nickel.

[0191] The following are solar cell Examples 1 to 13 and Comparative Examples 1 to 4 prepared according to the above method, and the specific process parameters are shown in Table 1:

[0192]

[0193] Table 2. Related preparation process parameters of the solar cell

[0194]

[0195] Table 3. Test results of the solar cell

[0196]

[0197] According to Embodiments 1 to 13, by controlling the distance between sub-structures in the first texture structure on the rear surface of the semiconductor substrate within an ideal range, the roughness of the rear surface of the semiconductor substrate can be ensured to be within a suitable range, which is beneficial to improving the uniformity of the tunneling oxide layer formed on the first texture structure. The formed tunneling oxide layer has better performance, and further inhibits the excessively high local doping concentration of the doped conductive layer, effectively reducing the contact resistivity, increasing the open-circuit voltage of the solar cell, and improving the fill factor and photoelectric conversion efficiency.

[0198] In the first texture structure of the solar cell of Comparative Example 1, in the direction away from the rear surface and perpendicular to the rear surface, the distance between the top surface of the outermost first sub-structure and the top surface of the adjacent first sub-structure is greater than 2 μm. The smaller the one-dimensional size of the top surface of the outermost first sub-structure, the thicker the deposited tunneling oxide layer, and the uniformity of the tunneling oxide layer decreases, resulting in an excessively high local doping concentration of the doped conductive layer formed on the surface of the tunneling oxide layer. The contact resistivity increases compared with Embodiment 1, resulting in a decrease in the open-circuit voltage of the solar cell, and the fill factor and photoelectric conversion efficiency also decrease accordingly.

[0199] The solar cell of Comparative Example 2 was not subjected to alkali polishing treatment after texturing, and the rear surface was a pyramid-shaped micro-structure. The uniformity of the tunneling oxide layer deposited on the pyramid-shaped micro-structure decreased, easily resulting in an excessively high local doping concentration of the doped conductive layer formed on the surface of the tunneling oxide layer. The contact resistivity increased compared with Embodiment 1, resulting in a decrease in the open-circuit voltage of the solar cell, and the fill factor and photoelectric conversion efficiency also decreased accordingly.

[0200] Although the solar cell of Comparative Example 3 can inhibit the excessively high local doping concentration of the doped conductive layer through the treatment of the sub-structures of the first texture structure, due to the use of a silicon nitride layer with a high silicon-nitrogen ratio, it is difficult to further reduce the contact resistivity during the metallization process. Compared with Embodiment 1, by controlling the distance between the sub-structures in the first texture structure on the rear surface of the semiconductor substrate and controlling the refractive index of the second passivation layer, the two work together to better reduce the contact resistivity, increase the open-circuit voltage, fill factor and photoelectric conversion efficiency of the solar cell.

[0201] Although the solar cell of Comparative Example 4 can inhibit the excessively high local doping concentration of the doped conductive layer through the treatment of the sub-structures of the first texture structure, due to the use of an alumina layer and a silicon nitride layer with a relatively low overall refractive index as the first passivation layer, the contact resistivity increases during the metallization process.

[0202] Although the present application is disclosed above in preferred embodiments, it is not intended to limit the claims. Any person skilled in the art can make several possible changes and modifications without departing from the concept of the present application. Therefore, the protection scope of the present application shall be subject to the scope defined by the claims of the present application.

Claims

1. A solar cell, characterized in that, the solar cell comprises: a semiconductor substrate, wherein, the rear surface of the semiconductor substrate has a first texture structure; the front surface of the semiconductor substrate has a second texture structure; a first passivation layer located on the second texture structure on the front surface of the semiconductor substrate; a tunneling oxide layer located on the first texture structure on the rear surface of the semiconductor substrate; a doped conductive layer located on the surface of the tunneling oxide layer; and a second passivation layer located on the surface of the doped conductive layer; the first texture structure presents a non-pyramidal microstructure morphology, including two or more first sub-structures that are at least partially stacked, the top surface of the first sub-structure is a polygonal plane; among the two or more first sub-structures that are at least partially stacked, the one-dimensional size of the top surface of the outermost first sub-structure is less than or equal to 45 μm; among the two or more first sub-structures that are at least partially stacked, in a direction away from the rear surface and perpendicular to the rear surface, the distance between the top surface of the outermost first sub-structure and the top surface of the first sub-structure adjacent thereto is less than or equal to 2 μm; wherein, the one-dimensional size of the top surface includes any one of the length of the top surface, the width of the top surface, the diagonal length of the top surface, and the diameter of the top surface; the second texture structure includes pyramidal microstructures, the pyramidal microstructures include a top away from the front surface of the semiconductor substrate and a bottom close to the front surface of the semiconductor substrate, in a direction away from the front surface and perpendicular to the front surface, the distance between the top and the bottom of the pyramidal microstructures is less than or equal to 5 μm.

2. The solar cell according to claim 1, characterized in that, the top surface of the first sub-structure is at least one of a rhombus, a square, and a trapezoid.

3. The solar cell according to claim 1, characterized in that, the thickness of the tunneling oxide layer on the top surface of the outermost first sub-structure is less than the thickness of the tunneling oxide layer on the side surface of the outermost first sub-structure.

4. The solar cell according to claim 1, characterized in that, the first texture structure further includes two or more second sub-structures arranged adjacently and non-stacked, and the one-dimensional size of the top surface of the second sub-structure away from the rear surface is less than or equal to 45 μm.

5. The solar cell according to claim 4, characterized in that, the top surface of the second sub-structure is a polygonal plane.

6. The solar cell according to claim 1, characterized in that, the tunneling oxide layer includes at least one of a silicon oxide layer, an aluminum oxide layer, a silicon oxynitride layer, a molybdenum oxide layer, and a hafnium oxide layer, the thickness of the tunneling oxide layer is 0.8 nm to 2 nm.

7. The solar cell according to claim 1, characterized in that, the second passivation layer includes at least one of a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer, the thickness of the second passivation layer is 70 nm - 120 nm.

8. The solar cell according to claim 1, characterized in that, The first passivation layer includes at least one of a silicon oxide layer, a silicon nitride layer, an aluminum oxide layer, and a silicon oxynitride layer.

9. The solar cell according to claim 1, wherein, the first passivation layer is a stacked passivation structure of an aluminum oxide layer and a silicon nitride layer, the thickness range of the aluminum oxide layer is 2 nm to 10 nm, and the thickness of the silicon nitride layer is 50 nm to 110 nm.

10. The solar cell according to claim 1, wherein, the first passivation layer is a stacked passivation structure of an aluminum oxide layer, a silicon nitride layer, and a silicon oxynitride layer stacked in sequence, the thickness range of the aluminum oxide layer is 2 nm to 10 nm, the thickness of the silicon nitride layer is 40 nm to 80 nm, and the thickness of the silicon oxynitride layer is 10 nm to 60 nm.

11. The solar cell according to any one of claims 1 to 10, wherein, the semiconductor substrate is an N-type single crystal silicon substrate, the doped conductive layer is an N-type doped polysilicon layer, an N-type doped microcrystalline silicon layer, or an N-type doped amorphous silicon layer, the thickness of the doped conductive layer is 60 nm to 200 nm.

12. A photovoltaic module, wherein, the photovoltaic module includes a plurality of solar cell strings, and the solar cell strings include the solar cell according to any one of claims 1 to 11.

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