Light-emitting diode manufacturing method and light-emitting diode

Abstract

The present application provides a method for manufacturing a light-emitting diode and a light-emitting diode. The method for manufacturing a light-emitting diode includes providing a substrate; sequentially growing a buffer layer, at least one three-dimensional structure layer, at least one two-dimensional structure layer, an N-type doped layer, a quantum well light-emitting layer, and a P-type doped layer on the substrate; wherein, the first growth conditions of the three-dimensional structure layer are: rotation speed of 500 - 1300 revolutions per minute, temperature of 1000 - 1200 °C, and pressure of 300 - 600 Torr; the first growth conditions of the two-dimensional structure layer are: rotation speed of 500 - 1300 revolutions per minute, temperature of 1000 - 1200 °C, and pressure of 10 - 300 Torr; the second growth conditions of the three-dimensional structure layer are: rotation speed of 40 - 100 revolutions per minute, temperature of 1000 - 1200 °C, and pressure of 100 - 500 Torr; the second growth conditions of the two-dimensional structure layer are: rotation speed of 40 - 100 revolutions per minute, temperature of 1000 - 1200 °C, and pressure of 10 - 100 Torr. The present application is beneficial to reducing the warpage degree of the epitaxial structure layer and beneficial to improving the uniformity of the wavelength of the light-emitting diode.

Description

Technical Field

[0001] This application relates to the field of semiconductor lighting technology, and particularly to a method for manufacturing a light-emitting diode and a light-emitting diode. Background Art

[0002] A common technique for growing light-emitting diodes is to use heteroepitaxy, that is, to grow an epitaxial structure layer on a substrate. When growing a light-emitting diode (LED) using Metal-Organic Chemical Vapor Deposition (MOCVD for short), the epitaxial structure layer has a very large impact on the performance of the light-emitting diode.

[0003] In related technologies, when manufacturing a light-emitting diode, the general approach is to first grow a nucleation layer on a sapphire substrate, and then grow a three-dimensional structure layer (also known as an island structure layer) on the basis of the nucleation layer. By growing a certain thickness of the three-dimensional structure layer on the basis of the nucleation layer, the lattice mismatch caused by heteroepitaxy can be reduced, thereby reducing the defect density.

[0004] However, in the solution of related technologies, the three-dimensional structure layer is grown at low temperature, high pressure, and low rotation speed, and the crystal quality of the grown three-dimensional structure layer is poor, resulting in a large warping of the epitaxial structure layer, which affects the temperature uniformity at the bottom of the epitaxial structure layer. The poor temperature uniformity will directly affect the wavelength uniformity, and the wavelength uniformity of the light-emitting diode is a key parameter of the product, and the wavelength uniformity directly affects the sorting cost in the subsequent processing process. Summary of the Invention

[0005] In order to overcome the above defects in related technologies, the purpose of this application is to provide a method for manufacturing a light-emitting diode and a light-emitting diode, which is beneficial to reducing the warping degree of the epitaxial structure layer, thereby being beneficial to improving the wavelength uniformity of the light-emitting diode.

[0006] On the one hand, this application provides a method for manufacturing a light-emitting diode, including:

[0007] Providing a substrate;

[0008] Growing a buffer layer on the substrate;

[0009] Growing at least one three-dimensional structure layer and at least one two-dimensional structure layer alternately on the buffer layer;

[0010] Growing an N-type doped layer on the uppermost two-dimensional structure layer;

[0011] Growing a quantum well light-emitting layer on the N-type doped layer;

[0012] A P-type doped layer is grown on the quantum well light-emitting layer;

[0013] Wherein, the three-dimensional structure layer and the two-dimensional structure layer can be grown under the first growth condition or the second growth condition;

[0014] The first growth condition of the three-dimensional structure layer is: rotation speed 500 - 1300 revolutions per minute, temperature 1000 - 1200 °C, pressure 300 - 600 Torr; the first growth condition of the two-dimensional structure layer is: rotation speed 500 - 1300 revolutions per minute, temperature 1000 - 1200 °C, pressure 10 - 300 Torr;

[0015] The second growth condition of the three-dimensional structure layer is: rotation speed 40 - 100 revolutions per minute, temperature 1000 - 1200 °C, pressure 100 - 500 Torr; the second growth condition of the two-dimensional structure layer is: rotation speed 40 - 100 revolutions per minute, temperature 1000 - 1200 °C, pressure 10 - 100 Torr.

[0016] For the light-emitting diode manufacturing method as described above, optionally, the first growth condition of the three-dimensional structure layer is: rotation speed 1200 revolutions per minute, pressure 500 Torr; the first growth condition of the two-dimensional structure layer is: rotation speed 1200 revolutions per minute, pressure 100 Torr;

[0017] The second growth condition of the three-dimensional structure layer is: rotation speed 50 revolutions per minute, pressure 300 Torr; the second growth condition of the two-dimensional structure layer is: rotation speed 50 revolutions per minute, pressure 50 Torr.

[0018] For the light-emitting diode manufacturing method as described above, optionally, the first growth condition of the three-dimensional structure layer further includes: the flow rate ratio of N2:H2:NH3 introduced is 75:150:56; the first growth condition of the two-dimensional structure layer further includes: the flow rate ratio of N2:H2:NH3 introduced is 64:120:50;

[0019] The second growth condition of the three-dimensional structure layer further includes: the flow rate ratio of N2:H2:NH3 introduced is 15:6:27; the second growth condition of the two-dimensional structure layer further includes: the flow rate ratio of N2:H2:NH3 introduced is 15:6:27.

[0020] For the light-emitting diode manufacturing method as described above, optionally, the thickness of each layer of the three-dimensional structure layer is 10 - 2000 nm; the thickness of each layer of the two-dimensional structure layer is 10 - 2000 nm.

[0021] For the light-emitting diode manufacturing method as described above, optionally, the thickness of each layer of the three-dimensional structure layer is 120 - 1500 nm; the thickness of each layer of the two-dimensional structure layer is 50 - 1000 nm.

[0022] The method for manufacturing a light-emitting diode as described above. Optionally, the three-dimensional structure layer has 2 - 15 layers; the two-dimensional structure layer has 2 - 15 layers.

[0023] The method for manufacturing a light-emitting diode as described above. Optionally, both the three-dimensional structure layer and the two-dimensional structure layer are gallium nitride layers.

[0024] The method for manufacturing a light-emitting diode as described above. Optionally, the substrate includes a sapphire substrate, a silicon substrate, or a silicon carbide substrate.

[0025] The method for manufacturing a light-emitting diode as described above. Optionally, the buffer layer, the three-dimensional structure layer, the two-dimensional structure layer, the N-type doping layer, the quantum well light-emitting layer, and the P-type doping layer are all gallium nitride layers.

[0026] On the other hand, the present application provides a light-emitting diode manufactured by using the method for manufacturing a light-emitting diode described in any one of the above.

[0027] The present application provides a method for manufacturing a light-emitting diode and a light-emitting diode. The method for manufacturing a light-emitting diode includes providing a substrate; growing a buffer layer on the substrate; alternately growing at least one three-dimensional structure layer and at least one two-dimensional structure layer on the buffer layer; growing an N-type doping layer on the uppermost two-dimensional structure layer; growing a quantum well light-emitting layer on the N-type doping layer; growing a P-type doping layer on the quantum well light-emitting layer; wherein, the three-dimensional structure layer and the two-dimensional structure layer can be grown under a first growth condition or a second growth condition; the first growth condition for the three-dimensional structure layer is: rotation speed 500 - 1300 revolutions per minute, temperature 1000 - 1200 °C, pressure 300 - 600 Torr; the first growth condition for the two-dimensional structure layer is: rotation speed 500 - 1300 revolutions per minute, temperature 1000 - 1200 °C, pressure 10 - 300 Torr; the second growth condition for the three-dimensional structure layer is: rotation speed 40 - 100 revolutions per minute, temperature 1000 - 1200 °C, pressure 100 - 500 Torr; the second growth condition for the two-dimensional structure layer is: rotation speed 40 - 100 revolutions per minute, temperature 1000 - 1200 °C, pressure 10 - 100 Torr. By the above method, the present application alternately grows at least one three-dimensional structure layer and at least one two-dimensional structure layer under the first growth condition or the second growth condition, which is beneficial to reducing the warpage of the epitaxial structure layer and improving the uniformity of the wavelength of the light-emitting diode. Description of the Drawings

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the following will briefly introduce the drawings required for the description of the embodiments or the related art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0029] Figure 1 Schematic structural diagram of a light-emitting diode manufacturing method provided by an embodiment of the present application;

[0030] Figure 2 Schematic structural diagram of a light-emitting diode provided by an embodiment of the present application;

[0031] Figure 3 Schematic structural diagram of a three-dimensional structure layer and a two-dimensional structure layer provided by an embodiment of the present application.

[0032] Reference numerals:

[0033] 100 - Substrate;

[0034] 200 - Buffer layer;

[0035] 300 - Three-dimensional structure layer;

[0036] 400 - Two-dimensional structure layer. Detailed implementation manners

[0037] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application.

[0038] All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application. Without conflict, the following embodiments and the features in the embodiments may be combined with each other.

[0039] In the related art, when manufacturing a light-emitting diode, the common practice is to first grow a nucleation layer on a sapphire substrate, and then grow a three-dimensional structure layer (also known as an island structure layer) on the basis of the nucleation layer. By growing a certain thickness of the three-dimensional structure layer on the basis of the nucleation layer, the lattice mismatch generated by heteroepitaxy can be reduced, thereby reducing the defect density. However, with the solution of the related art, the three-dimensional structure layer is grown at low temperature, high pressure, and low rotation speed, and the crystal quality of the grown three-dimensional structure layer is poor, resulting in a large warpage of the epitaxial structure layer, thereby affecting the uniformity of the temperature at the bottom of the epitaxial structure layer. The poor temperature uniformity will directly affect the uniformity of the wavelength, and the uniformity of the wavelength of the light-emitting diode is a key parameter of the product, and the uniformity of the wavelength directly affects the sorting cost in the subsequent processing process.

[0040] In view of this, the present application aims to provide a method for manufacturing a light-emitting diode and a light-emitting diode. By alternately growing at least one three-dimensional structure layer and at least one two-dimensional structure layer on a substrate, and controlling the growth of the three-dimensional structure layer under high rotation speed, high temperature, and high pressure conditions, and the growth of the two-dimensional structure layer under high rotation speed, high temperature, and low pressure conditions, it is beneficial to reduce the warpage of the epitaxial structure layer and improve the uniformity of the wavelength of the light-emitting diode.

[0041] The content of the embodiments of the present application will be described in detail below with reference to the accompanying drawings, so that those skilled in the art can understand the content of the present application in more detail.

[0042] Figure 1 It is a structural schematic diagram of a method for manufacturing a light-emitting diode provided by an embodiment of the present application.

[0043] Please refer to Figure 1 , this embodiment provides a method for manufacturing a light-emitting diode, including:

[0044] Step S110: Provide a substrate.

[0045] In this embodiment, the substrate can be any one of a sapphire (Patterned Sapphire Substrate, abbreviated as PSS) substrate, a silicon substrate, or a silicon carbide substrate.

[0046] Step S120: Grow a buffer layer on the substrate.

[0047] In this embodiment, the substrate can be subjected to high-temperature purification before growing the buffer layer; the buffer layer can be a gallium nitride layer.

[0048] Step S130: Alternately grow at least one three-dimensional structure layer and at least one two-dimensional structure layer on the buffer layer.

[0049] In this embodiment, the three-dimensional structure layer and the two-dimensional structure layer can be grown under the first growth condition or the second growth condition; wherein, the first growth condition refers to the growth condition in the first device, and the second growth condition refers to the growth condition in the second device; the first device is a VEECO K series model, and the second device is an AIXTRON CRIUS series model.

[0050] In this embodiment, the first growth conditions of the three-dimensional structure layer are: rotation speed of 500 - 1300 revolutions per minute, temperature of 1000 - 1200 °C, and pressure of 300 - 600 Torr; the first growth conditions of the two-dimensional structure layer are: rotation speed of 500 - 1300 revolutions per minute, temperature of 1000 - 1200 °C, and pressure of 10 - 300 Torr; the second growth conditions of the three-dimensional structure layer are: rotation speed of 40 - 100 revolutions per minute, temperature of 1000 - 1200 °C, and pressure of 100 - 500 Torr; the second growth conditions of the two-dimensional structure layer are: rotation speed of 40 - 100 revolutions per minute, temperature of 1000 - 1200 °C, and pressure of 10 - 100 Torr.

[0051] Step S140: Grow an N-type doped layer on the topmost two-dimensional structure layer.

[0052] In this embodiment, the N-type doped layer can be a gallium nitride layer.

[0053] Step S150: Grow a quantum well light-emitting layer on the N-type doped layer.

[0054] In this embodiment, the quantum well light-emitting layer can be a gallium nitride layer.

[0055] Step S160: Grow a P-type doped layer on the quantum well light-emitting layer.

[0056] In this embodiment, the P-type doped layer can be a gallium nitride layer.

[0057] In this embodiment, at least one three-dimensional structure layer and at least one two-dimensional structure layer are alternately grown using the first growth conditions or the second growth conditions, such that the three-dimensional structure layer is grown under high rotation speed, high temperature, and high pressure conditions, and the two-dimensional structure layer is grown under high rotation speed, high temperature, and low pressure conditions, thereby facilitating the reduction of the warpage of the epitaxial structure layer and improving the uniformity of the wavelength of the light-emitting diode.

[0058] Preferably, in this embodiment, the first growth conditions of the three-dimensional structure layer are: rotation speed of 1200 revolutions per minute and pressure of 500 Torr; the first growth conditions of the two-dimensional structure layer are: rotation speed of 1200 revolutions per minute and pressure of 100 Torr. The second growth conditions of the three-dimensional structure layer are: rotation speed of 50 revolutions per minute and pressure of 300 Torr; the second growth conditions of the two-dimensional structure layer are: rotation speed of 50 revolutions per minute and pressure of 50 Torr.

[0059] By adopting the above method, the warpage of the epitaxial structure layer can be better reduced, and the uniformity of the wavelength of the light-emitting diode can be improved.

[0060] Further, the first growth conditions of the three-dimensional structure layer in this embodiment further include: the flow rate ratio of N2:H2:NH3 introduced is 75:150:56; the first growth conditions of the two-dimensional structure layer further include: the flow rate ratio of N2:H2:NH3 introduced is 64:120:50. The second growth conditions of the three-dimensional structure layer further include: the flow rate ratio of N2:H2:NH3 introduced is 15:6:27; the second growth conditions of the two-dimensional structure layer further include: the flow rate ratio of N2:H2:NH3 introduced is 15:6:27.

[0061] By controlling the flow rate ratio of N2:H2:NH3 introduced, the growth of the three-dimensional structure layer and the two-dimensional structure layer can be better achieved, which is beneficial to reducing the warpage of the epitaxial structure layer and improving the uniformity of the light-emitting diode wavelength.

[0062] In this embodiment, the thickness of each three-dimensional structure layer is 10 - 2000 nm; the thickness of each two-dimensional structure layer is 10 - 2000 nm. The specific thickness of each layer can be selected according to actual needs.

[0063] Preferably, in this embodiment, the thickness of each three-dimensional structure layer is 120 - 1500 nm; the thickness of each two-dimensional structure layer is 50 - 1000 nm.

[0064] Controlling the three-dimensional structure layer and the two-dimensional structure layer within the above thickness range is beneficial to reducing the warpage of the epitaxial structure layer and improving the uniformity of the light-emitting diode wavelength.

[0065] Optionally, in this embodiment, there are 2 - 15 layers of the three-dimensional structure layer; there are 2 - 15 layers of the two-dimensional structure layer, and the number of layers of the three-dimensional structure layer and the two-dimensional structure layer is equal.

[0066] The following lists several specific embodiments of manufacturing a light-emitting diode.

[0067] Embodiment A:

[0068] Using the Veeco K series model, the growth conditions of the three-dimensional structure layer are a rotation speed of 1100 revolutions per minute, a temperature of 1050 °C, and a pressure of 500 Torr; the growth conditions of the two-dimensional structure layer are a rotation speed of 1100 revolutions per minute, a temperature of 1080 °C, and a pressure of 100 Torr.

[0069] First, place the sapphire substrate in the reaction chamber, control the flow rate ratio of N2:H2:NH3 introduced to be 0:120:0 liters per minute (Standard Liter per Minute, abbreviated as SLM), the pressure of the reaction chamber is 200 Torr, raise the temperature to 1080 °C, and stabilize for 300 seconds to perform high-temperature purification of the substrate.

[0070] Then, the temperature is lowered to 540 °C, and the flow rate ratio of N2:H2:NH3 is controlled to be 75:150:56 L / min. The pressure in the reaction chamber is controlled at 500 Torr, and a low-temperature gallium nitride buffer layer with a thickness of 35 nm is grown.

[0071] Thereafter, the temperature is raised to 1050 °C, and the flow rate ratio of N2:H2:NH3 is controlled to be 75:150:56 L / min. The pressure in the reaction chamber is controlled at 500 Torr, and the carrier disk rotation speed is controlled at 1100 rpm, and a three-dimensional structure layer with a thickness of 400 nm is grown.

[0072] Thereafter, the temperature is raised to 1080 °C, and the flow rate ratio of N2:H2:NH3 is controlled to be 64:120:50 L / min. The pressure in the reaction chamber is controlled at 100 Torr, and the carrier disk rotation speed is controlled at 1100 rpm, and a two-dimensional structure layer with a thickness of 100 nm is grown.

[0073] Thereafter, the above steps are repeated, and the three-dimensional structure layer and the two-dimensional structure layer are each grown three times, and the total thickness of the three-dimensional structure layer and the two-dimensional structure layer is controlled at 1500 nm.

[0074] Thereafter, the temperature is maintained at 1050 °C, and the flow rate ratio of N2:H2:NH3 is controlled to be 64:120:50 L / min. The pressure in the reaction chamber is controlled at 200 Torr, and an N-type gallium nitride N-GaN layer with a thickness of 1000 nm is grown.

[0075] Thereafter, the temperature is controlled at 750 - 880 °C, and the flow rate ratio of N2:H2:NH3 is controlled to be 72:0:40 L / min. The pressure in the reaction chamber is controlled at 200 Torr. A quantum well is grown at 760 °C, and a quantum barrier is grown at 860 °C, with a total of 13 pairs of quantum well light-emitting layers.

[0076] Thereafter, the temperature is raised to 960 °C, and the flow rate ratio of N2:H2:NH3 is controlled to be 64:120:50 L / min. The pressure in the reaction chamber is controlled at 200 Torr, and a P-type gallium nitride P-GaN layer with a thickness of 200 nm is grown.

[0077] Finally, the epitaxial structure layer of this embodiment and the epitaxial structure layer using conventional technology are tested using an X-ray diffractometer. It can be known from the test that the crystal plane indices of 002 and 102 of the epitaxial structure layer of this embodiment are reduced from (270, 290) to (220, 236), that is, the dislocation density of the crystal is effectively reduced. By measuring the warpage degree, the warpage degree of the epitaxial structure layer is reduced from 120 to 80. The epitaxial structure layer is processed into a chip, and it can be obtained from the test that the performance of various optoelectronic parameters has been greatly improved.

[0078] Example B:

[0079] Using the K series models of Veeco, the growth conditions for the three-dimensional structure layer are a rotation speed of 1100 revolutions per minute, a temperature of 1050 °C, and a pressure of 550 Torr; the growth conditions for the two-dimensional structure layer are a rotation speed of 1100 revolutions per minute, a temperature of 1080 °C, and a pressure of 100 Torr.

[0080] First, place the sapphire substrate into the reaction chamber, control the flow rate ratio of N2:H2:NH3 introduced into the chamber to be 0:120:0 liters per minute, the pressure in the reaction chamber to be 200 Torr, raise the temperature to 1080 °C, and stabilize for 300 seconds to perform high-temperature purification of the substrate.

[0081] Then, lower the temperature to 540 °C, control the flow rate ratio of N2:H2:NH3 introduced into the chamber to be 75:150:56 liters per minute, control the pressure in the reaction chamber at 500 Torr, and grow a low-temperature gallium nitride buffer layer with a thickness of 35 nm.

[0082] After that, raise the temperature to 1050 °C, control the flow rate ratio of N2:H2:NH3 introduced into the chamber to be 75:150:56 liters per minute, control the pressure in the reaction chamber at 500 Torr, and control the carrier disk rotation speed at 1100 revolutions per minute to grow a three-dimensional structure layer with a thickness of 200 nm.

[0083] After that, raise the temperature to 1080 °C, control the flow rate ratio of N2:H2:NH3 introduced into the chamber to be 64:120:50 liters per minute, control the pressure in the reaction chamber at 100 Torr, control the carrier disk rotation speed at 1100 revolutions per minute, and grow a two-dimensional structure layer with a total thickness of 60 nm.

[0084] After that, repeat the above steps to grow the three-dimensional structure layer and the two-dimensional structure layer six times each, and control the total thickness of the three-dimensional structure layer and the two-dimensional structure layer at 1560 nm.

[0085] After that, maintain the temperature at 1050 °C, control the flow rate ratio of N2:H2:NH3 introduced into the chamber to be 64:120:50 liters per minute, control the pressure in the reaction chamber at 200 Torr, and grow an N-type gallium nitride N-GaN layer with a thickness of 1000 nm.

[0086] After that, control the temperature at 750 - 880 °C, control the flow rate ratio of N2:H2:NH3 introduced into the chamber to be 72:0:40 liters per minute, control the pressure in the reaction chamber at 200 Torr, grow quantum wells at 760 °C, grow quantum barriers at 860 °C, and there are a total of 13 pairs of quantum well light-emitting layers.

[0087] After that, raise the temperature to 960 °C, control the flow rate ratio of N2:H2:NH3 introduced into the chamber to be 64:120:50 liters per minute, control the pressure in the reaction chamber at 200 Torr, and grow a P-type gallium nitride P-GaN layer with a thickness of 200 nm.

[0088] Finally, the epitaxial structure layer of this embodiment and the epitaxial structure layer of the above-mentioned Embodiment A were tested using an X-ray diffractometer. It was found through testing that for the epitaxial structure layer of this embodiment, the crystal plane indices of 002 and 102 decreased from (220, 236) to (200, 206), that is, the dislocation density of the crystal was effectively reduced. By measuring the warp, the warp of the epitaxial structure layer decreased from 80 to 60. That is, through effective optimization of the thickness and number of periods of the three-dimensional structure layer and the two-dimensional structure layer, various properties have been greatly improved.

[0089] Embodiment C:

[0090] Using the K series model of Veeco, the growth conditions of the three-dimensional structure layer are a rotation speed of 1100 revolutions per minute, a temperature of 1050 °C, and a pressure of 500 Torr; the growth conditions of the two-dimensional structure layer are a rotation speed of 1100 revolutions per minute, a temperature of 1080 °C, and a pressure of 60 Torr.

[0091] First, place the sapphire substrate into the reaction chamber, control the flow ratio of N2:H2:NH3 introduced into the reaction chamber to be 0:120:0 liters per minute, the pressure of the reaction chamber to be 200 Torr, raise the temperature to 1080 °C, and stabilize for 300 seconds to perform high-temperature purification of the substrate.

[0092] Then, lower the temperature to 540 °C, control the flow ratio of N2:H2:NH3 introduced into the reaction chamber to be 75:150:56 liters per minute, control the pressure of the reaction chamber at 500 Torr, and grow a low-temperature gallium nitride buffer layer with a thickness of 35 nm.

[0093] After that, raise the temperature to 1050 °C, control the flow ratio of N2:H2:NH3 introduced into the reaction chamber to be 75:150:56 liters per minute, control the pressure of the reaction chamber at 550 Torr, and control the carrier disk rotation speed at 1100 revolutions per minute to grow a three-dimensional structure layer with a thickness of 200 nm.

[0094] After that, raise the temperature to 1080 °C, control the flow ratio of N2:H2:NH3 introduced into the reaction chamber to be 64:120:50 liters per minute, control the pressure of the reaction chamber at 60 Torr, and control the carrier disk rotation speed at 1100 revolutions per minute to grow a two-dimensional structure layer with a thickness of 60 nm.

[0095] After that, repeat the above steps to grow the three-dimensional structure layer and the two-dimensional structure layer six times each, and control the total thickness of the three-dimensional structure layer and the two-dimensional structure layer at 1560 nm.

[0096] After that, keep the temperature at 1050 °C, control the flow ratio of N2:H2:NH3 introduced into the reaction chamber to be 64:120:50 liters per minute, control the pressure of the reaction chamber at 200 Torr, and grow an N-type gallium nitride N-GaN layer with a thickness of 1000 nm.

[0097] Thereafter, the temperature is controlled at 750 - 880 °C, the flow rate ratio of N2:H2:NH3 is controlled at 72:0:40 L / min, the pressure in the reaction chamber is controlled at 200 Torr, the quantum well is grown at 760 °C, and the quantum barrier is grown at 860 °C, with a total of 13 pairs of quantum well light-emitting layers.

[0098] Thereafter, the temperature is raised to 960 °C, the flow rate ratio of N2:H2:NH3 is controlled at 64:120:50 L / min, the pressure in the reaction chamber is controlled at 200 Torr, and the P-type gallium nitride P-GaN layer with a thickness of 200 nm is grown.

[0099] Finally, the epitaxial structure layer of this embodiment is tested with an X-ray diffractometer against the epitaxial structure layer of the above-mentioned embodiment A. It can be known from the test that for the epitaxial structure layer of this embodiment, the crystal plane indices of 002 and 102 are reduced from (220, 236) to (210, 230), that is, the dislocation density of the crystal is reduced. By measuring the warp, the warp of the epitaxial structure layer is reduced from 80 to 50. That is, by effectively optimizing the pressure of the three-dimensional structure layer and the two-dimensional structure layer, the warp of the epitaxial structure layer is reduced and the uniformity of the epitaxial structure layer is improved.

[0100] Example D:

[0101] Using the Aixtron CRIUS series model, the growth conditions for the three-dimensional structure layer are a rotation speed of 50 rpm, a temperature of 1000 °C, and a pressure of 300 Torr; the growth conditions for the two-dimensional structure layer are a rotation speed of 80 rpm, a temperature of 1080 °C, and a pressure of 50 Torr.

[0102] First, the sapphire substrate is placed in the reaction chamber, the flow rate ratio of N2:H2:NH3 is controlled at 0:10:0 L / min, the pressure in the reaction chamber is 200 Torr, the temperature is raised to 1100 °C and stabilized for 200 seconds to perform high-temperature purification of the substrate.

[0103] Then, the temperature is lowered to 540 °C, the flow rate ratio of N2:H2:NH3 is controlled at 12:9:15 L / min, the pressure in the reaction chamber is controlled at 520 Torr, and a low-temperature gallium nitride buffer layer with a thickness of 35 nm is grown.

[0104] Thereafter, the temperature is raised to 1000 °C, the flow rate ratio of N2:H2:NH3 is controlled at 15:6:27 L / min, the pressure in the reaction chamber is controlled at 300 Torr, and the carrier disk rotation speed is controlled at 50 rpm to grow a three-dimensional structure layer with a thickness of 500 nm.

[0105] Thereafter, the temperature is raised to 1080 °C, the flow rate ratio of N2:H2:NH3 is controlled at 15:6:27 L / min, the pressure in the reaction chamber is controlled at 50 Torr, and the carrier disk rotation speed is controlled at 80 rpm to grow a two-dimensional structure layer with a thickness of 100 nm.

[0106] Thereafter, repeat the above steps to grow the three-dimensional structure layer and the two-dimensional structure layer five times each, and control the total thickness of the three-dimensional structure layer and the two-dimensional structure layer to be 3000 nm.

[0107] Thereafter, keep the temperature at 1050 °C, control the flow rate ratio of N2:H2:NH3 introduced to be 15:10:27 L / min, control the pressure in the reaction chamber to be 130 Torr, and grow an N-type gallium nitride N-GaN layer with a thickness of 1000 nm.

[0108] Thereafter, control the temperature at 750 - 880 °C, control the flow rate ratio of N2:H2:NH3 introduced to be 9:0:15 L / min, control the pressure in the reaction chamber to be 130 Torr, grow quantum wells at 770 °C, and grow quantum barriers at 870 °C, with a total of 13 pairs of quantum well light-emitting layers.

[0109] Thereafter, raise the temperature to 960 °C, control the flow rate ratio of N2:H2:NH3 introduced to be 15:6:27 L / min, control the pressure in the reaction chamber to be 130 Torr, and grow a P-type gallium nitride P-GaN layer with a thickness of 200 nm.

[0110] Finally, use an X-ray diffractometer to test the epitaxial structure layer of this embodiment and the epitaxial structure layer using conventional technology. It can be known from the test that for the epitaxial structure layer of this embodiment, the crystal plane indices of 002 and 102 are reduced from (280, 305) to (230, 262), that is, the dislocation density of the crystal is effectively reduced. By measuring the warp degree, the warp degree of the epitaxial structure layer is reduced from 120 to 70. Process the epitaxial structure layer into a chip, and it can be obtained through testing that the performance of various optoelectronic parameters has been significantly improved.

[0111] Figure 2 It is a schematic diagram of the structure of a light-emitting diode provided by an embodiment of the present application; Figure 3 It is a schematic diagram of the structure of the three-dimensional structure layer and the two-dimensional structure layer provided by an embodiment of the present application.

[0112] Please refer to Figure 2 and Figure 3 , this embodiment also provides a light-emitting diode, which is manufactured by using the manufacturing method of the light-emitting diode in the above embodiment.

[0113] Specifically, the light-emitting diode includes a substrate 100, and a buffer layer 200, a three-dimensional structure layer 300, and a two-dimensional structure layer 400 are provided on the substrate. Among them, both the three-dimensional structure layer 300 and the two-dimensional structure layer 400 can be provided with multiple layers, and the multiple three-dimensional structure layers 300 and the multiple two-dimensional structure layers 400 are alternately arranged. An N-type doped layer, a quantum well light-emitting layer, and a P-type doped layer are sequentially provided on the topmost two-dimensional structure layer 400.

[0114] The light-emitting diode of this embodiment is manufactured by using the manufacturing method of the light-emitting diode in the above embodiment. Therefore, it is beneficial to reduce the warpage of the epitaxial structure layer and improve the uniformity of the wavelengths of the light-emitting diodes.

[0115] In the description of the present application, it should be understood that the orientation or positional relationship indicated by terms such as "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present application.

[0116] In the present application, unless otherwise clearly specified and defined, terms such as "installed", "connected", "connected to", "fixed" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can be directly connected, or indirectly connected through an intermediate medium, and it can be the communication inside two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0117] It should be noted that in the description of the present application, the terms "first" and "second" are only used for conveniently describing different components, and cannot be understood as indicating or implying a sequential relationship, relative importance, or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features.

[0118] In the present application, the various embodiments or implementation manners are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the various embodiments can be referred to each other.

[0119] In the description of the present application, the description referring to terms such as "one implementation manner", "some implementation manners", "illustrative implementation manners", "examples", "specific examples", or "some examples", etc. means that the specific features, structures, materials, or characteristics described in connection with the implementation manner or example are included in at least one implementation manner or example of the present application. In the present application, the schematic expressions of the above terms do not necessarily refer to the same implementation manner or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more implementation manners or examples.

[0120] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for manufacturing a light-emitting diode, characterized in that, Including: Providing a substrate; Growing a buffer layer on the substrate; Growing at least one three-dimensional structure layer and at least one two-dimensional structure layer alternately on the buffer layer; Growing an N-type doped layer on the topmost two-dimensional structure layer; Growing a quantum well light-emitting layer on the N-type doped layer; Growing a P-type doped layer on the quantum well light-emitting layer; Wherein, the three-dimensional structure layer and the two-dimensional structure layer can be grown under a first growth condition or a second growth condition; The first growth condition for the three-dimensional structure layer is: rotation speed 500 - 1300 revolutions per minute, temperature 1000 - 1200 °C, pressure 300 - 600 Torr; the first growth condition for the two-dimensional structure layer is: rotation speed 500 - 1300 revolutions per minute, temperature 1000 - 1200 °C, pressure 10 - 300 Torr; The second growth condition for the three-dimensional structure layer is: rotation speed 40 - 100 revolutions per minute, temperature 1000 - 1200 °C, pressure 100 - 500 Torr; the second growth condition for the two-dimensional structure layer is: rotation speed 40 - 100 revolutions per minute, temperature 1000 - 1200 °C, pressure 10 - 100 Torr.

2. The method for manufacturing a light-emitting diode according to claim 1, characterized in that, The first growth condition for the three-dimensional structure layer is: rotation speed 1200 revolutions per minute, pressure 500 Torr; the first growth condition for the two-dimensional structure layer is: rotation speed 1200 revolutions per minute, pressure 100 Torr; The second growth condition for the three-dimensional structure layer is: rotation speed 50 revolutions per minute, pressure 300 Torr; the second growth condition for the two-dimensional structure layer is: rotation speed 50 revolutions per minute, pressure 50 Torr.

3. The method for manufacturing a light-emitting diode according to claim 1, characterized in that, The first growth condition for the three-dimensional structure layer further includes: the flow rate ratio of N2:H2:NH3 introduced is 75:150:56; the first growth condition for the two-dimensional structure layer further includes: the flow rate ratio of N2:H2:NH3 introduced is 64:120:50; The second growth condition for the three-dimensional structure layer further includes: the flow rate ratio of N2:H2:NH3 introduced is 15:6:27; the second growth condition for the two-dimensional structure layer further includes: the flow rate ratio of N2:H2:NH3 introduced is 15:6:

27.

4. The method for manufacturing a light-emitting diode according to claim 1, characterized in that, The thickness of each three-dimensional structure layer is 10 - 2000 nm; the thickness of each two-dimensional structure layer is 10 - 2000 nm.

5. The method for manufacturing a light-emitting diode according to claim 4, characterized in that, The thickness of each three-dimensional structure layer is 120 - 1500 nm; the thickness of each two-dimensional structure layer is 50 - 1000 nm.

6. The method for manufacturing a light-emitting diode according to claim 5, characterized in that, There are 2 - 15 layers of the three-dimensional structure layer; there are 2 - 15 layers of the two-dimensional structure layer.

7. The method for manufacturing a light-emitting diode according to claim 1, characterized in that, Both the three-dimensional structure layer and the two-dimensional structure layer are gallium nitride layers.

8. The method for manufacturing a light-emitting diode according to claim 1, characterized in that, The substrate includes a sapphire substrate, a silicon substrate or a silicon carbide substrate.

9. The method for manufacturing a light-emitting diode according to claim 1, characterized in that, The buffer layer, the three-dimensional structure layer, the two-dimensional structure layer, the N-type doped layer, the quantum well light-emitting layer and the P-type doped layer are all gallium nitride layers.

10. A light-emitting diode, characterized in that, Manufactured by using the light-emitting diode manufacturing method as described in any one of claims 1 - 9.

Images