A bridge high voltage drive circuit
By introducing components such as oscillators and inverters into the bridge high-voltage drive circuit, the bootstrap capacitor is eliminated, enabling precise control of high-side and low-side power devices. This solves the low-frequency operation problem caused by the bootstrap capacitor, simplifies the peripheral circuit structure, and reduces power consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- STATE SILICON INTEGRATED CIRCUIT TECH (WUXI) CO LTD
- Filing Date
- 2022-10-26
- Publication Date
- 2026-06-09
AI Technical Summary
In traditional bridge-type high-voltage driver chip circuits, the presence of bootstrap capacitors prevents the circuit from operating under low-frequency input conditions, and they also occupy a large area and are costly in integrated circuits.
By employing an oscillator, inverter, capacitor, and high-side turn-on/turn-off circuit, combined with a clamping circuit and a low-side drive circuit, precise control of high-side and low-side power devices is achieved. The bootstrap capacitor and bootstrap diode are eliminated, and voltage regulation is performed by the oscillator when the high-side input signal changes.
It achieves precise control of high-voltage bridge high- and low-side power devices, simplifies the peripheral circuit structure, has low standby power consumption, and is suitable for integrated circuits.
Smart Images
Figure CN115528917B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to high-voltage drive circuits used in switching power supplies, motor drives, LED drivers, DC-DC converters, etc., and specifically to a bridge-type high-voltage drive circuit, belonging to the field of integrated circuit technology. Background Technology
[0002] High-voltage driver chips, especially bridge-type high-voltage driver chips, have a wide range of applications, such as power supplies, motor drivers, LED drivers, and DC-DC converters.
[0003] A traditional bridge-type high-voltage driver chip circuit, such as Figure 1 As shown in the dashed box, the level shifting circuit converts the low-voltage signal HIN input on the high side into a high-voltage signal, which is used to control the on and off of the high-side power transistor MP. The circuit structure is relatively simple, but its disadvantages are also obvious. In integrated circuits, the size of PMOS transistors is relatively large, generally more than twice the size of NMOS transistors of the same type, so the cost of this circuit is high.
[0004] Another type of bridge-type high-voltage driver chip circuit, such as Figure 2 The dashed box shows a level shifter circuit, a buffer, a bootstrap capacitor CB, a bootstrap diode DB, and a high-side power transistor M1. The bootstrap capacitor CB maintains a stable high-side supply voltage in the level shifter circuit. The bootstrap diode DB charges the bootstrap capacitor CB when the output OUT goes low. This traditional bootstrap charging structure only charges when the high-side power transistor M1 is off and OUT goes low. Therefore, the circuit cannot operate under low-frequency input conditions because high-side leakage current will cause the voltage across capacitor CB to drop until it reaches zero. To address this situation, as follows... Figure 3 As shown, patent CN103683864B makes an improvement, namely, that during the period when the high-side power transistor is turned on, a charge pump can be used to continuously charge the bootstrap capacitor CB, maintaining the voltage across the capacitor CB unchanged, so that the circuit can operate at low frequency.
[0005] However, regardless of the traditional bootstrap circuit structure or the existing patented improved circuit structure, the presence of the bootstrap capacitor CB is required. The stability of the voltage on capacitor CB is related to whether the high-side power transistor can work stably and reliably. When the voltage on capacitor CB decreases, it will cause the gate voltage of the high-side power transistor to drop and the impedance to increase. In order to improve the stability of the voltage on capacitor CB, capacitor CB needs to be made very large, generally at least in the nF level. However, such a large capacitor requires a large area in integrated circuits, so it is difficult to integrate and discrete capacitors are required. Summary of the Invention
[0006] To overcome the shortcomings of the existing technology, the present invention provides a bridge high-voltage drive circuit, which adopts the following technical solution: a bridge high-voltage drive circuit is integrated into a chip, the chip has seven ports, namely, high-side input port HIN, low-side input port LIN, high-side output port HO, low-side output port LO, high-side floating ground VS, chip power supply port VDD and ground GND;
[0007] Its features include: a high-voltage drive circuit comprising an oscillator, an inverter INV0, capacitors C1 and C2, a high-side turn-on circuit, a high-side turn-off circuit, and a low-side drive circuit; the high-side input port HIN of the chip is connected to the input terminal of the oscillator and the input terminal of the high-side turn-off circuit; the output of the oscillator is connected to the input terminal of the inverter INV0 and one end of capacitor C2; the output of the inverter INV0 is connected to one end of capacitor C1; the other end of capacitor C1 is connected to the inverting input terminal of the high-side turn-on circuit; and the other end of capacitor C2 is connected to the non-inverting input terminal of the high-side turn-on circuit. One output of the turn-on circuit is connected to the gate turn-off port of the high-side turn-off circuit and the high-side output port HO of the chip, and is connected to the gate of the high-side switching transistor M1. The other output of the high-side turn-on circuit is connected to the floating potential VS turn-off port of the high-side turn-off circuit and the high-side floating ground VS of the chip. The low-side input port LIN of the chip is connected to the input of the low-side drive circuit. The output of the low-side drive circuit is connected to the low-side output port LO of the chip and is connected to the gate of the low-side switching transistor M2. The oscillator, inverter INV0 and low-side drive circuit are all powered by the chip power supply VDD.
[0008] The high-side turn-on circuit includes diodes D1, D2, D3, and D4, as well as a clamping circuit. The anode of diode D1 is connected to the cathode of diode D3 and serves as the inverting input terminal of the high-side turn-on circuit, connected to capacitor C1. The anode of diode D2 is connected to the cathode of diode D4 and serves as the non-inverting input terminal of the high-side turn-on circuit, connected to capacitor C2. The clamping circuit is connected between the connection point of the cathodes of diodes D1 and D2 and the connection point of the anodes of diodes D3 and D4. The connection point of the cathodes of diodes D1 and D2 is also connected to the high-side output port HO of the chip, and the connection point of the anodes of diodes D3 and D4 is also connected to the high-side floating potential VS of the chip.
[0009] The high-side turn-off circuit includes a PMOS transistor P2, an NMOS transistor N2, a resistor R0, and an inverter INV1. The source of the PMOS transistor P2 is connected to one end of the resistor R0 and to the output terminal of the high-side turn-on circuit connected to the high-side output port HO of the chip. The other end of the resistor R0 is connected to the gate of the PMOS transistor P2 and the drain of the NMOS transistor N2. The drain of the PMOS transistor P2 is connected to the output terminal of the high-side turn-on circuit connected to the high-side floating potential VS of the chip. The source of the NMOS transistor N2 is grounded, and the gate of the NMOS transistor N2 is connected to the output of the inverter INV1. The input of the inverter INV1 is connected to the high-side input port HIN of the chip.
[0010] Furthermore, in the high-side turn-on circuit, PMOS transistors P0 and P1 can replace diodes D1 and D2 respectively, and NMOS transistors N0 and N1 can replace diodes D3 and D4 respectively. The drain of PMOS transistor P0 is connected to the gate of PMOS transistor P1, the gate of NMOS transistor N1, and the drain of NMOS transistor N0, and serves as the inverting input terminal of the high-side turn-on circuit, connected to capacitor C1. The gate of PMOS transistor P0 is connected to the drain of PMOS transistor P1 and the gate of NMOS transistor N0. The source and drain of PMOS transistor P0 and NMOS transistor N1 are connected to capacitor C2 as the non-inverting input of the high-side turn-on circuit. A clamping circuit is connected between the connection point of the sources of PMOS transistors P0 and P1 and the connection point of the sources of NMOS transistors N0 and N1. The connection point of the sources of PMOS transistors P0 and P1 is also connected to the high-side output port HO of the chip, and the connection point of the sources of NMOS transistors N0 and N1 is also connected to the high-side floating potential VS of the chip. The substrates of PMOS transistors P0, P1, NMOS transistors N0, and N1 are all connected to their sources.
[0011] Furthermore, the values of capacitors C1 and C2 are determined by the driving capability of the high-side output port HO, and C1 = C2.
[0012] Furthermore, the clamping circuit in the high-side turn-on circuit is a Zener diode. The cathode of the Zener diode is connected to the output terminal of the high-side turn-on circuit, which is connected to the high-side output port HO of the chip, and the anode of the Zener diode is connected to the output terminal of the high-side turn-on circuit, which is connected to the high-side floating potential VS of the chip.
[0013] The oscillator includes inverters INV2, INV3, and INV4, a NAND gate NAND1, a resistor R1, a capacitor C3, and a Schmitt trigger SCH1. One input of the NAND gate NAND1 serves as the input of the oscillator and is connected to the high-side input port HIN of the chip. The other input of the NAND gate NAND1 is connected to the output of inverter INV2. The output of the NAND gate NAND1 is connected to one end of the resistor R1. The other end of the resistor R1 is connected to one end of the capacitor C3 and the input of the Schmitt trigger SCH1. The other end of the capacitor C3 is grounded. The output of the Schmitt trigger SCH1 is connected to the input of inverter INV3. The output of inverter INV3 is connected to the input of inverter INV4. The output of inverter INV4 serves as the output of the oscillator, and the output of inverter INV4 is also fed back to the input of inverter INV2.
[0014] The oscillator described above is controlled by the high-side input port HIN of the chip. When the high-side input port signal HIN of the NAND gate NAND1 is low, the output of the NAND gate NAND1 is high, and the oscillator is in the off state. When the high-side input port signal HIN of the NAND gate NAND1 is high, the oscillator is in the working state. The frequency of the oscillator is determined by the resistor R1, the capacitor C3, and the threshold of the Schmitt trigger SCH1 used for shaping. The oscillator output is a rectangular wave signal with arbitrary frequency and arbitrary duty cycle.
[0015] Advantages and significant effects of the present invention:
[0016] 1. This invention can drive two N-type power devices on the high and low sides. When the high-side input signal HIN is high, the oscillator is activated, supplying power to the gate HO of the high-side power device. The gate voltage eventually reaches or approaches VS+VDD, fully turning on the high-side power device. When the high-side input signal HIN is low, the gate-source potential of the high-side power device is pulled low, completely turning it off. The low-side power device is controlled by the low-side input signal LIN through the low-side drive circuit. The chip and circuit of this invention realize the control of high-voltage bridge high and low-side power devices. The chip has an extremely simplified peripheral circuit structure in the application system, and the circuit has extremely low standby power consumption.
[0017] 2. The chip does not require external bootstrap diodes and bootstrap capacitors, and has a simplified external application circuit structure;
[0018] 3. The chip has extremely low static power consumption when there is no input signal. Attached Figure Description
[0019] Figure 1 This is a schematic diagram of a traditional high-voltage drive circuit;
[0020] Figure 2 This is a schematic diagram of another traditional high-voltage drive circuit;
[0021] Figure 3 A schematic diagram of a prior art circuit structure;
[0022] Figure 4 This is a general block diagram of a bridge-type high-voltage drive circuit according to the present invention;
[0023] Figure 5a for Figure 4 One implementation circuit of the high-side turn-on circuit in the middle;
[0024] Figure 5b for Figure 4 Another implementation circuit of the high-side turn-on circuit in the middle;
[0025] Figure 6 for Figure 4 One implementation circuit of the high-side turn-off circuit in the middle;
[0026] Figure 7 for Figure 4 One implementation circuit of the oscillator in the image;
[0027] Figure 8 This is a specific embodiment of a bridge-type high-voltage drive circuit of the present invention;
[0028] Figure 9 for Figure 8 The working waveform diagram. Detailed Implementation
[0029] The present invention will now be described in further detail with reference to the accompanying drawings.
[0030] like Figure 4The dashed box shows the high-voltage drive circuit of this invention, including an oscillator, an inverter INV0, capacitors C1 and C2, a high-side turn-on circuit, a high-side turn-off circuit, and a low-side drive circuit. The high-side input port HIN of the chip is connected to the input terminal of the oscillator and the input terminal of the high-side turn-off circuit. The output of the oscillator is connected to the input terminal of the inverter INV0 and one end of capacitor C2. The output of the inverter INV0 is connected to one end of capacitor C1. The other end of capacitor C1 is connected to the inverting input terminal of the high-side turn-on circuit, and the other end of capacitor C2 is connected to the non-inverting input terminal of the high-side turn-on circuit. One output of the high-side turn-on circuit is connected to the gate turn-off port of the high-side turn-off circuit and the chip's high-side output port HO, and is connected to the gate of the high-side switching transistor M1. The other output of the high-side turn-on circuit is connected to the floating ground VS turn-off port of the high-side turn-off circuit and the chip's high-side floating ground VS. The chip's low-side input port LIN is connected to the input of the low-side drive circuit. The output of the low-side drive circuit is connected to the chip's low-side output port LO and is connected to the gate of the low-side switching transistor M2. The oscillator, inverter INV0, and low-side drive circuit are all powered by the chip's power supply VDD.
[0031] like Figure 5a The dashed box contains the high-side turn-on circuit, which includes diodes D1, D2, D3, and D4, as well as a clamping circuit. The anode of diode D1 is connected to the cathode of diode D3 and serves as the inverting input of the high-side turn-on circuit, connected to capacitor C1. The anode of diode D2 is connected to the cathode of diode D4 and serves as the non-inverting input of the high-side turn-on circuit, connected to capacitor C2. The clamping circuit is connected between the junction of the cathodes of diodes D1 and D2 and the junction of the anodes of diodes D3 and D4. The junction of the cathodes of diodes D1 and D2 is also connected to the high-side output port HO of the chip, and the junction of the anodes of diodes D3 and D4 is also connected to the high-side floating ground VS of the chip. In the high-side turn-on circuit, the lowest potential of the non-inverting and inverting input terminals is clamped by the VS potential, and the highest potential is clamped by the HO potential. The floating ground port has unidirectional conductivity to the non-inverting and inverting input terminals, meaning that current can only flow from the floating ground port to the non-inverting and inverting input terminals. The non-inverting and inverting input terminals have unidirectional conductivity to the gate output terminal, meaning that current can only flow from the non-inverting and inverting input terminals to the gate output terminal.
[0032] like Figure 6The dashed box encloses the high-side shutdown circuit, which includes a PMOS transistor P2, an NMOS transistor N2, a resistor R0, and an inverter INV1. The source of PMOS transistor P2 is connected to one end of resistor R0 and then to the output terminal of the high-side turn-on circuit, which is connected to the high-side output port HO of the chip. The other end of resistor R0 is connected to the gate of PMOS transistor P2 and the drain of NMOS transistor N2. The drain of PMOS transistor P2 is connected to the output terminal of the high-side turn-on circuit, which is connected to the high-side floating potential VS of the chip. The source of NMOS transistor N2 is grounded, and its gate is connected to the output of inverter INV1. The input of inverter INV1 is connected to the high-side input port HIN of the chip. When the input signal HIN of the high-side shutdown circuit is high, the gate-to-ground VS shutdown port of the high-side shutdown circuit is in a high-impedance state; when the input signal HIN is low, the gate-to-ground VS shutdown port is in a low-impedance state.
[0033] Figure 5b The dashed box shows another implementation of the high-side turn-on circuit, which uses PMOS transistors P0 and P1 to replace... Figure 5a Diodes D1 and D2 are replaced by NMOS transistors N0 and N1, respectively. The drain of PMOS transistor P0 is connected to the gate of PMOS transistor P1, the gate of NMOS transistor N1, and the drain of NMOS transistor N0, and serves as the inverting input of the high-side turn-on circuit, connected to capacitor C1. The gate of PMOS transistor P0 is connected to the drain of PMOS transistor P1, the gate of NMOS transistor N0, and the drain of NMOS transistor N1, and serves as the non-inverting input of the high-side turn-on circuit, connected to capacitor C2. The clamping circuit is connected between the connection point of the source of PMOS transistor P0 and the source of PMOS transistor P1 and the connection point of the source of NMOS transistor N0 and the source of NMOS transistor N1. The connection point of the source of PMOS transistor P0 and the source of PMOS transistor P1 is also connected to the high-side output port HO of the chip. The connection point of the source of NMOS transistor N0 and the source of NMOS transistor N1 is also connected to the high-side floating potential VS of the chip. The substrates of the PMOS transistors P0, PMOS transistor P1, NMOS transistor N0, and NMOS transistor N1 are all connected to the source.
[0034] Figure 7The dashed box shows an implementation circuit for an oscillator, including inverters INV2, INV3, and INV4, a NAND gate NAND1, a resistor R1, a capacitor C3, and a Schmitt trigger SCH1. One input of the NAND gate NAND1 serves as the input of the oscillator and is connected to the high-side input port HIN of the chip. The other input of the NAND gate NAND1 is connected to the output of inverter INV2. The output of the NAND gate NAND1 is connected to one end of resistor R1. The other end of resistor R1 is connected to one end of capacitor C3 and the input of Schmitt trigger SCH1. The other end of capacitor C3 is grounded. The output of Schmitt trigger SCH1 is connected to the input of inverter INV3. The output of inverter INV3 is connected to the input of inverter INV4. The output of inverter INV4 serves as the output of the oscillator, and the output of inverter INV4 is also fed back to the input of inverter INV2.
[0035] Figure 8 yes Figure 4 The specific implementation circuit of the block diagram, in which the oscillator can be adopted Figure 7 The circuit structure is such that when one input port HIN of NAND1 is low, the output of NAND1 is high and the oscillator is in the off state. When HIN is high, the oscillator is in the working state. The frequency of the oscillator is mainly determined by resistor R1, capacitor C3 and the threshold of SCH1. SCH1 plays a signal shaping role. The oscillator output B is a square wave signal with a certain frequency.
[0036] Figure 8 The high-side turn-on circuit in the middle adopts Figure 5b The Zener diode Z0 forms the clamping circuit. The high-side turn-off circuit uses... Figure 6 The low-side drive circuit is composed of inverters INV5, INV6, INV7 and INV8 connected in series.
[0037] Figure 8 The circuit's operating waveform is as follows Figure 9As shown, when the high-side input signal HIN is low, the oscillator is off, N2 and P2 are on, the HO-VS voltage is pulled to 0V, and transistor M1 is off. When the high-side input signal HIN is high, the oscillator starts working, N2 and P2 are off. When the voltage at the connection point V1 between C1 and the high-side turn-on circuit is high, the voltage at the connection point V2 between C2 and the high-side turn-on circuit is low. P1 and N2 are on, P2 and N1 are off, and the potential at point V2 remains the same as the VS potential. The potential at point V1 remains the same as the HO potential. When the voltage at the connection point V2 between C2 and the high-side turn-on circuit is high, the voltage at the connection point V1 between C1 and the high-side turn-on circuit is low, P2 and N1 are on, P1 and N2 are off, and the potential at point V1 remains the same as the VS potential. The potential at point V2 remains the same as the HO potential. Finally, the HO potential rises, the HO-VS voltage is approximately equal to VDD, and transistor M1 is fully turned on.
[0038] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.
Claims
1. A bridge-type high-voltage drive circuit, integrated into a chip, the chip having seven ports: high-side input port HIN, low-side input port LIN, high-side output port HO, low-side output port LO, high-side floating ground VS, chip power supply port VDD, and ground GND; Its features are: The high-voltage drive circuit includes an oscillator, an inverter INV0, capacitors C1 and C2, a high-side turn-on circuit, a high-side turn-off circuit, and a low-side drive circuit. The chip's high-side input port HIN is connected to the input of the oscillator and the input of the high-side turn-off circuit. The oscillator's output is connected to the input of the inverter INV0 and one end of capacitor C2. The output of the inverter INV0 is connected to one end of capacitor C1. The other end of capacitor C1 is connected to the inverting input of the high-side turn-on circuit, and the other end of capacitor C2 is connected to the non-inverting input of the high-side turn-on circuit. The high-side turn-on... One output of the circuit is connected to the gate turn-off port of the high-side turn-off circuit and the high-side output port HO of the chip, and is connected to the gate of the high-side switching transistor M1. The other output of the high-side turn-on circuit is connected to the floating ground VS turn-off port of the high-side turn-off circuit and the high-side floating ground VS of the chip. The low-side input port LIN of the chip is connected to the input of the low-side drive circuit. The output of the low-side drive circuit is connected to the low-side output port LO of the chip and is connected to the gate of the low-side switching transistor M2. The oscillator, inverter INV0 and low-side drive circuit are all powered by the chip power supply VDD. The high-side turn-on circuit includes diodes D1, D2, D3, and D4, as well as a clamping circuit. The anode of diode D1 is connected to the cathode of diode D3 and serves as the inverting input terminal of the high-side turn-on circuit, connected to capacitor C1. The anode of diode D2 is connected to the cathode of diode D4 and serves as the non-inverting input terminal of the high-side turn-on circuit, connected to capacitor C2. The clamping circuit is connected between the connection point of the cathodes of diodes D1 and D2 and the connection point of the anodes of diodes D3 and D4. The connection point of the cathodes of diodes D1 and D2 is also connected to the high-side output port HO of the chip, and the connection point of the anodes of diodes D3 and D4 is also connected to the high-side floating ground VS of the chip. The high-side turn-off circuit includes a PMOS transistor P2, an NMOS transistor N2, a resistor R0, and an inverter INV1. The source of the PMOS transistor P2 is connected to one end of the resistor R0 and is connected to the output terminal of the high-side turn-on circuit, which is connected to the high-side output port HO of the chip. The other end of the resistor R0 is connected to the gate of the PMOS transistor P2 and the drain of the NMOS transistor N2. The drain of the PMOS transistor P2 is connected to the output terminal of the high-side turn-on circuit, which is connected to the high-side floating ground VS of the chip. The source of the NMOS transistor N2 is grounded, and the gate of the NMOS transistor N2 is connected to the output of the inverter INV1. The input of the inverter INV1 is connected to the high-side input port HIN of the chip.
2. The bridge-type high-voltage drive circuit according to claim 1, characterized in that: In the high-side turn-on circuit, PMOS transistors P0 and P1 replace diodes D1 and D2 respectively, and NMOS transistors N0 and N1 replace diodes D3 and D4 respectively. The drain of PMOS transistor P0 is connected to the gate of PMOS transistor P1, the gate of NMOS transistor N1, and the drain of NMOS transistor N0, and serves as the inverting input of the high-side turn-on circuit, connected to capacitor C1. The gate of PMOS transistor P0 is connected to the drain of PMOS transistor P1, the gate of NMOS transistor N0, and... The drain of NMOS transistor N1 is connected to capacitor C2 as the non-inverting input of the high-side turn-on circuit. The clamping circuit is connected between the connection point of the source of PMOS transistor P0 and the source of PMOS transistor P1 and the connection point of the source of NMOS transistor N0 and the source of NMOS transistor N1. The connection point of the source of PMOS transistor P0 and the source of PMOS transistor P1 is also connected to the high-side output port HO of the chip. The connection point of the source of NMOS transistor N0 and the source of NMOS transistor N1 is also connected to the high-side floating ground VS of the chip.
3. The bridge-type high-voltage drive circuit according to claim 2, characterized in that: The substrates of the PMOS transistors P0, PMOS transistor P1, NMOS transistor N0, and NMOS transistor N1 are all connected to the source.
4. The bridge-type high-voltage drive circuit according to claim 1, 2, or 3, characterized in that: The values of capacitors C1 and C2 are determined by the driving capability of the high-side output port HO, and C1 = C2.
5. The bridge-type high-voltage drive circuit according to claim 1, 2, or 3, characterized in that: The clamping circuit in the high-side turn-on circuit is a Zener diode. The cathode of the Zener diode is connected to the output terminal of the high-side turn-on circuit, which is connected to the high-side output port HO of the chip, and the anode of the Zener diode is connected to the output terminal of the high-side turn-on circuit, which is connected to the high-side floating ground VS of the chip.
6. The bridge-type high-voltage drive circuit according to claim 1, 2, or 3, characterized in that: The oscillator includes inverters INV2, INV3, and INV4, a NAND gate NAND1, a resistor R1, a capacitor C3, and a Schmitt trigger SCH1. One input of the NAND gate NAND1 is connected to the high-side input port HIN of the chip, and the other input of the NAND gate NAND1 is connected to the output of inverter INV2. The output of the NAND gate NAND1 is connected to one end of resistor R1. The other end of resistor R1 is connected to one end of capacitor C3 and the input of Schmitt trigger SCH1. The other end of capacitor C3 is grounded. The output of Schmitt trigger SCH1 is connected to the input of inverter INV3, and the output of inverter INV3 is connected to the input of inverter INV4. The output of inverter INV4 serves as the output of the oscillator, and its output is also fed back to the input of inverter INV2. The oscillator is controlled by the high-side input port HIN of the chip. When the high-side input port signal HIN of the NAND gate NAND1 is low, the output of NAND gate NAND1 is high, and the oscillator is off. When the high-side input port signal HIN of the NAND gate NAND1 is high, the oscillator is in operation. The frequency of the oscillator is determined by resistor R1, capacitor C3, and the threshold of Schmitt trigger SCH1 used for shaping. The oscillator output is a rectangular wave signal with arbitrary frequency and duty cycle.