Converter comprising an inverting full bridge and method of controlling the same

Abstract

To balance the thermal stress of the switches in the two arms of the inverter bridge, a modulation period T is used. mod A booster / deboss counter with a period T twice that of the input voltage generates the drive signal. The booster / deboss counter has a first comparison value of D / 4 and a second comparison value of (2+D) / 4, where D is the duty cycle, and the second half-bridge is a phase-shifted second half-bridge with a period T. In another embodiment, the second half-bridge has no phase shift but has different comparison values, where the first comparison value of the second half-bridge is (1-D / 4) and the second comparison value is (1-(2+D) / 4). The generation of the drive signal includes: each time the booster / deboss counter crosses one of the comparison values, a switch is turned on or off, thus extending the modulation period T. mod In the inverter full bridge, the switches of each arm can be turned on and off under the same current, thereby balancing the switching losses and thus balancing the thermal stress of each arm.

Description

Technical Field

[0001] This invention relates to a method for controlling a converter, the converter including an inverter full-bridge having a first input terminal, a second input terminal, a first half-bridge, and a second half-bridge, the first and second half-bridges being connected across the first and second input terminals; wherein an input voltage (Vin) with a period T is provided between the first and second input terminals, and wherein each half-bridge includes a first switch and a second switch connected in series between the first and second input terminals; wherein a drive signal for the switches is generated using pulse width modulation with a duty cycle of D. The invention also relates to a converter including an inverter full-bridge having a first input terminal, a second input terminal, a first half-bridge, and a second half-bridge, the first and second half-bridges being connected across the first and second input terminals; wherein each half-bridge includes a first switch and a second switch connected in series between the first and second input terminals, and wherein the inverter full-bridge further includes a drive signal generator for generating drive signals for the switches using pulse width modulation with a duty cycle of D. Background Technology

[0002] Phase-shift modulated converters are widely used in a variety of applications. For example, phase-shift modulation is used as the modulation mode in phase-shift full-bridge converters, and also in LLC converters to reduce gain under light loads and to balance interleaved LLC converters under all load conditions in a single-stage architecture. In phase-shift modulation, both half-bridges (arms) of the inverter operate at approximately 50% duty cycles, with phase shifting modulated on individual arms to adjust the voltage transfer ratio.

[0003] While this is an easy-to-implement modulation method, it has drawbacks: the leading halfbridge always experiences greater switching losses than the lagging halfbridge. Because the current decreases in the freewheeling interval, the leading halfbridge turns off at a higher current, while the lagging halfbridge turns off at a significantly lower current. Furthermore, this lower turn-off current of the lagging halfbridge may prevent the leading halfbridge from performing zero-voltage switching (ZVS) due to insufficient energy in the series inductor. This can also increase switching losses. The greater switching losses lead to a thermal imbalance between the leading and lagging halfbridge switches. The leading halfbridge switch always experiences a higher temperature.

[0004] Uneven stress on these switches can cause some switches to fail prematurely, leading to premature failure of the entire inverter while most other components are still in good condition and can continue to operate.

[0005] To balance switching losses, some methods involve swapping the leading and lagging bridge arms. However, this requires external control and reprogramming of the PWM register, thus forming a non-closed control method. Summary of the Invention

[0006] The object of this invention is to create a converter and a method for controlling the converter in the aforementioned technical field, which can reduce or even eliminate thermal imbalance of the switch during operation, thereby using a closed modulation method.

[0007] The solution for the control method of the present invention can be found in the following embodiments. According to the present invention, the drive signals for the switches (S1, S2, S3, S4) are generated using pulse width modulation technology with a duty cycle of D, and the up-down counters used have a period T. mod (twice the period T), the first comparison value and the second comparison value, where:

[0008] The first switch (S1) of the first half-bridge is turned on when the up-down counter counts to the first comparison value.

[0009] The first switch (S1) of the first half-bridge is turned off when the up-down counter counts to the second comparison value.

[0010] The first switch (S1) of the first half-bridge is turned on when the up-down counter counts down to the second comparison value.

[0011] The first switch (S1) of the first half-bridge is turned off when the up-down counter counts down to the first comparison value.

[0012] The second switch (S3) of the first half-bridge is switched alternately with the first switch (S1) of the first half-bridge.

[0013] The first comparison value of the first half-bridge is D / 4, and the second comparison value of the first half-bridge is (2+D) / 4.

[0014] Therefore, this invention proposes a closed-loop modulation method for two original cycles of a continuous input voltage. An up-and-down counter is used to generate the drive signal. The counter has two comparison values, D / 4 and (2+D) / 4. In the generated modulation, the enable event transitions from one comparison event to the next.

[0015] Thus, this invention enables the creation of an easily implemented modulation method that ensures equal switching activity and switching losses across all switches in the inverter full-bridge. By using a modulation sequence of two cycles in length, thermal imbalance can be significantly reduced, subjecting all switches to the same stress and resulting in similar or identical switch temperatures. Experimental measurements validate this concept and demonstrate that this modulation significantly reduces temperature variations.

[0016] The drive signal generator is implemented using, for example, a microprocessor. A digital signal processor (DSP) is preferred because it is better suited for this type of task.

[0017] In a preferred embodiment of the present invention, the switching methods of the first and second switches of the second half-bridge are the same as those of the first and second switches of the first half-bridge, except that the comparison values ​​are different. The first comparison value of the second half-bridge is (1-D / 4), and the second comparison value of the second half-bridge is (1-(2+D) / 4).

[0018] In this case, the up and down counters of the two half-bridges are the same, which means that there is no phase shift between the two half-bridges, only different comparison values.

[0019] However, besides using different comparison values ​​for the two half-bridges, they can also use the same comparison value. But in this case, a phase shift must be applied between the up / down counters of the first and second half-bridges. For example, the comparison value of the first half-bridge can also be used as the comparison value of the second half-bridge, but with a phase shift corresponding to the period T applied.

[0020] In a preferred embodiment of the present invention, during the modulator period T mod In the first half, the up / down counter gradually increases from its minimum value to its maximum value, and then during the modulator period T... mod In the latter half, the up / down counter gradually decreases from its maximum value to its minimum value. The minimum value is preferably zero, and the maximum value is preferably 1. However, the minimum and maximum values ​​can also be chosen differently, which would require appropriate adjustments to the comparison value. For example, if the minimum value remains zero, but the maximum value is chosen to be 2, then the comparison value must be doubled to obtain the same result.

[0021] This makes the output waveform of the up / down counter triangular, passing through the first comparison value and the second comparison value once each time it rises and falls.

[0022] The solution for the converter in this invention can be found in the following embodiments. According to this invention, the drive signal generator includes an up-and-down counter having a first comparison value, a second comparison value, and a period T. mod Period T modThe period T is twice that of the input voltage (Vin) provided between the first and second input terminals, wherein the drive signal generator is adapted to generate a drive signal for the switch according to the method of the invention as described above (including a preferred embodiment of the method).

[0023] Therefore, this invention proposes a converter with a drive signal generator capable of implementing a closed-loop modulation method that lasts for two original cycles of the input voltage. An up / down counter is used to generate the drive signal. For the first half-bridge, the counter has two comparison values, D / 4 and (2+D) / 4. And as previously mentioned, the counter preferably has different comparison values ​​for the second half-bridge, i.e., the first comparison value of the second half-bridge is (1-D / 4), and the second comparison value of the second half-bridge is (1-(2+D) / 4). In the resulting modulation, the enable event changes from one comparison event to the next.

[0024] Thus, this invention enables the creation of an easily implemented converter, including an inverter full-bridge, which can be controlled using a modulation method to ensure that all switches in the inverter full-bridge have equal conduction and switching losses. Through such a modulation sequence of two cycles in length, thermal imbalance can be significantly reduced, ensuring that all switches are subjected to the same stress, thereby resulting in identical or similar switch temperatures.

[0025] Inverter full-bridge switches are implemented using, for example, MOSFET switches, such as silicon or silicon carbide MOSFETs. However, other types of MOSFETs, or more generally, other types of transistors, can also be used. The optimal choice for implementing the switch depends on the specific application.

[0026] In another preferred embodiment of the invention, the converter includes a transformer, a converter stage connected between the inverter full bridge and the primary side of the transformer, a rectifier connected to the secondary side of the transformer, and an output stage connected to the rectifier, wherein the output power of the converter is provided at the output of the output stage.

[0027] This invention is preferably applied to converters having these components. However, it can also be applied to converters that do not contain one or more of the aforementioned components. For example, if a converter provides AC output power to another device, it means that the converter does not need to have a rectifier before the output stage.

[0028] However, in most applications where this invention can be applied, the converter includes not only a transformer and a rectifier located on the secondary side of the transformer, but also a conversion stage between the inverter full-bridge and the transformer. This conversion stage effectively defines the type of converter that includes the inverter full-bridge.

[0029] As mentioned above, the lead arm switch also turns off when the current increases. When the lead arm switch turns off, a freewheeling interval begins. During this interval, the transformer current decreases, causing the lagging arm switch to turn off at a significantly reduced current at the end of the freewheeling interval. While this effect is less relevant to other converters (such as phase-shifted full-bridge converters), it poses a problem for LLC converters because the resonant capacitor voltage causes a significant reduction in the resonant current during this time interval, resulting in the lagging arm turning off at a much smaller current.

[0030] By applying the invention to LLC converters in this way, this imbalance can be eliminated or at least significantly reduced. Therefore, the invention is preferably applied to converters in which the conversion stage includes an LLC resonant tank. This means the converter is an LLC converter.

[0031] In another preferred embodiment of the invention, the conversion stage includes a series inductor and a magnetizing inductor, wherein the series inductor is connected in series between the inverter full-bridge and the transformer, and the magnetizing inductor is connected in parallel to the transformer. This configuration yields a phase-shifted full-bridge converter. Although the advantages of the invention are not as pronounced in, for example, LLC converters, the invention eliminates or reduces thermal imbalance of the switches in a phase-shifted full-bridge converter.

[0032] In another preferred embodiment of the invention, the rectifier includes a synchronous rectifier. It can be a half-bridge rectifier or a full-bridge rectifier, wherein the synchronous rectifier switch can be selected according to the requirements of a specific application. Typically, MOSFETs (metal oxide field effect transistors) or BJTs (bipolar junction transistors) are used.

[0033] Preferably, the synchronous rectifier includes a first controllable rectifier switch connected to a first output terminal of the transformer and a second controllable rectifier switch connected to a second output terminal of the transformer, wherein both controllable rectifier switches are connected to the first output terminal of the rectifier, and wherein the secondary winding of the transformer includes a center tap connected to the second output terminal of the rectifier.

[0034] However, synchronous rectifiers can also be implemented as full-bridge rectifiers with controllable switches, thus avoiding a center tap on the transformer secondary. Depending on the specific application, a center-tapped rectifier may be superior to a full-bridge rectifier, and vice versa. This applies not only to synchronous rectifiers but also to diode rectifiers as described below.

[0035] In another preferred embodiment of the invention, the rectifier includes a full-bridge diode rectifier. This rectifier includes four diodes connected in a bridge configuration, with two half-bridges connected in parallel across the transformer output. Each half-bridge includes two diodes connected in series, wherein the common terminal of the two switches of the first half-bridge is connected to the first output terminal of the rectifier, and the common terminal of the two switches of the second half-bridge is connected to the second output terminal of the rectifier.

[0036] However, a diode rectifier can also be implemented as a center-tapped diode rectifier with only two diodes, and the connection of these two diodes is similar to the connection of the two controllable switches in the aforementioned center-tapped synchronous rectifier.

[0037] In addition, it should be mentioned that half-wave rectifiers can also be used, implemented with diodes or controlled switches. However, full-bridge rectifiers are usually preferred due to their higher efficiency.

[0038] In another preferred embodiment of the invention, the output stage includes an output filter having a capacitor connected between the rectifier output terminals. A load is then connected to the capacitor in the output stage.

[0039] In another preferred embodiment of the invention, the switch of the inverter full-bridge comprises a MOSFET, such as a silicon, silicon carbide, or gallium nitride MOSFET. Of course, other types of MOSFETs can also be used, or more generally, other types of transistors. The optimal choice for implementing the switch depends on the specific application.

[0040] It should be noted that the converter may also include additional components, such as a DC-DC conversion stage preceding the inverter full-bridge. Furthermore, the individual components of the aforementioned converter may also include additional components required for specific applications.

[0041] Other advantageous embodiments and feature combinations can be found in the detailed description and various embodiments below. Attached Figure Description

[0042] The accompanying drawings, used to illustrate the embodiments, show:

[0043] Figure 1 A schematic circuit diagram of a phase-shifted full-bridge converter known in the art is shown;

[0044] Figure 2 Part a) of the diagram illustrates the prior art Figure 1 The switching scheme of the phase-shifting full-bridge converter is shown.

[0045] Figure 2 Section b) shows the use of Figure 2 The voltage and current of the inverter full bridge obtained by the switching scheme shown in part a) of the diagram;

[0046] Figure 3 A schematic circuit diagram of an LLC converter according to the present invention is shown;

[0047] Figure 4 A schematic circuit diagram of a phase-shifted inverter full-bridge according to the present invention is shown;

[0048] Figure 5 The switching scheme according to the invention and the voltage and current of the resulting inverter full bridge are shown.

[0049] In the figures, the same parts are given the same reference numerals. Detailed Implementation

[0050] Figure 1 A schematic circuit diagram of a phase-shifted full-bridge converter 1 known in the art is shown. The input voltage Vin is connected between the first input terminal 2 and the second input terminal 3. The phase-shifted full-bridge converter 1 also includes an inverter full-bridge 4, a phase-shifted full-bridge 5 (the phase-shifted full-bridge 5 includes a series inductor Ls connected in series with the primary of a transformer 6 having a center-tapped secondary and a magnetizing inductor Lm connected in parallel with the primary of the transformer 6 having a center-tapped secondary), a rectifier 7, and an output stage 8.

[0051] The inverter full-bridge 4 includes two half-bridges connected between input terminals 2 and 3, each half-bridge having two switches connected in series. The first half-bridge includes switches S1 and S3, and the second half-bridge includes switches S2 and S4. The common terminal of switches S1 and S3 is connected to the series inductor Ls, and the common terminal of switches S2 and S4 is connected to the second terminal of the phase-shifted full-bridge 5. The rectifier includes two synchronous rectifiers S5 and S6, each connected to one output terminal of transformer 6, and the other terminals of the two synchronous rectifiers S5 and S6 are connected to the first output terminal 12 of the output stage 8. The secondary winding of transformer 6 includes a center tap 18, which is connected to the second output terminal 13 of the output stage 8. The output stage includes an output capacitor Cout, and the output voltage Vout is provided across output terminals 12 and 13.

[0052] Figure 2 In the middle, a) shows, as Figure 1 The switching scheme of the phase-shifted full-bridge converter is shown. Figures 1-2 In the illustrated embodiment, switches S1 and S3 are used, for example, as leading arms, while the lagging arms are switches S2 and S4. However, in another embodiment, switches S2 and S4 may be used as leading arms, and switches S1 and S3 as lagging arms.

[0053] In phase-shift modulation, both arms of the inverter operate with a duty cycle of approximately 50%, with one arm undergoing phase-shift modulation to adjust the voltage transfer ratio. This modulation results in freewheeling interval 20, where either the upper switches S1 and S2 are simultaneously turned on, or the lower switches S3 and S4 are simultaneously turned on. Freewheeling interval 20 is marked by the dashed line area.

[0054] The dead time of this switching scheme is not explicitly shown in the figure, but only schematically. The switching time is slightly delayed compared to the switching time.

[0055] Figure 2 In the diagram, b) shows the output voltage V of the inverter full bridge obtained using the switching scheme shown in a). AB and output current i LS .

[0056] like Figure 2 As shown in b), the lead bridge arm switches S1 and S3 are in the current i P2 The circuit is connected, and the current i is also connected. P2 Downward switching off. The lagging bridge arm switches S2 and S4 are in the current i P3 The circuit is connected, and the current i is also connected. P3 Turn off, where the current i P2 The absolute value is significantly greater than the current i P3 The absolute value of . Regarding this, it should be noted that the current i P2 and current i P3 It can be positive or negative, but the absolute value is the same.

[0057] therefore, Figure 2 The disadvantage of the switching scheme shown in a) is that the leading half-bridge always experiences greater switching losses than the lagging half-bridge. The leading half-bridge switches S1 and S3 turn off at higher currents, while the lagging half-bridge switches S2 and S4 turn off at significantly lower currents. Furthermore, this lower turn-off current of the lagging half-bridge may prevent the leading half-bridge from performing ZVS (Zero-Voltage Switching), thus exacerbating switching losses, especially under light load conditions. The energy of the series inductor Ls may be insufficient to ensure ZVS in the lagging half-bridge, leading to increased conduction losses in the leading half-bridge.

[0058] When the leading arm switches S1 and S3 are turned off, they enter the freewheeling interval. During this interval, the transformer current decreases, causing the lagging arm switches S2 and S4 to turn off at a significantly reduced current at the end of the freewheeling interval. Larger switching losses lead to thermal imbalance between the leading and lagging arm switches. The leading arm switch always has a higher temperature.

[0059] Figure 3 A schematic circuit diagram of an LLC converter 31 according to the present invention is shown, i.e., for applications such as Figure 5The switch scheme shown is based on the present invention.

[0060] The input voltage Vin is connected between the first input terminal 2 and the second input terminal 3. The LLC converter 31 also includes an inverter full bridge 4, an LLC resonant circuit 35, a transformer 6 with a center tap on the secondary side, a rectifier 7, and an output stage 8. The LLC resonant circuit 35 includes a resonant inductor Lr, a magnetizing inductor Lm, and a resonant capacitor Cr. The resonant inductor Lr and the resonant capacitor Cr are connected in series, and the magnetizing inductor Lm is connected in parallel with the primary side of the transformer 6.

[0061] The inverter full-bridge 4 includes two half-bridges connected between input terminals 2 and 3, each half-bridge having two switches connected in series. The first half-bridge includes switches S1 and S3, and the second half-bridge includes switches S2 and S4. The common terminal of switches S1 and S3 is connected to the resonant inductor Lr, and the common terminal of switches S2 and S4 is connected to the resonant capacitor Cr. The rectifier includes two synchronous rectifiers S5 and S6, each connected to one output terminal of transformer 6, and the other terminal of the two synchronous rectifiers S5 and S6 is connected to the first output terminal 12 of output stage 8. The secondary winding of transformer 6 includes a center tap 18, which is connected to the second output terminal 13 of output stage 8. The output stage includes an output capacitor Cout, and the output voltage Vout is provided through output terminals 12 and 13.

[0062] Switches S1-S4 are implemented using, for example, silicon carbide MOSFETs, silicon MOSFETs, or gallium nitride MOSFETs. However, other types of MOSFETs, or more generally, other types of transistors, can also be used. The optimal choice for implementing the switches depends on the specific application.

[0063] Figure 4 A schematic circuit diagram of a phase-shifted full-bridge converter 41 according to the present invention is shown, i.e., for applications such as... Figure 5 The switch scheme shown is based on the present invention.

[0064] The input voltage Vin is connected between the first input terminal 2 and the second input terminal 3. The phase-shifted full-bridge converter 1 also includes an inverter full-bridge 4, a phase-shifted full-bridge 5 (the phase-shifted full-bridge 5 includes a series inductor Ls connected in series with the primary of the transformer 6 and a magnetizing inductor Lm connected in parallel with the primary of the transformer 6), a rectifier 7, and an output stage 8.

[0065] The inverter full-bridge 4 includes two half-bridges connected between input terminals 2 and 3, each half-bridge having two switches connected in series. The first half-bridge includes switches S1 and S3, and the second half-bridge includes switches S2 and S4. The common terminal of switches S1 and S3 is connected to the series inductor Ls, and the common terminal of switches S2 and S4 is connected to the second terminal of the phase-shifted full-bridge 5. The rectifier includes four diodes D1, D2, D3, and D4, which are connected in a full-bridge configuration to the secondary side of transformer 6. The common terminal of diodes D1 and D2 is connected to the first output terminal 12 of output stage 8, and the common terminal of diodes D3 and D4 is connected to the second output terminal 13 of output stage 8. The output stage includes an output capacitor Cout, and the output voltage Vout is provided through output terminals 12 and 13.

[0066] Similarly, switches S1-S4 are implemented using, for example, silicon carbide MOSFETs or silicon MOSFETs. However, other types of MOSFETs, or more generally, other types of transistors, can also be used. The optimal choice for implementing the switches depends on the specific application.

[0067] Figure 5 A switching scheme according to the present invention is shown, which can be applied to, for example... Figure 1 The phase-shifting full-bridge converter 1 shown includes a center-tapped synchronous rectifier; it can be applied to applications such as... Figure 3 The LLC converter 31 shown includes a center-tapped synchronous rectifier; it can also be applied to, for example... Figure 4 The phase-shifting full-bridge converter 41 shown includes a diode full-bridge rectifier.

[0068] Figure 5 In the diagram, a) shows the switching scheme of switch S1, b) shows the switching scheme of switch S3, c) shows the switching scheme of switch S2, and d) shows the switching scheme of switch S4.

[0069] It should be noted that the control signal generated by the drive signal generator itself is not in Figure 5 As shown in the image.

[0070] It should also be noted that the dead time of the switching scheme is not explicitly shown in the figure, but only schematically. The switching time is slightly delayed compared to the switching time.

[0071] Figure 5 In diagram e), an up / down counter 40 is shown, whose period is twice the period T of the input voltage Vin. The up / down counter 40 starts from its minimum value of 0, gradually increases to its maximum value of 1 within one period T, and then gradually decreases from its maximum value of 1 back to its minimum value of 0 within another period T. Therefore, the up / down counter 40 has a period of 2T, which is also referred to as the modulation period T.mod . Figure 5 The value 'e' in the figure also shows the first comparison value 41 (which has the value D / 4) and the second comparison value 42 (which has the value (2+D) / 4).

[0072] It is important to note that, Figure 5 In the example shown, the first and second comparison values ​​shown in e) are used for the two half-bridges, namely, for switches S1 and S3, and for switches S2 and S4. Therefore, the up / down counters for switches S2 and S4 in the second half-bridge include a phase shift T. However, for clarity, Figure 5 The up / down counter used for the second half-bridge is not shown in the diagram.

[0073] Figure 5 Another example, not shown, is where no phase shift is applied between the two half-bridges, and both half-bridges use the same up / down counter 40. In this case, the comparison value of the first half-bridge will be compared with... Figure 5 The comparison is the same as shown in e), that is, the comparison value 41 has the value D / 4, and the second comparison value 42 has the value (2+D) / 4. However, the comparison values ​​of the second half-bridge are different. The first comparison value is 1-D / 4, and the second comparison value is (1-2+D) / 4.

[0074] from Figure 5 From a) to e), we can see that:

[0075] When the up / down counter 40 increments beyond the first comparison value 41, switch S1 is turned on; when the up / down counter 40 increments beyond the second comparison value 42, switch S1 is turned off. Then, when the up / down counter 40 decrements beyond the second comparison value 42, switch S1 is turned on; when the up / down counter 40 decrements beyond the first comparison value 41, switch S1 is turned off.

[0076] - When the increment / decrement counter 40 increments beyond the first comparison value 41, switch S3 is turned off; when the increment / decrement counter 40 increments beyond the second comparison value 42, switch S3 is turned on. Then, when the decrement counter 40 decrements beyond the second comparison value 42, switch S3 is turned off; when the decrement counter 40 decrements beyond the first comparison value 41, switch S3 is turned on.

[0077] Therefore, switch S3 and switch S1 are switched alternately. From Figure 5 From a) to e), we can further see that

[0078] Switch S2 is turned on and off in the same way as switch S3, but includes the phase shift period T.

[0079] - Switch S4 is turned on and off in the same way as switch S1, but also includes the phase shift period T.

[0080] Similarly, switches S2 and S4 are switched alternately.

[0081] Figure 5 f) in the figure shows the output voltage of the inverter full bridge 4 obtained therefrom. Figure 5 g) shows the output current i of the inverter full-bridge 4 obtained therefrom. Ls .

[0082] Despite Figure 5 The output current i of the inverter full-bridge 4 shown in g) is Ls With Figure 2 The output current i shown in b) is Ls There is no difference, but from Figure 5 From a) to d), it can be seen that in a single modulation period T mod =2T period:

[0083] -Switch S1 in current i P3 Once switched on, and in the current i P2 Once connected,

[0084] -Switch S1 in current i P3 Turn off once, and in current i P2 Turn off once,

[0085] -Switch S3 in current i P2 Once switched on, and in the current i P3 Once connected, and,

[0086] -Switch S3 in current i P3 Turn off once, and in current i P2 Turn it off once.

[0087] and,

[0088] -Switch S2 in current i P3 Once switched on, and in the current i P2 Once connected,

[0089] -Switch S2 in current i P2 Turn off once, and in current i P3 Turn off once,

[0090] -Switch S4 in current i P3 Once switched on, and in the current i P2 Once connected, and,

[0091] -Switch S4 in current i P3 Turn off once, and in current iP2 Turn it off once.

[0092] Or in other words, all switches S1-S4 at higher current i P2 and lower current i P3 The number of times the connection is made is the same as the number of times it is broken.

[0093] Therefore, as Figure 5 The switching scheme shown does not suffer from the disadvantage that one bridge arm bears a greater switching loss than another. Within a single modulation cycle of 2T, the turn-off and turn-on currents of all switches are the same.

[0094] Therefore, the thermal stress of all switches S1-S4 is the same. Furthermore, in a phase-shifted full-bridge converter, the energy of the series inductor is so small that ZVS will not fail under light load conditions.

[0095] The switching scheme according to the present invention can be applied not only to the inverter configuration described above, but also to LLC converters including diode full-bridge rectifiers. Furthermore, it can be applied to other converter configurations, including the inverter full-bridge described above, regardless of the specific implementation of the switching stage and secondary rectifier.

[0096] In summary, it should be noted that the present invention can create a converter comprising an inverter full-bridge and a corresponding closed-loop modulation method, which reduces or even eliminates thermal imbalance of the inverter full-bridge during operation.

Claims

1. A method for controlling a converter including an inverter full-bridge, the inverter full-bridge having a first input terminal, a second input terminal, a first half-bridge, and a second half-bridge, the first half-bridge and the second half-bridge being connected between the first input terminal and the second input terminal, wherein, An input voltage with a period T is provided between the first input terminal and the second input terminal, wherein each half-bridge includes a first switch and a second switch connected in series between the first input terminal and the second input terminal. The method is characterized in that, The drive signals for each switch are generated using pulse width modulation (PWM) with a duty cycle of D. The up-and-down counter used in the PWM technique has a period of T. mod The first comparison value and the second comparison value, the period T mod Twice the period T, When the up-down counter counts to the first comparison value, the first switch of the first half-bridge is turned on; when the up-down counter counts to the second comparison value, the first switch of the first half-bridge is turned off. When the up-down counter counts down to the second comparison value, the first switch of the first half-bridge is turned on; when the up-down counter counts down to the first comparison value, the first switch of the first half-bridge is turned off. The second switch of the first half-bridge switches alternately with the first switch of the first half-bridge. Wherein, the first comparison value of the first half-bridge is D / 4, and wherein, the second comparison value of the first half-bridge is (2+D) / 4; The method further includes switching the first and second switches of the second half-bridge in the same manner as the first and second switches of the first half-bridge, wherein the first comparison value of the second half-bridge is (1-D / 4), and wherein the second comparison value of the second half-bridge is (1-(2+D) / 4).

2. The method according to claim 1, wherein, In the period T mod In the first half, the up / down counter gradually increases from its minimum value to its maximum value, and then in the period T... mod In the latter half, the up-down counter gradually decreases from the maximum value to the minimum value, wherein the minimum value is zero and the maximum value is 1.

3. A converter comprising an inverter full-bridge having a first input terminal, a second input terminal, a first half-bridge, and a second half-bridge, the first half-bridge and the second half-bridge being connected between the first input terminal and the second input terminal, each half-bridge including a first switch and a second switch connected in series between the first input terminal and the second input terminal, and further comprising a drive signal generator for generating drive signals for each switch using pulse width modulation technique with a duty cycle D. The converter is characterized in that, The drive signal generator includes an up-down counter, which has a first comparison value, a second comparison value, and a period T. mod The period T mod T is twice the period T of the input voltage supplied between the first input terminal and the second input terminal, where, The drive signal generator is adapted to be Each switch in the method according to claim 1 or 2 generates a drive signal.

4. The converter of claim 3, further comprising a transformer, a conversion stage connected between the inverter full-bridge and the primary side of the transformer, a rectifier connected to the secondary side of the transformer, and an output stage connected to the rectifier, wherein, The output power of the converter is provided at the output terminal of the output stage.

5. The converter according to claim 4, wherein, The conversion stage includes an LLC resonant circuit.

6. The converter according to claim 4, wherein, The conversion stage includes a series inductor and a magnetizing inductor, wherein the series inductor is connected in series between the inverter full bridge and the transformer, and the magnetizing inductor is connected in parallel with the transformer.

7. The converter according to any one of claims 4 to 6, wherein, The rectifier includes a synchronous rectifier.

8. The converter according to claim 7, wherein, The synchronous rectifier includes a first controllable rectifier switch connected to a first output terminal of the transformer and a second controllable rectifier switch connected to a second output terminal of the transformer, wherein both controllable rectifier switches are connected to the first output terminal of the rectifier, and wherein the secondary winding of the transformer includes a center tap connected to the second output terminal of the rectifier.

9. The converter according to any one of claims 4 to 6, wherein, The rectifier includes a diode full-bridge rectifier.

10. The converter according to any one of claims 4 to 6, wherein, The output stage includes an output filter having a capacitor connected between the output terminals of the rectifier.

11. The converter according to any one of claims 4 to 6, wherein, The inverter full-bridge switches include MOSFETs.

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