Millimeter wave asymmetric doherty power amplifier chip based on equivalent parallel die structure

Abstract

The application discloses a millimeter wave asymmetric Doherty power amplifier chip based on an equivalent parallel die structure, which comprises a broadband input power divider (1), a carrier amplification circuit (2), a peak amplification circuit (3) and a back matching network (4), wherein the input end of the broadband input power divider is connected with a radio frequency signal input end; the output end of the carrier amplification circuit is connected with the output end of the peak amplification circuit after the output ends of the carrier amplification circuit and the peak amplification circuit are combined, and the combined output end is connected with the input end of the back matching network; and the output end of the back matching network is connected with a radio frequency signal output end. Compared with a conventional millimeter wave asymmetric gallium nitride monolithic integrated Doherty power amplifier chip, the application solves the problems of the low gain of a large-size transistor in a peak amplifier power stage, the small output impedance in an off state and the low saturation efficiency in the conventional millimeter wave asymmetric Doherty power amplifier, and realizes better broadband characteristics, so that the application can be applied to a 5G millimeter wave large-scale MIMO mobile communication system.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to a millimeter wave asymmetric Doherty power amplifier chip based on an equivalent parallel die structure. BACKGROUND

[0002] Enabling millimeter wave frequency band is one of the most important technical innovations of 5G. Due to its high frequency and large loss characteristics, the millimeter wave frequency band will bring greater challenges to the design of physical layer devices. In addition, in order to further improve the utilization rate of spectrum resources, more complex high-order modulation methods and more complex carrier aggregation technologies (Carrier Aggregation, CA) with more carrier numbers will be used, which will result in higher peak-to-average ratio of the modulated signal. Therefore, it is necessary to improve the efficiency of the millimeter wave power amplifier at a larger back-off output power.

[0003] In addition, large-scale multiple-input and multiple-output technology (Multiple-Input and Multiple-Output, MIMO) based on large-scale antenna arrays will be used to further improve the data throughput rate, while further improving the gain of the antenna and the ability of beam convergence. MIMO technology has been used in 4G technology. Compared with the traditional MIMO technology in 4G, 5G will use a larger antenna array with more antenna elements (the number of antenna elements ≥ 64), which can provide large array gain and multi-user spatial multiplexing function on the same time-frequency resource. The large-scale application of MIMO technology in 5G reduces the demand for single power amplifier output power and improves the demand for small size of power amplifier. High electron mobility monolithic integrated Doherty power amplifier chip based on gallium nitride (GaN) is one of the best choices to meet the above requirements, and has attracted widespread attention.

[0004] In order to further improve the back-off range of the Doherty power amplifier, it is usually necessary to use an asymmetric architecture, which requires the use of a larger size peak amplifier final transistor. The traditional millimeter wave asymmetric Doherty power amplifier directly uses a single larger size transistor as the final transistor of the peak amplifier, which will result in lower gain, lower output impedance in the off state, and lower efficiency in saturation. Therefore, it is necessary to research a millimeter wave power amplifier to solve the above problems. SUMMARY

[0005] The present application provides a millimeter wave asymmetric Doherty power amplifier chip based on an equivalent parallel die structure.

[0006] Technical solution: To achieve the above technical problems, the application provides a millimeter wave asymmetric Doherty power amplifier chip based on an equivalent parallel die structure, which comprises a broadband input power divider, a carrier amplification circuit, a peak amplification circuit and a back matching network.

[0007] The input end of the broadband input power divider is connected with the radio frequency signal input end.

[0008] The carrier amplification circuit is sequentially connected by a phase shift network, a first input matching network, a driving stage carrier amplifier, a first inter-stage matching network, a power stage carrier amplifier and a first output matching network, and the input end of the carrier amplification circuit is connected with the first output end of the broadband input power divider.

[0009] The peak amplification circuit is sequentially connected by a second input matching network, a driving stage peak amplifier, a second inter-stage matching network, a parallel power stage first peak amplifier and a power stage second peak amplifier and a second output matching network, and the input end of the peak amplification circuit is connected with the second output end of the broadband input power divider.

[0010] The output end of the carrier amplification circuit is combined with the output end of the peak amplification circuit, and then connected with the input end of the back matching network; and the output end of the back matching network is connected with the output end of the radio frequency signal.

[0011] In the peak amplification circuit, the parallel power stage first peak amplifier and the power stage second peak amplifier adopt an equivalent parallel die structure, which comprises two transistors with the size of N x W g ; the total gate width of the power stage first peak amplifier and the power stage second peak amplifier is N' x W g ', which is determined according to the required back-off range and saturation power; the size of the power stage first peak amplifier and the power stage second peak amplifier and the total gate width satisfy the following relationship:

[0012] N' x W g ' = 2 x N x W g

[0013] Wherein N is set to the maximum gate index allowed by the process under the condition of ensuring that W g does not violate the process rules.

[0014] The first output matching network is connected by the first output capacitor of the power stage carrier amplifier and the carrier output matching network connected thereto.

[0015] The second output matching network is composed of a second output capacitor of the power stage first peak value amplifier, a third output capacitor of the power stage second peak value amplifier, a first parallel resonant inductor, a second parallel resonant inductor, a first impedance transformation line, a second impedance transformation line and a third impedance transformation line; wherein the output end of the power stage first peak value amplifier is connected with the second output capacitor, the first parallel resonant inductor and the first impedance transformation line respectively; the output end of the power stage second peak value amplifier is connected with the third output capacitor, the second parallel resonant inductor and the second impedance transformation line respectively, and the other ends of the first impedance transformation line and the second impedance transformation line are connected with the third impedance transformation line after being combined.

[0016] The first input matching network is connected with a first external power supply end; the first inter-stage matching network is connected with a second external power supply end and the first external power supply end; the first output matching network is connected with the second external power supply end; the second input matching network is connected with a third external power supply end; the second inter-stage matching network is connected with the second external power supply end and the third external power supply end; and the second output matching network is connected with the second external power supply end.

[0017] The drive stage carrier wave amplifier, the power stage carrier wave amplifier, the drive stage peak value amplifier, the power stage first peak value amplifier and the power stage second peak value amplifier are all high electron mobility transistors.

[0018] The first impedance transformation line, the second impedance transformation line and the third impedance transformation line are all quarter wavelengths.

[0019] Beneficial effects: compared with the prior art, the application has the following advantages:

[0020] 1. The equivalent parallel die structure is adopted, and the problems of low gain, small output impedance in the off state and low saturation efficiency of the large-size transistor of the power stage of the peak value amplifier in the traditional millimeter wave asymmetric Doherty power amplifier are solved.

[0021] 2. The output capacitor of the carrier wave amplifier power stage transistor is absorbed into the equivalent quarter wavelength line network immediately after it; and the output capacitor of the peak value amplifier power stage transistor is resonated and offset, which can further expand the bandwidth of the millimeter wave Doherty power amplifier.

[0022] Overall, the millimeter wave asymmetric Doherty power amplifier chip based on the equivalent parallel die structure provided by the application has a large backoff range, high backoff and saturation efficiency, and good Doherty characteristics in a wide frequency range, and can be widely used as a millimeter wave power amplifier device in the fifth generation mobile communication millimeter wave large-scale MIMO system. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1A circuit structure principle block diagram of a millimeter wave asymmetric Doherty power amplifier chip based on an equivalent parallel die structure for the embodiment;

[0024] Figure 2 A comparison diagram of a power stage peak amplifier (right) adopting an equivalent parallel gate width structure and a traditional structure (left) in the specific embodiment of the application;

[0025] Figure 3 A comparison of output impedance simulation results of a power stage peak amplifier adopting an equivalent parallel gate width structure and a power stage peak amplifier adopting a traditional structure in an off state in the specific embodiment of the application;

[0026] Figure 4 A comparison of fundamental current ratio simulation results of a peak amplifier and a carrier amplifier of a millimeter wave asymmetric Doherty power amplifier adopting an equivalent parallel gate width structure power stage peak amplifier and a millimeter wave asymmetric Doherty power amplifier adopting a traditional structure power stage peak amplifier in a saturation state in the specific embodiment of the application;

[0027] Figure 5 Saturation power, efficiency and backoff efficiency simulation curves of a millimeter wave asymmetric Doherty power amplifier adopting a parallel gate width structure power stage peak amplifier and a traditional structure power stage peak amplifier in the specific embodiment of the application.

[0028] In the figure: a broadband input power divider 1, a carrier amplification circuit 2, a peak amplification circuit 3, a post-matching network 4; a phase shift network 21, a first input matching network 22, a first inter-stage matching network 23, a first output matching network 24, a carrier output matching network 241; a second input matching network 31, a second inter-stage matching network 32, a second output matching network 33; a driver stage carrier amplifier T1, a power stage carrier amplifier T2, a driver stage peak amplifier T3, a power stage first peak amplifier T4, a power stage second peak amplifier T5; a radio frequency signal input end RFIN, a radio frequency signal output end RFOUT; a first impedance transformation line TL1, a second impedance transformation line TL2, a third impedance transformation line TL3; a first output end out1 of the broadband input power divider, a second output end out2 of the broadband input power divider; a first output capacitor C out,C1 , a second output capacitor C out,P2 , a third output capacitor C out,P3 ; a first parallel resonant inductor L1, a second parallel resonant inductor L2; a first external power supply end V g1 , a second external power supply end V d , a third external power supply end V g2 . DETAILED DESCRIPTION

[0029] The application will be further described in detail below with reference to the embodiments and drawings, which do not constitute limitation to the application.

[0030] The millimeter wave asymmetric Doherty power amplifier chip with the equivalent parallel die structure provided by the embodiment includes: Figure 1

[0031] The broadband input power divider is connected with the input end of the radio frequency signal.

[0032] The input end of the carrier amplification circuit is connected with the first output end of the broadband input power divider; the carrier amplification circuit mainly includes a phase shift network, a first input matching network, a driving stage carrier amplifier T1, a first inter-stage matching network, a power stage carrier amplifier T2 and a first output matching network connected in sequence.

[0033] The input end of the peak amplification circuit is connected with the second output end of the broadband input power divider; the peak amplification circuit mainly includes a second input matching network, a driving stage peak amplifier T3, a second inter-stage matching network, a power stage first peak amplifier T4, a power stage second peak amplifier T5 and a second output matching network connected in sequence.

[0034] The output end of the carrier amplification circuit and the output end of the peak amplification circuit are connected with the input end of the post matching circuit after being combined; the output end of the post matching circuit is connected with the output end of the radio frequency signal.

[0035] The broadband input power divider, the phase shift network, the first input matching network, the first inter-stage matching network, the second input matching network, the second inter-stage matching network, the carrier output matching network and the post matching network in the application can be realized by using the prior art or conventional technical means in the field.

[0036] The first output matching network is connected with the carrier output matching network in sequence. out,C1

[0037] The power stage peak amplifier adopting the equivalent parallel die structure includes two transistors, i.e., a power stage first peak amplifier T4 and a power stage second peak amplifier T5, both having a size of N×W. g The total gate width of the power stage first peak amplifier T4 and the power stage second peak amplifier T5 is N'×W. g The required back-off range and saturation power are determined according to the total gate width; the size of the power stage first peak amplifier T4 and the power stage second peak amplifier T5 needs to satisfy the following relationship with the total gate width:

[0038] N'×W​​g = 2 x N x W g

[0039] where N is set to the maximum gate number allowed by the process under the condition that W g does not violate the process rules.

[0040] The second output matching network is composed of the second output capacitor C out,P2 , the third output capacitor C out,P3 , their respective first parallel resonant inductor L1, second parallel resonant inductor L2, quarter-wave first impedance transformation line TL1, second impedance transformation line TL2, third impedance transformation line TL3 in parallel.

[0041] Figure 2 is a comparison chart of the power stage peak amplifier with equivalent parallel gate width structure and the conventional structure. The left side is the power stage peak amplifier transistor structure with the conventional structure, and the right chart is the power stage peak amplifier structure with the equivalent parallel gate width structure.

[0042] Figure 3 is a comparison of the output impedance simulation results of the power stage peak amplifier with equivalent parallel gate width structure and the power stage peak amplifier with conventional structure in the off state. From Figure 3 it can be seen that the equivalent parallel die structure can effectively improve the output impedance of the power stage peak amplifier in the off state.

[0043] Figure 4 is a comparison of the fundamental current ratio simulation results of the millimeter wave asymmetric Doherty power amplifier with the peak amplifier and the carrier amplifier when the power stage peak amplifier with equivalent parallel gate width structure and the power stage peak amplifier with conventional structure are saturated. From Figure 4 it can be seen that the equivalent parallel gate width structure can effectively improve the fundamental current ratio of the millimeter wave asymmetric Doherty power amplifier in saturation, and thus enhance the load modulation.

[0044] Figure 5 is the large signal characteristic simulation results of the millimeter wave asymmetric Doherty power amplifier with the power stage peak amplifier with equivalent parallel gate width structure and the power stage peak amplifier with conventional structure. From Figure 5It can be seen that the overall performance of the millimeter wave asymmetric Doherty power amplifier can be effectively improved by using the equivalent parallel gate width structure. The center frequency of the Doherty power amplifier chip of the specific embodiment is 26 GHz, the bandwidth is 4 GHz, the full-band saturated power is 37.6-38.4 dBm, and the saturated efficiency is 32.5-35.4%. The 8-dB backoff efficiency is 20.2-31.7%. The power gain in the low power region is greater than 14.9 dB, and the simulation results show good Doherty power amplifier characteristics.

[0045] As described above, although the present application has been shown and described with respect to a certain preferred embodiments thereof, it should be construed as not limited thereto since modifications in form and detail thereof can be made without departing from the spirit and scope of the application as defined by the appended claims.

Claims

1. A millimeter-wave asymmetric Doherty power amplifier chip based on an equivalent parallel die structure, characterized in that, The power amplifier chip includes: a broadband input power divider (1), a carrier amplifier circuit (2), a peak amplifier circuit (3), and a post-matching network (4); among which, The input terminal of the broadband input power divider (1) is connected to the radio frequency signal input terminal (RFIN); The carrier amplifier circuit (2) is composed of a phase shifting network (21), a first input matching network (22), a driver stage carrier amplifier (T1), a first interstage matching network (23), a power stage carrier amplifier (T2), and a first output matching network (24) connected in sequence. The input terminal of the carrier amplifier circuit (2) is connected to the first output terminal (out1) of the broadband input power divider. The peak amplifier circuit (3) is composed of a second input matching network (31), a driver stage peak amplifier (T3), a second interstage matching network (32), a power stage first peak amplifier (T4) and a power stage second peak amplifier (T5) connected in parallel, and a second output matching network (33) connected in sequence; the input terminal of the peak amplifier circuit is connected to the second output terminal (out2) of the broadband input power divider; After the output of the carrier amplifier circuit (2) is combined with the output of the peak amplifier circuit (3), it is connected to the input of the matching network (4); the output of the matching network (4) is connected to the output of the radio frequency signal (RFOUT). In the peak amplifier circuit (3), the parallel power stage first peak amplifier (T4) and power stage second peak amplifier (T5) adopt an equivalent parallel die structure, which includes two N×W diodes. g The transistors; the total gate width of the first peak amplifier (T4) and the second peak amplifier (T5) of the power stage is N'×W. g The dimensions of the first peak amplifier (T4) and the second peak amplifier (T5) of the power stage, as determined by the required back-off range and saturation power, must satisfy the following relationship with the total gate width: N′×W g ′=2×N×W g Where N ensures W g Without violating process rules, set it to the maximum gate index allowed by the process.

2. The millimeter-wave asymmetric Doherty power amplifier chip based on an equivalent parallel die structure as described in claim 1, characterized in that, The first output matching network (24) consists of the first output capacitor (C) of the power stage carrier amplifier (T2). out,C1 It is cascaded with the carrier output matching network (241) that follows it.

3. The millimeter-wave asymmetric Doherty power amplifier chip based on an equivalent parallel die structure as described in claim 1, characterized in that, The second output matching network (33) consists of the second output capacitor (C) of the first peak amplifier (T4) of the power stage. out,P2 ), the third output capacitor (C) of the second peak amplifier (T5) in the power stage out,P3 The system consists of a first parallel resonant inductor (L1), a second parallel resonant inductor (L2), a first impedance transformation line (TL1), a second impedance transformation line (TL2), and a third impedance transformation line (TL3); wherein, the output terminal of the first peak amplifier (T4) of the power stage is connected to the second output capacitor (C). out,P2 The first parallel resonant inductor (L1) and the first impedance transformation line (TL1) are connected; the output of the second peak amplifier (T5) of the power stage is connected to the third output capacitor (C). out,P3 The second parallel resonant inductor (L2) and the second impedance transformation line (TL2) are connected together, and the other ends of the first impedance transformation line (TL1) and the second impedance transformation line (TL2) are connected to the third impedance transformation line (TL3).

4. The millimeter-wave asymmetric Doherty power amplifier chip based on an equivalent parallel die structure as described in claim 1, characterized in that, The first input matching network (22) and the first external power supply terminal (V) g1 ) connection; the first inter-stage matching network (23) and the second external power supply terminal (V d ) and the first external power supply terminal (V g1 ) connection; the first output matching network (24) and the second external power supply terminal (V d The second input matching network (31) is connected to the third external power supply terminal (V). g2 ) connection; the second-stage inter-matching network (32) and the second external power supply terminal (V d ) and the third external power supply terminal (V g2 ) connection; the second output matching network (33) is connected to the second external power supply terminal (V d )connect.

5. The millimeter-wave asymmetric Doherty power amplifier chip based on an equivalent parallel die structure as described in claim 1, characterized in that, The driver stage carrier amplifier (T1), power stage carrier amplifier (T2), driver stage peak amplifier (T3), power stage first peak amplifier (T4), and power stage second peak amplifier (T5) are all high electron mobility transistors.

6. The millimeter-wave asymmetric Doherty power amplifier chip based on an equivalent parallel die structure as described in claim 1, characterized in that, The first impedance transformation line (TL1), the second impedance transformation line (TL2), and the third impedance transformation line (TL3) are all quarter wavelengths.

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