Computing devices and terminal equipment

Abstract

An embodiment of the present invention provides a computing device and terminal device. The computing device is applied to a first terminal device and includes: a first computing module; the first computing module includes an integrated circuit board, the front of which is provided with a computing unit, an integrated power module, and a sideband signal connector, the computing unit being connected to the integrated power module and the sideband signal connector respectively; the back of the integrated circuit board is provided with multiple high-speed serial interfaces and multiple memory interfaces, the high-speed serial interfaces and the memory interfaces being connected to the computing unit respectively. The computing device provided by the embodiment of the present invention can minimize wiring distance, significantly reduce impedance and transmission loss, and thus more easily meet the diverse and ever-expanding computing power requirements.

Description

Technical Field

[0001] The present invention relates to the technical field of servers, and in particular to computing devices and terminal equipment. Background Art

[0002] To meet the diverse and exponentially growing data computing needs, high-density and highly converged servers are developing rapidly.

[0003] In the prior art, a server chassis includes multiple independent computing motherboards, each of which integrates a CPU (Central Processing Unit) / GPU (Graphics Processing Unit) / FPGA (Field Programmable Gate Array), memory, and various slots.

[0004] However, there are many integrated structures on the computing motherboard, and the memory and various slots are distributed at the edge. The wiring distance is long and the transmission loss is high, which is not conducive to meeting the diversified and ever-expanding computing power needs. Summary of the Invention

[0005] The purpose of the embodiments of the present invention is to provide a computing device and terminal equipment to solve the technical problems of long wiring distances and high transmission losses on computing motherboards in the prior art. The specific technical solutions are as follows:

[0006] In a first aspect of the present invention, a computing device is provided, which is applied to a first terminal device and includes: a first computing module;

[0007] The first computing module includes an integrated circuit board, a computing unit, an integrated power module and a sideband signal connector are provided on the front of the integrated circuit board, and the computing unit is connected to the integrated power module and the sideband signal connector respectively;

[0008] The back side of the integrated circuit board is provided with a plurality of high-speed serial interfaces and a plurality of memory interfaces, and the high-speed serial interfaces and the memory interfaces are respectively connected to the computing units.

[0009] Optionally, the first computing module further includes multiple solid-state hard drives, the multiple memory interfaces are respectively used to connect the multiple solid-state hard drives, and the memory interfaces are used to realize serial communication between the solid-state hard drives and the computing unit.

[0010] Optionally, the memory interface is an EDSFF connector.

[0011] Optionally, it further includes: a second computing module having the same structure as the first computing module;

[0012] The high-speed serial interface includes a first PCIE×8 connector, and the first computing module and the second computing module are connected via the first PCIE×8 connector.

[0013] Optionally, the high-speed serial interface further includes a second PCIE×8 connector, and the second PCIE×8 connector is used to connect to a second terminal device.

[0014] Optionally, the high-speed serial interface further includes a first PCIE×16 connector, and the first PCIE×16 connector is used to configure a PCIEx16 device.

[0015] Optionally, the high-speed serial interface further includes a second PCIE×16 connector, where the second PCIE×16 connector is used to connect to a PCIE Switch unit of the first terminal device, and the PCIE Switch unit of the first terminal device is used to connect to a PCIE Switch unit of the second terminal device.

[0016] Optionally, a through hole connected to a system power bus of the first terminal device is provided on the integrated circuit board.

[0017] Optionally, the computing unit includes a CPU, and a plurality of OMI interfaces are provided on the CPU, and the plurality of OMI interfaces are respectively connected to the plurality of memory interfaces.

[0018] In a second aspect of the implementation of the present invention, a terminal device is further provided, comprising any one of the computing devices described above.

[0019] In a computing device provided by an embodiment of the present invention, a computing unit, an integrated power module, and a sideband signal connector are arranged on the front side of an integrated circuit board, and multiple high-speed serial interfaces and multiple memory interfaces are arranged on the back side of the integrated circuit board. By arranging the computing unit, the integrated power module, the sideband signal connector, the high-speed serial interface, and the memory interface on different sides of the integrated circuit board, that is, a back-to-back design, the wiring distance can be shortened to the maximum extent, the impedance and transmission loss are greatly reduced, and the problem of long wiring distance and high transmission loss on the computing motherboard can be solved, thereby making it easier to meet the diversified and ever-expanding computing power requirements; in addition, by arranging the computing unit, the integrated power module, the sideband signal connector, the high-speed serial interface, and the memory interface on different sides of the integrated circuit board, full utilization of the integrated circuit board can be achieved, more high-speed serial interfaces and memory interfaces can be arranged on a limited integrated circuit board, and the size of the required integrated circuit board and the space occupied can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for describing the embodiments or the prior art.

[0021] Figure 1 A front schematic diagram of a first computing module provided in an embodiment of the present invention;

[0022] Figure 2 The back side of the first computing module provided in the embodiment of the present invention is shown as follows Figure 1 ;

[0023] Figure 3 The back side of the first computing module provided in the embodiment of the present invention is shown as follows Figure 2 ;

[0024] Figure 4 A schematic diagram of the connection of the first computing module provided in an embodiment of the present invention;

[0025] Figure 5 A schematic diagram of the structure of a computing device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present invention will be described below with reference to the accompanying drawings in the embodiments of the present invention.

[0027] The current growth and popularity of cloud services has laid the foundation for the increasing adoption of diverse services to meet diverse data computing needs. The use of artificial intelligence (AI) and machine learning is further stimulating exponential growth in the demand for data computing power. To meet these diverse and expanding computing needs, high-density, highly converged servers are rapidly developing.

[0028] In the prior art, a server chassis includes multiple independent computing motherboards, with the CPU (Central Processing Unit) / GPU (Graphics Processing Unit) / FPGA (Field Programmable Gate Array), memory, and various slots integrated on the same surface of the computing motherboard. However, many structures are integrated on the same surface of the computing motherboard. The CPU is located in the center of the same surface of the computing motherboard, while the memory and various slots are located at the edge. The CPU is far away from the memory and various slots, resulting in long wiring distances and high transmission losses, which is not conducive to meeting the diverse and ever-expanding computing power requirements.

[0029] To address the above-mentioned issues, in a first aspect, embodiments of the present invention provide a computing device that can be applied to a terminal device, such as a server chassis, a computer chassis, a messaging device, or a mobile phone. The computing device mentioned above is described in detail below.

[0030] Reference Figure 1 、 Figure 2 and Figure 3 , a computing device, applied to a first terminal device, includes: a first computing module; the first computing module includes an integrated circuit board, the front of the integrated circuit board is provided with a computing unit, an integrated power module and a sideband signal connector, and the computing unit is respectively connected to the integrated power module and the sideband signal connector; the back of the integrated circuit board is provided with multiple high-speed serial interfaces and multiple memory interfaces, and the high-speed serial interfaces and the memory interfaces are respectively connected to the computing units.

[0031] Specifically, a computing device may include multiple computing modules, which may be interconnected. By providing multiple computing modules in a computing device, the computing performance of the computing device can be improved, making it easier to meet diverse and expanding computing power requirements. An integrated circuit board has two opposing front and back surfaces. The integrated circuit board is a carrier for carrying integrated circuits. The integrated circuit board is manufactured using semiconductor technology and may utilize a PCB (Printed Circuit Board).

[0032] The computing unit is electrically connected to the integrated power module, and to the sideband signal connector. The computing unit is a processor, which has flexible configurations and can be configured according to actual needs. For example, it can be a general-purpose processor, including a CPU, GPU, or network processor (NP); it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), an FPGA or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component.

[0033] The computing unit may be a CPU, which may be packaged in a CPU BGA (Ball Grid Array) package. The CPU BGA may be directly soldered onto an integrated circuit board. Compared to a CPU mounted on a motherboard via a slot, the structure of the CPU BGA soldered onto the integrated circuit board reduces thickness and improves CPU signal integrity. Figure 1The computing unit is located at the center of the front of the integrated power module. The computing unit can also be located elsewhere on the front of the integrated power module based on actual needs. The front of the integrated power module houses only the computing unit, the integrated power module, and the sideband signal connector, providing ample space for the computing unit.

[0034] The integrated power module, namely the Power Module, is used to supply power to the computing unit. The input of the integrated power module is 12V DC, and the output of the integrated power module can be set according to the actual needs of the computing unit. Sideband refers to the modulated signal, which generates a frequency band on the upper and lower sides of the center carrier frequency, called a sideband. The computing unit will generate a low-speed signal, and the sideband signal connector, namely the Sideband signal connector, is used to fan out the low-speed signal of the computing unit, such as the fan-out of the low-speed signal in the CPU / GPU / FPGA. The first terminal device also includes a system management unit, and the sideband signal connector is also used to electrically connect to the system management unit in the first terminal device, so as to realize low-speed signal interconnection between multiple different computing modules. The system management unit can specifically use a BMC (Baseboard Management Controller).

[0035] The integrated circuit board has a length direction and a width direction. The length direction of the integrated circuit board can refer to Figure 1 The direction indicated by arrow A in the middle is the width direction of the integrated circuit board. Figure 1 The integrated power module and the sideband signal connector are located on the same side of the length direction of the integrated circuit board. Of course, the integrated power module and the sideband signal connector can also be located on both sides of the length direction of the integrated circuit board.

[0036] The computing unit is electrically connected to the high-speed serial interface, and the computing unit is electrically connected to the memory interface. The high-speed serial interface can be used for communication between the first computing module and other devices, and the other devices can be other computing modules, other terminal devices, or PCIE (Peripheral Component Interconnect Express) devices. The high-speed serial interface can use EDSFF (Enterprise and Datacenter SSD Form Factor, enterprise and data center fixed hard disk specifications) 4C / 4C+ connectors or PCIE connectors, etc. The PCIE connector can specifically use PCIE×4 connectors, PCIE×8 connectors, or PCIE×16 connectors, etc. The memory interface is used for serial communication between the first computing module and the memory. The memory can be a pluggable serial memory, and the memory interface can use an EDSFF connector.

[0037] In a computing device provided by an embodiment of the present invention, a computing unit, an integrated power module, and a sideband signal connector are arranged on the front side of an integrated circuit board, and multiple high-speed serial interfaces and multiple memory interfaces are arranged on the back side of the integrated circuit board. By arranging the computing unit, the integrated power module, the sideband signal connector, the high-speed serial interfaces, and the memory interfaces on different sides of the integrated circuit board, wiring distances can be minimized, impedance and transmission loss can be significantly reduced, and the problem of long wiring distances and high transmission losses on the computing motherboard when the aforementioned structure is designed entirely on the same plane can be solved, thereby more easily meeting the diverse and ever-expanding computing power requirements. Furthermore, arranging the computing unit, the integrated power module, the sideband signal connector, the high-speed serial interfaces, and the memory interfaces on different sides of the integrated circuit board can fully utilize the integrated circuit board, allowing more high-speed serial interfaces and memory interfaces to be arranged on a limited integrated circuit board, thereby reducing the required size and space occupied by the integrated circuit board. Furthermore, when the computing unit is a CPU, by arranging only the computing unit, the integrated power module, and the sideband signal connector on the front side of the integrated circuit board, it is possible to directly solder the CPU BGA to the integrated circuit board, eliminating the CPU socket and improving the integrity of the CPU signal.

[0038] Reference Figure 4 The first computing module also includes multiple solid-state hard drives, and the multiple memory interfaces are respectively used to connect the multiple solid-state hard drives, and the memory interfaces are used to realize serial communication between the solid-state hard drives and the computing unit.

[0039] Specifically, multiple solid-state drives can be used as memory pools for computing units, and the number of solid-state drives can be set to be the same as the number of memory interfaces. The solid-state drive can be an E3.S drive. The height of the E3.S drive allows the solid-state drive to use a ×4, ×8, or even ×16 PCIE connector, which can achieve higher bandwidth and can be configured with higher operating power. Figure 4 For example, if the back of the integrated circuit board is provided with twelve memory interfaces, the number of connected solid-state drives is also twelve. Of course, the number of memory interfaces can also be set according to actual needs, such as eight or ten. One end of the memory interface is used to connect to the corresponding interface on the computing unit, and the other end of the memory interface is used to connect to the solid-state drive, thereby realizing serial communication between the solid-state drive and the computing unit.

[0040] In this embodiment, serial communication between the computing unit and the solid-state drive is used. Compared with the DDRx parallel memory commonly used in server CPUs in the prior art, the interface bandwidth is higher and the latency is reduced, making it easier to meet the diverse and ever-expanding computing power requirements. For example, a current general-purpose CPU has a maximum of 12 DDR channels on the left and right sides, using DDR5-5200 memory, with a bandwidth of 41.6GB / s per channel, and 12 channels of approximately 500GB / s. The computing unit in this embodiment can use an AMD EPYC Genoa series CPU, which uses an OMI (Open Memory Interface)-32G interface OMI channel, each interface bandwidth can reach 64GB / s. With 12 interfaces on each side, the bandwidth can reach a maximum of 1536GB / s, which is significantly higher than the traditional DDR5 interface rate. The computing unit can be connected to the memory interface through multiple connecting lines, and the OMI channel is formed in the connecting lines.

[0041] Furthermore, the integrated circuit board of this embodiment can be configured with more solid-state drives, further increasing the configurable memory capacity of the computing device provided by this embodiment. For example, in the prior art, CPUs employ up to DDR5 parallel memory. The capacity of a single DDR5-5200 memory stick is 16GB, so a single side can support up to 96GB of memory. The first computing module provided by this embodiment can support 512Gbyte bandwidth OMI memory on a single side, further increasing the configurable memory capacity.

[0042] The memory interface is an EDSFF connector, specifically an EDSFF4C / 4C+ connector. By setting the memory interface to an EDSFF connector, the connection requirements between the E3.S hard drive and other devices can be met, avoiding interface conversion. The memory interface can be a serial interface, that is, the computing device provided in this embodiment uses a serial interface connection solution. Compared with the traditional DDR parallel interface, the number of PCB layers can be reduced, thereby reducing costs.

[0043] Reference Figure 3, the EDSFF connectors can be set to twelve, and the twelve EDSFF connectors can be divided into two columns, each column includes six EDSFF connectors, and the two columns of EDSFF connectors are located on both sides of the length direction of the integrated circuit board. The arrangement of the two columns of EDSFF connectors on both sides of the computing unit can facilitate the routing between the computing unit and the EDSFF connector, and shorten the routing distance between the computing unit and the EDSFF connector, greatly reducing the impedance and transmission loss. A heat sink can also be provided between the two columns of EDSFF connectors on the back of the integrated circuit board. The heat sink is used to dissipate heat from the computing unit to meet the heat dissipation requirements of the computing unit. Of course, multiple EDSFF connectors can also be distributed in the shape of a "mouth" around the computing unit, which is not specifically limited in this embodiment.

[0044] The computing device provided by the embodiment of the present invention also includes: a second computing module with the same structure as the first computing module; the high-speed serial interface includes a first PCIE×8 connector, and the first computing module and the second computing module are connected through the first PCIE×8 connector.

[0045] Specifically, the second computing module can be any one of the multiple computing modules included in the computing device. The high-speed serial interface includes multiple first PCIE×8 connectors. The number of first PCIE×8 connectors can be set to six, seven, eight or ten, etc., which is not specifically limited in this embodiment. The first PCIE×8 connector can use the PCIE-GEN5 high-speed connector type. The PCIE-GEN5 high-speed connector adopts PCIE5.0 technology. PCIE5.0 technology can achieve 128GB / s X16 duplex bandwidth and a rate of 32GT / s. That is, the PCIE-GEN5 high-speed connector type can have an extremely high signal rate and can better support high-performance devices with high throughput requirements.

[0046] Reference Figure 3 , there are seven first PCIE × 8 connectors, and the seven first PCIE × 8 connectors are located on both sides of the width direction of the back side of the integrated circuit board, that is, the seven first PCIE × 8 connectors are distributed on the upper and lower edges of the integrated circuit board. Because the first PCIE × 8 connector is used to connect the first computing module with the second computing module, arranging the first PCIE × 8 connector at the edge of the integrated circuit board can facilitate the connection and routing of the first computing module and the second computing module.

[0047] The first computing module and the second computing module can be connected via a single or multiple first PCIE×8 connectors. Figure 5The first computing module and the second computing module are connected via three first PCIE x8 connectors. Of course, the first PCIE x8 connector can also be connected to the second computing module without connecting to the second computing module, and can be flexibly configured with PCIE devices. In addition, the first computing module and the second computing module can be connected via only one first PCIE x8 connector, and the other first PCIE x8 connectors can be flexibly configured with PCIE devices.

[0048] Through the setting of the first PCIE×8 connector, the computing modules can be interconnected to form a multi-channel system, thereby forming memory pooling to meet the application of high-performance computing scenarios; and through the interconnection of computing modules, the computing performance of the computing device can be improved, thereby making it easier to meet the diverse and ever-expanding computing power requirements.

[0049] Reference Figure 5 The computing device may include four computing modules: a first computing module, a second computing module, a third computing module, and a fourth computing module. The computing modules are interconnected in pairs. For example, the first computing module is configured with seven first PCIE×8 connectors, and the first computing module can be interconnected with the other three computing modules through the seven first PCIE×8 connectors. The second computing module is also configured with seven first PCIE×8 connectors, and the second computing module can be interconnected with the other three computing modules through the seven first PCIE×8 connectors. The third computing module is also configured with seven first PCIE×8 connectors, and the third computing module can be interconnected with the other three computing modules through the seven first PCIE×8 connectors. The fourth computing module is also configured with seven first PCIE×8 connectors, and the fourth computing module can be interconnected with the other three computing modules through the seven first PCIE×8 connectors. That is, each computing module is provided with multiple first PCIE×8 connectors to realize the interconnection of the computing module with all other computing modules in the computing device. Through this interconnection method, as many multi-channel systems as possible are constructed, thereby forming memory pooling to meet the application of high-performance computing scenarios.

[0050] Of course, the number of computing modules provided in the computing device can also be specifically set according to actual needs, for example, the number of computing modules can be two, three, five, or six. In other embodiments, the first computing module can also be interconnected with only one other computing module, for example, the first computing module can be interconnected with only the second computing module, but not with the third computing module and the fourth computing module.

[0051] The computing unit can be a CPU / GPU / FPGA. The types of computing units in the multiple computing modules in this embodiment can be different. For example, in the four computing modules, the computing unit in the first computing module can be a CPU, the computing unit in the second computing module can be a GPU, the computing unit in the third computing module can be an FPGA, and the computing unit in the fourth computing module can be a CPU. Of course, the types of computing units in multiple computing modules can also be the same, such as the computing units in the first computing module, the second computing module, the third computing module, and the fourth computing module can all be CPUs. That is, the computing device provided in this embodiment is compatible with CPU / GPU / FPGA, and the computing units can be flexibly configured and quickly deployed according to actual needs, thereby reducing the R&D cycle.

[0052] The high-speed serial interface further includes a second PCIE×8 connector, and the second PCIE×8 connector is used to connect to a second terminal device.

[0053] Specifically, the high-speed serial interface may include one or more second PCIE×8 connectors, and the second PCIE×8 connector may be a PCIE-GEN5 high-speed connector type, and the second PCIE×8 connector may be used as an expansion interface. Figure 2 , the high-speed serial interface may include a second PCIE×8 connector. In this embodiment, there may be multiple terminal devices, and the terminal devices can be interconnected. Each terminal device includes a computing device. The second terminal device is any terminal device different from the first terminal device. The second PCIE×8 connector is used to connect the first terminal device where the computing device is located to the second terminal device, that is, the second PCIE×8 connector in the first terminal device will be connected to the second PCIE×8 connector in the second terminal device. By setting the second PCIE×8 connector, the terminal devices can be interconnected.

[0054] The second PCIE x8 connector in the first terminal device can be connected to the second terminal device via an adapter board. Specifically, the second PCIE x8 connector is connected to the adapter board, which is then connected to the second terminal device. The adapter board converts signals from the PCIE x8 connector into signals that support long-distance transmission. While PCIE x8 connectors only support short-distance signal transmission, the adapter board enables long-distance interconnection between terminal devices.

[0055] The high-speed serial interface further includes a first PCIE×16 connector, and the first PCIE×16 connector is used to configure a PCIEx16 device.

[0056] Specifically, the first PCIE×16 connector can be a PCIE-GEN5 high-speed connector type, and the high-speed serial interface can include multiple first PCIE×16 connectors, such as the first PCIE×16 connector can be set to two, three or four. Figure 3 The first PCIE×16 connector can be set to three. The PCIE×16 connector has good compatibility and is backward compatible with PCIE×1 / PCIE×4 / PCIE×8 connectors. In addition, the PCIE×16 connector has more channels and higher bandwidth.

[0057] The first PCIE x16 connector is used to configure a PCIEx16 device. For example, one of the first PCIE x16 connectors can be configured as an NVMe SSD hard drive to run the OS, and the other first PCIE x16 connector can be configured as a x16 OCP (Open Compute Project) NIC (network interface card). By setting up multiple first PCIE x16 connectors, multiple different PCIEx16 devices can be configured to meet different connection expansion requirements.

[0058] The high-speed serial interface further includes a second PCIE×16 connector, which is used to connect to the PCIE Switch unit of the first terminal device, and the PCIE Switch unit of the first terminal device is used to connect to the PCIE Switch unit of the second terminal device.

[0059] Specifically, the first terminal device includes a PCIE Switch unit, and the high-speed serial interface may include one or more second PCIE×16 connectors, such as, referring to Figure 3 The high-speed serial interface includes a second PCIE×16 connector. The second PCIE×16 connector can be a PCIE-GEN5 high-speed connector type. At the same time, the first PCIE×16 connector and the second PCIE×16 connector can both be an EDSFF4C / 4C+ connector. In addition, the second PCIE×16 connector can be used as an uplink PCIE channel to connect to the PCIE Switch unit in the first terminal device. The PCIE Switch unit in the first terminal device can be connected to the PCIE Switch unit in the second terminal device to achieve interconnection between terminal devices at close range.

[0060] Reference Figure 2 There are four first PCIE×16 connectors and second PCIE×16 connectors in total, two of which are located at one column of EDSFF connectors, and the other two are located at another column of EDSFF connectors. Figure 3, 12 EDSFF connectors are respectively connected to the opposite sides of the CPU as a computing unit, and the first PCIE×8 connector, the second PCIE×8 connector, the first PCIE×16 connector and the second PCIE×16 connector are respectively connected to the opposite sides of the CPU.

[0061] The integrated circuit board is provided with a through hole connected to the system power bus of the first terminal device, referring to Figure 1 and Figure 2 Two through-holes are provided, one on either side of the integrated circuit board's width, one of which is grounded. Specifically, the through-holes can be circular through-holes that penetrate both the front and back sides of the integrated circuit board. The provision of the through-holes enables connection between the integrated circuit board and the system power busbar of the first terminal device.

[0062] The computing unit includes a CPU, and a plurality of OMI interfaces are provided on the CPU. The plurality of OMI interfaces are respectively connected to the plurality of memory interfaces.

[0063] Specifically, the CPU can use the AMD EPYC Genoa series CPU. The AMD Genoa CPU supports 12 groups of OMI interfaces, that is, 12 OMI interfaces can be set on the CPU. In this case, each OMI interface is connected to the EDSFF connector, and each EDSFF connector is connected to an E3.S hard drive. Then, the CPU can support 512Gbyte bandwidth OMI memory on one side. Differential transmission is a signal transmission technology. Different from the traditional method of one signal line and one ground line, differential transmission transmits signals on both lines. The two signals have the same amplitude and opposite phase. The signal transmitted on these two lines is a differential signal. The CPU is provided with an OMI interface that supports a serial protocol that uses differential signals. By using differential signals, the signal anti-interference capability of the computing device is further improved.

[0064] In addition, the advantage of using the OMI interface is that it balances memory bandwidth with the bandwidth of the Fabric and PCIE, thereby achieving bandwidth improvement, while also reducing power consumption and improving random access memory technology. For example, in the prior art, if computing modules want to access each other's memory, they must first connect to the computing unit of another computing module through a PCIE connector, and then access DDR memory through the computing unit. However, the development of DDR bandwidth lags behind the development of PCIE bandwidth. As a result, when computing modules in the prior art want to access each other's memory, the bandwidth will be reduced from high-speed bandwidth to low-speed bandwidth, that is, the speed level will be reduced, which is not conducive to bandwidth improvement. In the computing device provided in this embodiment, when a first computing module wants to access the memory of a second computing module, it first connects to the computing unit of the second computing module through a first PCIE×8 connector. Then, it accesses the solid-state drive through the OMI interface and EDSFF connector of the computing unit of the second computing module. This process always maintains high bandwidth, and the speed level remains at the same level, thereby achieving bandwidth improvement. The computing device provided in this embodiment accesses the solid-state drive through the OMI interface and EDSFF connector of the computing unit, which consumes less power than the prior art method of accessing DDR memory through the computing unit.

[0065] In a second aspect, an embodiment of the present invention provides a terminal device, which may include any of the aforementioned computing devices. For example, in one embodiment, the terminal device includes a computing device, which includes a first computing module; the first computing module includes an integrated circuit board, the front of which is provided with a computing unit, an integrated power module, and a sideband signal connector, the computing unit being connected to the integrated power module and the sideband signal connector, respectively; and the back of the integrated circuit board is provided with multiple high-speed serial interfaces and multiple memory interfaces, the high-speed serial interfaces and the memory interfaces being connected to the computing unit, respectively.

[0066] In another embodiment, the first computing module further includes multiple solid-state hard drives, and the multiple memory interfaces are respectively used to connect the multiple solid-state hard drives, and the memory interfaces are used to realize serial communication between the solid-state hard drives and the computing unit.

[0067] In another embodiment, the memory interface is an EDSFF connector.

[0068] In another embodiment, the terminal device further includes: a second computing module having the same structure as the first computing module; the high-speed serial interface includes a first PCIE×8 connector, and the first computing module and the second computing module are connected via the first PCIE×8 connector.

[0069] In another embodiment, the high-speed serial interface further includes a second PCIE×8 connector, and the second PCIE×8 connector is used to connect to the second terminal device.

[0070] In another embodiment, the high-speed serial interface further includes a first PCIE×16 connector, and the first PCIE×16 connector is used to configure a PCIEx16 device.

[0071] In another embodiment, the high-speed serial interface further includes a second PCIE×16 connector, the second PCIE×16 connector is used to connect to the PCIE Switch unit of the first terminal device, and the PCIE Switch unit of the first terminal device is used to connect to the PCIE Switch unit of the second terminal device.

[0072] In another embodiment, a through hole connected to a system power bus of the first terminal device is provided on the integrated circuit board.

[0073] In another embodiment, the computing unit includes a CPU, and a plurality of OMI interfaces are provided on the CPU, and the plurality of OMI interfaces are respectively connected to the plurality of memory interfaces.

[0074] The terminal device also includes a system management unit and a PCIE Switch unit. A baseboard is provided within the terminal device. Both the system management unit and the PCIE Switch unit are provided on the baseboard. The front of the integrated circuit board in the first computing module is provided toward the baseboard, and the front of the integrated circuit boards in the other computing modules included in the computing device are also provided toward the baseboard. The through-holes on the integrated circuit board are connected to the system power bus of the first terminal device through the baseboard. The sideband signal connectors in the multiple computing modules included in the computing device are all connected to the system management unit, and the second PCIE×16 connector in one or more computing modules included in the computing device is connected to the PCIE Switch unit.

[0075] The terminal device can specifically be a server chassis, a computer chassis, a message transceiver device, or a mobile phone. The terminal devices provided in the embodiment of the present invention can be interconnected with each other, such as the first terminal device and the second terminal device can be connected through the second PCIE×8 connector. At this time, the second PCIE×8 connector in the first terminal device is connected to the second terminal device through an adapter board, that is, the second PCIE×8 connector is connected to the adapter board, and the adapter board is then connected to the second terminal device. The adapter board is used to convert signals, and is used to convert the signal output by the PCIE×8 connector into a signal that supports long-distance transmission. The PCIE×8 connector only supports short-distance signal transmission. Through the setting of the adapter board, long-distance interconnection between terminal devices can be achieved.

[0076] Of course, the first terminal device and the second terminal device can also be interconnected through the PCIE Switch unit therein. In this case, the first terminal device and the second terminal device are relatively close to each other, and the PCIE Switch unit on the bottom board of the first terminal device is connected to the PCIE Switch unit on the bottom board of the second terminal device to achieve close-range interconnection between the terminal devices.

[0077] In a terminal device provided by an embodiment of the present invention, a computing unit, an integrated power module, and a sideband signal connector are arranged on the front side of an integrated circuit board, and multiple high-speed serial interfaces and multiple memory interfaces are arranged on the back side of the integrated circuit board. By arranging the computing unit, the integrated power module, the sideband signal connector, the high-speed serial interfaces, and the memory interfaces on different sides of the integrated circuit board, wiring distances can be minimized, impedance and transmission loss can be significantly reduced, and the problem of long wiring distances and high transmission losses on the computing motherboard when the above-mentioned structure is designed to be entirely coplanar can be solved, thereby more easily meeting the diverse and ever-expanding computing power requirements. Furthermore, arranging the computing unit, the integrated power module, the sideband signal connector, the high-speed serial interfaces, and the memory interfaces on different sides of the integrated circuit board can fully utilize the integrated circuit board, allowing more high-speed serial interfaces and memory interfaces to be arranged on a limited integrated circuit board, thereby reducing the required size and space occupied by the integrated circuit board. Furthermore, when the computing unit is a CPU, by arranging only the computing unit, the integrated power module, and the sideband signal connector on the front side of the integrated circuit board, it is possible to directly solder the CPU BGA to the integrated circuit board, eliminating the CPU socket and improving the integrity of the CPU signal.

[0078] The terminal device provided by the embodiment of the present invention includes various structures of the computing device in any of the above embodiments, which will not be described again here to avoid repetition.

[0079] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0080] Each embodiment in this specification is described in a related manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences between the other embodiments. In particular, the system embodiment is generally similar to the method embodiment, so the description is relatively simple. For related parts, refer to the description of the method embodiment.

[0081] The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention are included in the scope of protection of the present invention.

[0082] The above is a detailed introduction to a computing device and terminal device provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the structure of the present invention and its core ideas. At the same time, for those skilled in the art, according to the ideas of the present invention, there may be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A computing device, applied to a first terminal device, characterized in that: include: a first computing module; The first computing module includes an integrated circuit board, wherein a computing unit, an integrated power module, and a sideband signal connector are provided on the front of the integrated circuit board, wherein the computing unit is connected to the integrated power module and the sideband signal connector respectively, wherein the integrated power module is used to supply power to the computing unit, and the sideband signal connector is used to fan out the low-speed signal of the computing unit; The back of the integrated circuit board is provided with a plurality of high-speed serial interfaces and a plurality of memory interfaces, the high-speed serial interfaces and the memory interfaces are respectively connected to the computing unit, and the memory interfaces are used to realize serial communication between the solid-state drive and the computing unit; The memory interface is an EDSFF connector; The computing unit includes a CPU, and a plurality of OMI interfaces are provided on the CPU. The plurality of OMI interfaces are respectively connected to the plurality of memory interfaces.

2. The computing device according to claim 1, wherein: The first computing module also includes multiple solid-state hard drives, and the multiple memory interfaces are respectively used to connect to the multiple solid-state hard drives.

3. The computing device according to claim 1, wherein: Also includes: A second computing module having the same structure as the first computing module; The high-speed serial interface includes a first PCIE×8 connector, and the first computing module and the second computing module are connected via the first PCIE×8 connector.

4. The computing device according to claim 1, wherein: The high-speed serial interface further includes a second PCIE×8 connector, and the second PCIE×8 connector is used to connect to a second terminal device.

5. The computing device according to claim 1, wherein: The high-speed serial interface further includes a first PCIE×16 connector, and the first PCIE×16 connector is used to configure a PCIEx16 device.

6. The computing device according to claim 1, wherein: The high-speed serial interface further includes a second PCIE×16 connector, which is used to connect to the PCIE Switch unit of the first terminal device, and the PCIE Switch unit of the first terminal device is used to connect to the PCIE Switch unit of the second terminal device.

7. The computing device according to claim 1, wherein: The integrated circuit board is provided with a through hole connected to the system power bus of the first terminal device.

8. A terminal device, characterized in that: The computing device comprises the computing device according to any one of claims 1 to 7.

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