A method for calculating a partial depletion SOI MOSFET body region resistance

Abstract

The application belongs to the technical field of semiconductor integrated circuits, and particularly relates to a calculation method of a bulk resistance of a partially-depleted silicon-on-insulator metal-oxide-semiconductor field effect transistor (SOI MOSFET). According to the structure characteristics of the H-type gate MOSFET, the depletion charge amount generated by the front gate voltage and the back gate voltage in the bulk silicon of the device is solved by using the principle of the capacitive induced charge. Then, according to the source pn junction and the drain pn junction model, the depletion charge of the pn junction in the bulk silicon is obtained. On this basis, a basic bulk multi-charge model is established, and all the residual multi-charge amounts in the bulk are obtained. Then, according to the charge movement law, the bulk silicon resistance model is established, so that the bulk resistance can be quickly and accurately obtained. The model results are highly consistent with the simulation and experimental results. The application has clear physical concept, is easy to calculate, and has high calculation precision, and provides an effective calculation method for extracting the key parameters of the SOI MOSFET.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit technology, specifically a method for calculating the bulk resistance of a partially depleted (PD) silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET). Background Technology

[0002] With the continuous development of integrated circuit technology and the advancement of communication and digital signal processing technologies, high-frequency operating circuits have become a focus of design and research. This requires that the models of devices in the circuit be accurate, fast, and robust enough to meet the needs of circuit simulation under different conditions. SOI MOSFETs are a relatively ideal device, with a process similar to CMOS. However, due to the limited thickness of the bulk silicon, the channel punch-through effect can be well suppressed, improving the subthreshold characteristics of the device. At the same time, the influence of the back gate can adjust the threshold voltage of the device. For this new type of device structure, when the bulk silicon is floating, its potential is prone to change, thus affecting the threshold voltage. Therefore, before practical application of this device, it is necessary to be able to quickly and accurately calculate its key parameters, such as channel potential and threshold voltage, for circuit analysis and simulation.

[0003] Bulk resistance is a crucial parameter affecting the performance of SOI devices. It influences the ability of the bulk contact to control the bulk potential. It is defined as follows: by fabricating electrodes in the bulk region, measuring the current flowing through it under different conditions, and dividing the bulk voltage by the bulk current, the bulk resistance is obtained. Accurate calculation of the bulk resistance is essential for accurately describing the current-voltage characteristics of the device under different bulk biases. Summary of the Invention

[0004] The purpose of this invention is to provide a method for calculating the body resistance of a partially depleted SOI MOSFET that is physically simple, computationally fast, and has an accurate model.

[0005] This invention provides a method for calculating the body resistance of partially depleted SOI MOSFETs. Based on the structural characteristics of H-gate MOSFETs, it utilizes the principle of capacitively induced charge to calculate the depletion charge generated in the bulk silicon by the front and back gate voltages. Then, based on the source pn junction and drain pn junction models, the depletion charge of the pn junction in the bulk silicon is obtained. On this basis, a basic bulk majority carrier (holes for nMOSFETs) charge model is established, and the total amount of remaining majority carrier charge in the bulk region is obtained. Finally, based on the charge movement law, a resistance model of the bulk silicon is established to quickly and accurately obtain the body resistance. The model results are in high agreement with simulation and experimental results.

[0006] The specific steps are as follows.

[0007] (I) First, the majority carrier charge model in the bulk silicon of the PDSOI MOSFET is constructed, given by the following equation:

[0008] Q nbr =qN eff LWt si -Q B (1)

[0009] Among them, Q nbr Where N is the majority carrier charge, q is the electron charge, and N is the electron charge. eff The effective channel doping concentration (including halo doping) is given by W and L, which represent the channel width and length, respectively, and t. si For bulk silicon thickness, Q B The charge in the bulk region is depleted; when a partially depleted SOI device is working, the internal charge is not completely depleted, so it can be assumed that the original total charge in the device is greater than the amount of charge depleted.

[0010] The total amount of charge depletion in the body region caused by each port, Q B Its composition is given by the following formula:

[0011] Q B =Q bf +Q e +Q js +Q jd (2)

[0012] Among them, Q bf It is the top-gate induced charge, Q e It is the back-gate induced charge, Q js and Q jd These are the depletion layer charges of the source junction and the drain junction, respectively; the definitions of each charge are as follows:

[0013] (1) Top grid induced charge:

[0014] Q bf =WLC ox (Vgs -V FB -V bs (3)

[0015] (2) Back grid induced charge:

[0016] Q e =WLC oxb (V es -V fbb -V bs (4)

[0017] Where C ox V is the capacitance per unit area of ​​the top gate oxide layer. gs V is the voltage between the gate and the source. FB V is the top-gate flat-band voltage. bs V is the voltage between the source and the source. es V is the voltage between the substrate and the source. fbb For the back-gate flat-band voltage, C oxb Capacitance of the oxide layer per unit area of ​​the back gate;

[0018] Constructing a source-drain depletion charge model for PDSOI MOSFETs:

[0019] (1) Source junction depletion charge:

[0020]

[0021] Among them, A sd For the source junction area, A sd =Wt si , ε si V is the dielectric constant of silicon. in For the built-in potential, N sd Source / drain doping concentration;

[0022] (2) Drain junction depletion of charge:

[0023]

[0024] Among them, V ds This represents the voltage between the drain and source.

[0025] (II) Constructing an analytical model of resistance between volume sources

[0026] The source and the body are connected by a pn junction, and the current density is typically:

[0027]

[0028] Among them, D p and D n L represents the hole and electron diffusion coefficients, respectively. p and Ln For the diffusion length, W p and W n For the length of the knot, The hole concentration at equilibrium in an n-type semiconductor. V represents the electron concentration at equilibrium for a p-type semiconductor. J This is an external bias voltage.

[0029] For the problem we are studying, the pn junction length is very short, i.e., W n <<L p W p <<L n The above formula can be approximated as:

[0030]

[0031] The current is:

[0032]

[0033] When the injected minority carrier concentration reaches or exceeds the majority carrier concentration, the large injection effect must be considered. In this case, the diffusion coefficient increases by a factor of 1, and the ideality factor m is increased. The above formula is then modified as follows:

[0034]

[0035] The value of m is between 1 and 2, and D′ p =2D p ,D′ n =2D n .

[0036] Therefore, the resistance between the source and the body is:

[0037]

[0038] Among them, V bs I is the voltage between the source and the body. bs The current between the body sources.

[0039] (III) Improving the Fitting Effect

[0040] For the pn junction between the source / body and drain / body, due to LDD and Halo doping, its built-in potential is difficult to describe accurately using ordinary analytical models. This invention adds a fitting parameter to the standard formula, given by the following equation:

[0041]

[0042] Where, n i f5 represents the intrinsic carrier concentration, and f5 is the fitting parameter.

[0043] (iv) For an H-type gate structure, the resistance generated by the movement of majority carriers (holes for nMOSFETs) in the bulk silicon from the front end to the back end along the channel width direction is given by the following formula:

[0044]

[0045] Where, μ B Q represents the effective mobility for multiple carriers. nbr The majority charge is given by equation (1).

[0046] (v) The aforementioned body resistance is modeled for the majority carrier effective mobility as follows: Considering that gate voltage and drain voltage will cause a decrease in carrier mobility, the effective mobility is expressed as:

[0047]

[0048] Here, f6 and f7 are two fitting parameters, which can be integers between 5 and 20. μ0 is the low-field mobility, which is related to the doping concentration. For holes, μ0 is typically 75 cm⁻¹. 2 / Vs.

[0049] (vi) The total bulk resistance can be considered as the resistance R between the front and rear ends of the bulk silicon. bW and the resistance R between the front end and the source bs By connecting them in parallel, we finally obtain:

[0050]

[0051] The method of this invention has a clear physical concept, is easy to calculate, and has high calculation accuracy, providing an efficient calculation method for extracting key parameters of SOI MOSFETs. Attached Figure Description

[0052] Figure 1 This is a cross-sectional view of the structure simulated in TCAD.

[0053] Figure 2 This is a bird's-eye view of the structure simulated in TCAD.

[0054] Figure 3 This is a front view of the device structure.

[0055] Figure 4 This is a schematic diagram of charge distribution in the bulk silicon of the device.

[0056] Figure 5 This is a top view of the H-type gate device structure.

[0057] Figure 6 This is a flowchart of the method of the present invention.

[0058] Figure 7 The graph shows a comparison between the model results and the simulation and experimental results.

[0059] Figure 8 This is a comparison chart between the model results and the simulation results. Detailed Implementation

[0060] This invention compares the numerical calculation results of the analytical model with the experimental results and TCAD simulation results.

[0061] exist Figure 7 In this paper, we compared the relationship between the bulk resistance and the bulk region bias voltage under different back-gate bias voltages. The dots represent experimental results, the solid lines represent model results, and the dashed lines represent simulation results (for calibrating simulation tools). The experiments used H-gate SOI MOSFETs, and the device bias voltages were: V... gs = -0.3V,V DS =0V,V ES Flat band voltages V for the front and rear gates, respectively, are 0V and -10V. fb =V fbb = -1V. Device dimensions: width W = 3μm, length L = 65nm, back gate oxide thickness t box =282nm, front gate oxide layer thickness is t fox =5nm, bulk silicon thickness t si =45nm, channel doping concentration N eff =1.3×10 18 cm -3 The source / drain doping concentration is 3×10 20 cm -3 W n =20nm,W p =65nm. For silicon material parameters: D n =25cm 2 / s,D p =10cm 2 / s,n i =1.5×10 10 cm -3 μ0=75cm 2 / Vs,T=300K. The seven fitting parameters in the model used were: f1=0.57, f2=0.12, f3=0.02, f4=0.786, f5=0.2, f6=9, f7=6. It is easy to see that the model results agree very well with the experimental results.

[0062] In addition, to calibrate the simulation tools, we simulated this device, and we can see that the simulation results match the experimental results very well.

[0063] Figure 8The relationship between body resistance and drain voltage under different gate voltages was compared. The dots represent simulation results, and the solid line represents model results. It can be seen that the analytical model and simulation results agree very well. The device bias voltages used in the simulation were: V... gs =-0.5,0,0.5,1V,V ES The flat band voltage V of the front and rear gates is 0V. fb =V fbb = -1V. Device dimensions: width W = 2μm, length L = 200nm, back gate oxide thickness t box =200nm, front gate oxide layer thickness is t fox = 5.3nm, bulk silicon thickness t si =250nm, channel doping concentration N eff =3.3×10 17 cm -3 The source / drain doping concentration is 6×10 20 cm -3 W n =20nm,W p =65nm. Regarding the selection of silicon material parameters, and... Figure 7 The same as in the model. The values ​​of the seven fitting parameters used in the model are: f1 = 0.01, f2 = 0.4, f3 = 0.01, f4 = 0.8, f5 = 0.3, f6 = 15, f7 = 19.

[0064] As can be seen, this invention can quickly and accurately extract the bulk resistance and related key parameters of SOI MOSFETs, enabling rapid verification of integrated circuit functional designs and providing an effective method for extracting bulk resistance parameters for circuit optimization design and electrical behavior simulation.

Claims

1. A method for calculating the body resistance of a partially depleted SOI MOSFET, characterized in that, The specific steps are as follows: (a) First, calculate the body charge model expression for the PDSOI MOSFET, which is the total body depletion charge Q caused by each port. B : ， （1） in, It is the top gate induced charge. It is back-gate induced charge. These are the depletion layer charges of the source junction and the drain junction, and their definitions are as follows: (1) Top grid induced charge: （2） (2) Back grid induced charge: （3） Where W is the device width, L is the device length, and C is the device width. ox V is the capacitance per unit area of ​​the top gate oxide layer. gs V is the voltage between the gate and the source. FB V is the top-gate flat-band voltage. bs V is the voltage between the source and the source. es V is the voltage between the substrate and the source. fbb For the back-gate flat-band voltage, C oxb Capacitance of the oxide layer per unit area of ​​the back gate; (3) Source junction depletion charge: （4） Among them, A sd For the source junction area, , t si For the bulk silicon thickness, ε si V is the dielectric constant of silicon. in For the built-in potential, N eff For the effective doping concentration of the channel, N sd Where q is the source / drain doping concentration, and q is the electron charge. (4) Drain junction depletes charge: （5） Among them, V ds This is the voltage between the drain and source; (ii) Calculate the total charge of all carriers providing the current in the body region. : ， （6） (iii) Based on the definition of resistance, obtain the resistance R generated when these charge carriers move along the channel width direction. bW : ，（7） Where, µ B The effective mobility of charge carriers.

2. The calculation method according to claim 1, characterized in that, In step (iii), the resistance between the source and the source is considered. A model of the resistance of a pn junction is established, and the final total bulk resistance is: ，（8） It is composed of the resistance R along the width of the channel. bW With the body source resistance R bs It is obtained by connecting them in parallel.

3. The calculation method according to claim 1, characterized in that, In the volume charge model, each charge term is multiplied by a fitting parameter; the four charges together form: , , Multiply by the fitting parameters respectively, i.e.: ，（9） Where f1, f2, f3, and f4 are the fitting parameters between 0 and 1.

4. The calculation method according to claim 1, characterized in that, The mobility µ of the bulk resistance B The expression is modified as follows: Considering that gate voltage and drain voltage will cause a decrease in carrier mobility, the mobility is modeled as follows: ， （10） Where f6 and f7 are two fitting parameters, It has a low field mobility.

5. The calculation method according to claim 2, characterized in that, The resistance between the sources The expression for is given by the following formula: （11） Among them, V bs I is the voltage between the source and the body. bs For the current between the body source, W n W and Wp are the lengths of the n-region and p-region of the pn junction, respectively. The hole concentration at equilibrium in an n-type semiconductor. Let be the electron concentration at equilibrium for a p-type semiconductor, and m be the ideality factor, whose value is between 1 and 2. Where V is Boltzmann's constant, T is temperature, and V is temperature. J This is the applied voltage; and These are twice the hole and electron diffusion coefficients, respectively.

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