Control device, method, driving device and apparatus for image display timing

Abstract

The application provides a kind of image display timing control device, method and driving device and equipment, it is related to display technical field.The device includes: determination module, for determining whether the length of the last row of current frame image meets preset condition;Control module, for in the case where determination module determines that the length of the last row of current frame image does not meet preset condition, control the timing of current frame image continues to output until the length of the last row of current frame image meets preset condition, output the vertical synchronization signal and horizontal synchronization signal corresponding to next frame image.The application can automatically adjust the display timing of each frame image in the process of image display, obtain the display timing that meets the specification requirements of display panel, ensure the image display quality while reducing the development cost of chip related to image display.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular, the present application relates to a kind of image display timing control device, method and driving device and equipment. BACKGROUND

[0002] In the development of image processing related chip, source clock is derived from player, display clock is derived from phase-locked loop, and the situation that source clock frequency and display clock frequency are inconsistent is often encountered.When display picture needs to be outputted by frame rate fixed proportion, source vertical synchronization signal (source Vsync, wherein, Vsync is the abbreviation of Vertical synchronization) is needed to control the timing of display panel, therefore, the length of the last line of image frame can be less than the number of sub-pixels in horizontal direction (htotal) of display panel, so as to cause the length of the last line to not meet the specification requirement range of display panel.

[0003] In the prior art, display clock frequency is adjusted according to source clock frequency, or the number of sub-pixels in horizontal direction of display panel is adjusted within the specification requirement range of display panel, to obtain timing that meets the specification requirement of display panel.But limited by whether phase-locked loop is adjustable and the precision, stability of phase-locked loop and the size of htotal range of display panel specification requirement, developers usually spend a lot of time and effort when manually adjusting, and the development cost is high. SUMMARY

[0004] Embodiments of the present application provide a kind of image display timing control device, method and driving device and equipment, to solve at least one technical problem in the prior art.

[0005] According to the first aspect of the embodiments of the present application, a kind of image display timing control device is provided, comprising:

[0006] Determination module, for determining whether the length of the last line of current frame image meets preset condition;

[0007] Control module, for in the case where the determination module determines that the length of the last line of current frame image does not meet the preset condition, the timing of the current frame image is controlled to continue output, until the length of the last line of current frame image meets the preset condition, output the vertical synchronization signal and horizontal synchronization signal corresponding to the next frame image.

[0008] In a possible implementation, the determining module is specifically configured to: when the length of the last row of the current frame image is within a range of a length of each row that can be received by the screen, or the length of the last row of the current frame image is equal to a length of the current frame in the horizontal direction, determine that the length of the last row of the current frame image satisfies the preset condition; otherwise, determine that the length of the last row of the current frame image does not satisfy the preset condition.

[0009] In another possible implementation, the control module is further configured to: in a case where the determining module determines that the length of the last row of the current frame image satisfies the preset condition, control the vertical synchronization signal and the horizontal synchronization signal corresponding to the next frame image to be directly output.

[0010] According to a second aspect of the embodiment of the present application, a control method of image display timing is provided, which comprises:

[0011] In the process of displaying the received images frame by frame, the following operations are performed on each frame image:

[0012] determining whether a length of a last row of a current frame image satisfies a preset condition;

[0013] if the length of the last row of the current frame image does not satisfy the preset condition, controlling timing of the current frame image to continue to be output until the length of the last row of the current frame image satisfies the preset condition, and outputting a vertical synchronization signal and a horizontal synchronization signal corresponding to the next frame image.

[0014] In a possible implementation, the determining whether the length of the last row of the current frame image satisfies the preset condition comprises:

[0015] when the length of the last row of the current frame image is within a range of a length of each row that can be received by the screen, or the length of the last row of the current frame image is equal to a length of the current frame in the horizontal direction, determining that the length of the last row of the current frame image satisfies the preset condition;

[0016] otherwise, determining that the length of the last row of the current frame image does not satisfy the preset condition.

[0017] In another possible implementation, the range of the length of each row that can be received by the screen is determined based on a display panel specification requirement.

[0018] In another possible implementation, the method further comprises:

[0019] if the length of the last row of the current frame image satisfies the preset condition, directly outputting the vertical synchronization signal and the horizontal synchronization signal corresponding to the next frame image.

[0020] According to a third aspect of the embodiments of the present application, a driving device for a display panel is provided, comprising a timing control unit and a display driving unit, wherein,

[0021] The timing control unit is configured to, in a case where the length of the last row of the current frame image does not satisfy a preset condition, control the timing of the current frame image to continue outputting until the length of the last row of the current frame image satisfies the preset condition, and output the vertical synchronization signal and the horizontal synchronization signal corresponding to the next frame image as signals required for the display driving unit to perform control;

[0022] The display driving unit is configured to control the image display in the display panel according to the signals received from the timing control unit.

[0023] In a possible implementation, the timing control unit is further configured to, in a case where the length of the last row of the current frame image satisfies the preset condition, directly output the vertical synchronization signal and the horizontal synchronization signal corresponding to the next frame image as the signals required for the display driving unit to perform control.

[0024] According to a fourth aspect of the embodiments of the present application, a display device is provided, comprising the driving device of the display panel in any one of the third aspect.

[0025] According to a fifth aspect of the embodiments of the present application, an electronic device is provided, comprising a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the method in any one of the second aspect.

[0026] The technical scheme provided by the embodiments of the present application has the following beneficial effects:

[0027] In the process of image display, the display timing of each frame of image can be automatically adjusted to obtain a display timing that meets the specification requirements of the display panel, thereby ensuring the image display quality. By automatically adjusting the display timing, the problem of time and effort caused by the limitation of whether the phase-locked loop is adjustable and its accuracy and stability, and the range of the number of sub-pixels in the horizontal direction required by the specification of the display panel is avoided, the development efficiency is improved, and the development cost of the chip related to image display is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical schemes in the embodiments of the present application, the drawings required to be used in the description of the embodiments of the present application will be briefly introduced.

[0029] Figure 1A schematic block diagram of a display device provided for an embodiment of the present application;

[0030] Figure 2 A schematic diagram of an image display timing provided for an embodiment of the present application;

[0031] Figure 3 A schematic block diagram of a control device of an image display timing provided for an embodiment of the present application;

[0032] Figure 4 A flowchart of a control method of an image display timing provided for an embodiment of the present application;

[0033] Figure 5 A structural schematic diagram of an electronic device provided for an embodiment of the present application. DETAILED DESCRIPTION

[0034] Embodiments of the present application will be described below with reference to the accompanying drawings. It should be understood that the embodiments described below in conjunction with the drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions of the embodiments of the present application.

[0035] In order to make the purpose, technical solutions and advantages of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

[0036] In the development of image processing related chips (IC and FPGA), the source clock is derived from the player, and the display clock is derived from the phase-locked loop. The source clock frequency and the display clock frequency are often inconsistent. When the display picture needs to be synchronized by frame or output at a fixed ratio of frame rate such as FreeSync, the source vertical synchronization signal (source Vsync) is needed to control the display timing of the display panel. Therefore, the length of the last row of the image frame may be less than the number of sub-pixels in the horizontal direction (htotal) of the display panel, resulting in a situation that the length of the last row does not meet the specification requirements of the display panel.

[0037] In the existing solution, by adjusting the display clock frequency or htotal to meet the timing requirements of the display panel specifications, it is limited by whether the phase-locked loop (PLL) is adjustable, the accuracy, stability of the PLL and the size of the htotal range required by the display panel specifications, which will consume a lot of time and effort, resulting in high development cost, and even cannot adjust the compliant display timing, affecting normal image display.

[0038] FreeSync is a technology that uses the DisplayPort interface for adaptive synchronization to achieve a dynamic refresh rate. This technology allows the refresh rate of a FreeSync-equipped monitor to synchronize with the user's graphics card frame rate, reducing input lag, stuttering, screen tearing, and ghosting.

[0039] Figure 1 This is a schematic block diagram of a display device according to an embodiment of this application. Figure 1 As shown, the display device includes: a display panel driving device 1, a video signal processing circuit 2, and an IP conversion circuit 3, as well as a display panel 4. When the video signal processing circuit 2 receives a video signal from an external source, it performs predetermined signal processing on the video signal. The IP conversion circuit 3 performs a conversion from interlaced to progressive signal and sends the converted signal to the timing control unit 11 in the driving device 1. Therefore, in the display device, the video signal processing circuit 2 and the IP conversion circuit 3 are equivalent to a "signal processing unit" configured to transmit externally input video signals to the timing control unit 11.

[0040] The driving device 1 for the display panel includes a display driving unit (including a data driving unit 12 and a scan driving unit 13) and a timing control unit 11, wherein the timing control unit 11 is configured to output various signals required for image display in the display panel 4. The timing control unit 11 generates and provides signals to the display driving unit. The display driving unit is configured to control the image display in the display panel 4 according to the signals received from the timing control unit 11.

[0041] Specifically, the timing control unit 11 receives a video signal from the signal processing unit, converts the transmission rate of the video signal to synchronize with the display timing on the display panel 4, and provides the resulting signal as an image data signal for specifying the image display content on the display panel 4 to the data driving unit 12.

[0042] The timing control unit 11 provides the data driving unit 12 with a clock signal CLK, a vertical synchronization signal Vsync, and a horizontal synchronization signal Hsync as synchronization signals for the image data signal. That is, the timing control unit 11 is configured to provide the data driving unit 12 with at least the horizontal synchronization signal Hsync and the vertical synchronization signal Vsync as signals required for the data driving unit 12 to perform control.

[0043] The timing control unit 11 also provides a signal to the scan drive unit 13. The specific content of the signal can be implemented using relevant technologies, which will not be elaborated here for the sake of brevity.

[0044] The display panel 4 has a plurality of display elements arranged in a matrix. The display panel 4 displays an image using the display elements. The display elements can be self-luminous organic EL elements, or can be transmissive or reflective liquid crystal elements. However, the display elements are not limited thereto; they can be any other display elements (such as self-luminous elements by discharge light emission), as long as they can constitute a display.

[0045] The data drive unit 12 causes the display panel 4 to display an image by supplying a voltage and a current to each display element constituting the display panel 4. Here, the amount of the voltage and the current corresponds to an image data signal for specifying the image content to be displayed on the display panel 4. When the display panel 4 is configured to receive a constant current at each display element, the data drive unit 12 performs grayscale display by pulse width modulation. That is, the data drive unit 12 controls the image display operation in the display panel 4 by supplying a voltage and a current to each display element.

[0046] Like the data drive unit 12, the scan drive unit 13 controls the image display in the display panel 4. The scan drive unit 13 is configured to perform line sequential scanning in synchronization with the output of the data drive unit 12.

[0047] The data drive unit 12 and the timing control unit 11 can be constructed as separate substrates. Signal transmission between the data drive unit 12 and the timing control unit 11 is generally performed using a high-speed data multiplexing differential signal transmission system, such as a low voltage differential signaling system or a low swing differential signaling system.

[0048] The length of each line under the standard timing is htotal (the number of subpixels in the horizontal direction of the display panel), and there are vtotal lines (the number of subpixels in the vertical direction of the display panel) in one frame, so the length of each frame is vtotal*htotal; there is an hsync_out output at the beginning of each line, and there is a vsync_out output at the beginning of each frame.

[0049] The present application adjusts the non-standard timing, such as the last line of each frame being shorter than the other lines, and the length of the last line not meeting the range required by the display panel specifications, i.e. the length of the current frame is (vtotal-1)*htotal+lastline_htotal. The method of the present application embodiment can adjust the last line of the current frame to meet the display panel specifications.

[0050] The following Figure 2 Taking a frame rate of 1:1 as an example, the schematic diagrams before and after timing adjustment using the image display timing control scheme provided by the present application are given. As shown in Figure 2As shown, the last_line_len in the original timing does not meet the specification requirements, and the last_line_len_0, last_line_len_1, …, last_line_len_N in the timing after adjustment can all meet the specification requirements.

[0051] Specifically, the timing adjustment process is as follows:

[0052] The timing control unit 11, after receiving the source Vsync_in and before preparing to output the Vsync_out, first determines whether the length of the last line of the current frame (Current_line_len) meets the display panel specification requirements, and the judgment condition formula is as follows:

[0053] (Current_line_len>=reg_lastline_low_thr) and (Current_line_len<=reg_lastline_high_thr); or,

[0054] (Current_line_len==reg_htotal)

[0055] Among them, the minimum length of each line that the screen can receive reg_lastline_low_thr, the maximum length of each line that the screen can receive reg_lastline_high_thr, and the length of the current frame in the horizontal direction reg_htotal can all be configured.

[0056] It should be noted that the above lengths all include the length of the data and the blank length. reg_lastline_low_thr, reg_lastline_high_thr and reg_htotal are limited by the display panel specification, and the values of different manufacturers or batches are different.

[0057] When the Current_line_len meets the condition, the timing control unit 11 outputs the Vsync_out and Hsync_out corresponding to the next frame immediately; when the condition is not met, the current frame continues the current line timing output of the current frame by means of the subsequent frame until the length of the current line meets the condition and then the Vsync_out and Hsync_out corresponding to the next frame are output. Similarly, after receiving the Vsync_in of the next frame, it is judged whether the length of the current line meets the condition according to the above formula, if it meets, then the Vsync_out and Hsync_out corresponding to the next frame can be output, otherwise the loan to the subsequent frame is continued, and so on. Finally, it is ensured that the lastline_len_X corresponding to each frame output by the Display timing generator meets the above judgment formula, thereby meeting the display panel specification requirements.

[0058] For example: the Panel specification requirement is 5*10, the length of the first frame is 4*10+9, that is, the number of sub-pixels of the 5th row is 9, the length of the second frame is 4*10+8, the length of the third frame is 4*10+8, …, and the length of the Nth frame is 4*10+9. Then: when outputting the timing of each row of the first frame, the number of sub-pixels of the 5th row is 9, which is less than the specification requirement of 10, therefore, 1 sub-pixel needs to be borrowed from the second frame for the timing output of the 5th row, and then the Vsync_out and Hsync_out corresponding to the second frame are output. At this time, the Vsync_out and Hsync_out corresponding to the second frame are delayed, and the length of the second frame is 4*10+7. When outputting the timing of each row of the second frame, the number of sub-pixels of the 5th row is 7, which is less than the specification requirement of 10, therefore, 3 sub-pixels need to be borrowed from the third frame for the timing output of the 5th row, and then the Vsync_out and Hsync_out corresponding to the third frame are output. In this way, the Nth frame is output.

[0059] It should be noted that the process of borrowing sub-pixels is reflected in the last two rows of each frame. If the length (number of sub-pixels) to be borrowed from the previous frame is greater than the length of the last row of the current frame, the length of the second last row of the current frame will be borrowed to the previous frame.

[0060] Since the previous N frames are borrowed frame by frame, the vertical length vtotal of the N+1 frame will finally become vtotal-1, that is, the N+1 frame will have one less row, which is within the acceptable range of the display. Therefore, the scheme of the embodiment of the application is applicable to the image display timing of each frame.

[0061] It should be further noted that the scheme of the embodiment of the application is not limited to 1:1 frame rate, and can also be applied to other frame rates. Figure 2The timing shown in the figure is related to the frame rate. The implementation process of the control scheme provided in the embodiments of the present application is not limited to the frame rate, that is, the implementation process of the control scheme provided in the embodiments of the present application is the same for any frame rate.

[0062] The frame rate is the frequency (rate) at which a bitmap image appears on a display in units of frames. In simple terms, it is the number of frames displayed in one second. 30 frames per second means 30 frames are displayed in one second, and 60 frames per second means 60 frames are displayed in one second.

[0063] Figure 3 A flowchart of a control method of an image display timing provided in the embodiments of the present application is shown in the figure. As shown in the figure, the method comprises the following steps. Figure 3

[0064] In the process of displaying the received image frame by frame, the following operations are performed on each frame of image:

[0065] S101, determining whether the length of the last row of the current frame of image meets a preset condition.

[0066] S102, if the length of the last row of the current frame of image does not meet the preset condition, controlling the timing of the current frame of image to continue to output until the length of the last row of the current frame of image meets the preset condition, and outputting the vertical synchronization signal and the horizontal synchronization signal corresponding to the next frame of image.

[0067] By using the method of the embodiment, the display timing of each frame of image can be automatically adjusted in the process of image display, so that the display timing meeting the specification requirements of the display panel is obtained, and the problems of time and effort caused by the limitation of whether the phase-locked loop is adjustable and its accuracy and stability, and the range of the number of sub-pixels in the horizontal direction required by the specification of the display panel are avoided, the development efficiency is improved, and the development cost of the chip related to image display is reduced.

[0068] In this embodiment, the current frame of image is a frame of image being processed.

[0069] In an implementable scheme of the present application, S101 can specifically comprise:

[0070] When the length of the last row of the current frame of image is within the range of the length of each row that can be received by the screen, or the length of the last row of the current frame of image is equal to the length of the current frame in the horizontal direction, it is determined that the length of the last row of the current frame of image meets the preset condition.

[0071] Otherwise, it is determined that the length of the last row of the current frame of image does not meet the preset condition. ​

[0072] That is, if the length of the last row of a frame image is within the range of the length of each row receivable by the screen, or equal to the length of the current frame in the horizontal direction, the condition is met, otherwise the condition is not met.

[0073] In the above embodiment, the range of the length of each row receivable by the screen is determined based on display panel specification requirements.

[0074] In another implementable solution of the present application, the above method can further include:

[0075] S103, if the length of the last row of the current frame image meets the preset condition, directly output the vertical synchronization signal and the horizontal synchronization signal corresponding to the next frame image.

[0076] That is, in this embodiment, if the length of the last row of a frame image is within the range of the length of each row receivable by the screen, or equal to the length of the current frame in the horizontal direction, the vertical synchronization signal and the horizontal synchronization signal corresponding to the next frame image are directly output.

[0077] In the above embodiment, the length of the current frame in the horizontal direction is the number of sub-pixel points in the horizontal direction of the current frame.

[0078] Figure 4 A structural schematic diagram of an image display timing control device provided by an embodiment of the present application is shown in FIG. 1. As shown in the figure, the device includes a determination module 201 and a control module 202, wherein, Figure 4

[0079] The determination module 201 is configured to determine whether the length of the last row of the current frame image meets the preset condition. The control module 202 is configured to, in the case that the determination module 201 determines that the length of the last row of the current frame image does not meet the preset condition, control the timing of the current frame image to continue outputting until the length of the last row of the current frame image meets the preset condition, and output the vertical synchronization signal and the horizontal synchronization signal corresponding to the next frame image.

[0080] ​With the device of the embodiment, the control module controls the timing of the current frame image to continue to be output until the length of the last row of the current frame image meets the preset condition, and then outputs the vertical synchronization signal and the horizontal synchronization signal corresponding to the next frame image, so that the display timing of each frame image can be adjusted in the process of image display, and the display timing meeting the specification requirement of the display panel is obtained, and the image display quality is ensured. Through automatic adjustment of the display, the problem of time and effort caused by the limitation of whether the phase-locked loop is adjustable and its accuracy and stability, and the range of the number of sub-pixels in the horizontal direction required by the specification of the display panel is avoided, the development efficiency is improved, and the development cost of the chip related to the image display is reduced.

[0081] In some embodiments, the determination module 201 is specifically configured to determine that the length of the last row of the current frame image meets the preset condition when the length of the last row of the current frame image is within the range of the length of each row that the screen can receive, or the length of the last row of the current frame image is equal to the length of the current frame in the horizontal direction; otherwise, it is determined that the length of the last row of the current frame image does not meet the preset condition.

[0082] In the above embodiment, the range of the length of each row that the screen can receive is determined based on the specification requirement of the display panel.

[0083] In this embodiment, the range of the length of each row that the screen can receive determined based on the specification requirement of the display panel, or the length of the current frame in the horizontal direction is used as the preset condition, and the image display timing that does not meet the preset condition is adjusted, so that the obtained display timing can meet the specification requirement of the display panel.

[0084] In other embodiments, the control module 202 is further configured to control the vertical synchronization signal and the horizontal synchronization signal corresponding to the next frame image to be directly output when the determination module 201 determines that the length of the last row of the current frame image meets the preset condition.

[0085] The embodiments of the present application also provide a driving device for a display panel, which comprises a timing control unit and a display driving unit, wherein,

[0086] The timing control unit is configured to, in a case where the length of the last row of the current frame image does not satisfy the preset condition, control the timing of the current frame image to continue outputting until the length of the last row of the current frame image satisfies the preset condition, and output the vertical synchronization signal and the horizontal synchronization signal corresponding to the next frame image as signals required by the display driving unit for performing control. The display driving unit is configured to control the image display in the display panel according to the signals received from the timing control unit.

[0087] It should be noted that the structure of the driving device in this embodiment can refer to the structure of the driving device 1 of the display panel in Figure 1

[0088] In one possible implementation, the timing control unit is specifically configured to determine that the length of the last row of the current frame image satisfies the preset condition when the length of the last row of the current frame image is within the range of the length of each row that can be received by the screen, or the length of the last row of the current frame image is equal to the length of the current frame in the horizontal direction; otherwise, it is determined that the length of the last row of the current frame image does not satisfy the preset condition.

[0089] In another possible implementation, the timing control unit is further configured to, in a case where the length of the last row of the current frame image satisfies the preset condition, directly output the vertical synchronization signal and the horizontal synchronization signal corresponding to the next frame image as signals required by the display driving unit for performing control.

[0090] The display device provided in the embodiments of the present application comprises the driving device of the display panel in the above embodiments.

[0091] It should be noted that the division of units in the embodiments of the present application is illustrative, and is only a logical functional division. In actual implementation, there can be another division manner. In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can be physically present alone, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0092] ​If the integrated unit is implemented in the form of a software function unit and sold or used as an independent product, it can be stored in a processor-readable storage medium. Based on such an understanding, the technical solutions of the present application essentially or in other words the part of the prior art that contributes to the present application or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to perform all or part of the steps of the methods of the various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0093] The embodiments of the present application also provide an electronic device, including a memory, a processor and a computer program stored in the memory, and the processor executes the computer program to implement the steps of the image display timing control method provided by the embodiments of the present application. Compared with the prior art, the method can automatically adjust the display timing of each frame of image in the process of image display, obtain the display timing meeting the specification requirements of the display panel, and ensure the image display quality. By automatically adjusting the display timing, the problem of time and effort caused by the limitation of whether the phase-locked loop is adjustable and its accuracy and stability, and the range size of the number of sub-pixels in the horizontal direction required by the display panel specification is avoided when the display clock frequency or the number of sub-pixels in the horizontal direction of the display panel is adjusted to meet the specification requirements of the display panel, the development efficiency is improved, and thus the development cost of the chip related to image display is reduced.

[0094] In an optional embodiment, an electronic device is provided, as shown in Figure 5 The electronic device 30 shown in Figure 5 The electronic device 30 shown in

[0095] The processor 301 can be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array) or other programmable logic device, transistor logic device, hardware component, or any combination thereof. It can implement or execute various exemplary logical blocks, modules and circuits described in conjunction with the disclosure. The processor 301 can also be a combination of computing functions, such as one or more microprocessor combinations, combinations of DSP and microprocessor, etc.

[0096] The bus 302 can include a path for transmitting information between the above-mentioned components. The bus 302 can be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The bus 302 can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 5 Only one thick line is used in the figure, but it does not mean that there is only one bus or only one type of bus.

[0097] The memory 303 can be a ROM (Read Only Memory) or other type of static storage device that can store static information and instructions, a RAM (Random Access Memory) or other type of dynamic storage device that can store information and instructions, an EEPROM (Electrically Erasable Programmable Read Only Memory), a CD-ROM (Compact Disc Read Only Memory) or other optical disk storage, an optical disk storage (including a compact disk, a laser disk, an optical disk, a digital versatile disk, a Blu-ray disk, etc.), a magnetic disk storage medium, other magnetic storage device, or any other medium capable of carrying or storing computer programs and capable of being read by a computer, without limitation.

[0098] The memory 303 is configured to store a computer program for implementing the embodiments of the present application, and the processor 301 is configured to control the execution of the computer program stored in the memory 303. The processor 301 is configured to execute the computer program stored in the memory 303 to implement the steps of the foregoing file packaging method embodiments, or the steps shown in the file unpacking method embodiments.

[0099] The embodiments of the present application provide a computer readable storage medium, and the computer readable storage medium stores a computer program. The computer program is executed by a processor to implement the steps and corresponding contents of the foregoing image display timing control method embodiments.

[0100] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. In addition, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage and optical storage, etc.) containing computer-usable program code.

[0101] It should be understood that, although the flowcharts of the embodiments of the present application indicate the respective operation steps by arrows, the implementation order of the steps is not limited to the order indicated by the arrows. Unless otherwise specified herein, in some implementation scenarios of the embodiments of the present application, the implementation steps in each flowchart can be executed in other orders as required. In addition, part or all of the steps in each flowchart can include multiple sub-steps or multiple stages based on the actual implementation scenario. Part or all of the sub-steps or stages can be executed at the same time, and each of the sub-steps or stages can also be executed at different times. In the scenario where the execution times are different, the execution order of the sub-steps or stages can be flexibly configured as required, and the embodiments of the present application do not limit this.

[0102] The above is only an optional implementation manner of some implementation scenarios of the present application. It should be pointed out that, for those skilled in the art, other similar implementation manners based on the technical concept of the present application can also be adopted without departing from the technical concept of the present application, and these also belong to the protection scope of the embodiments of the present application.

Claims

1. An apparatus for controlling timing of image display, characterized by comprising: The method comprises the following steps: determining whether the length of the last row of the current frame image meets a preset condition; controlling the time sequence of the current frame image to continue outputting until the length of the last row of the current frame image meets the preset condition, and outputting the vertical synchronization signal and the horizontal synchronization signal corresponding to the next frame image; wherein the control of the time sequence of the current frame image to continue outputting comprises: controlling the time sequence of the last row of the current frame image to continue outputting by means of the sub-pixels in the subsequent image frame.

2. The apparatus of claim 1, wherein, The determination module is specifically configured to: when the length of the last row of the current frame image is within the range of the length of each row that can be received by the screen, or the length of the last row of the current frame image is equal to the length of the current frame in the horizontal direction, determine that the length of the last row of the current frame image meets the preset condition; otherwise, determine that the length of the last row of the current frame image does not meet the preset condition.

3. The apparatus of claim 1 or 2, wherein, The control module is further configured to: when the determination module determines that the length of the last row of the current frame image meets the preset condition, control the vertical synchronization signal and the horizontal synchronization signal corresponding to the next frame image to be directly outputted.

4. A method of controlling timing of image display, characterized by, The method comprises the following steps: in the process of displaying the received image frame by frame, the following operations are performed on each frame image: determining whether the length of the last row of the current frame image meets a preset condition; if the length of the last row of the current frame image does not meet the preset condition, controlling the time sequence of the current frame image to continue outputting until the length of the last row of the current frame image meets the preset condition, and outputting the vertical synchronization signal and the horizontal synchronization signal corresponding to the next frame image; wherein the control of the time sequence of the current frame image to continue outputting comprises: controlling the time sequence of the last row of the current frame image to continue outputting by means of the sub-pixels in the subsequent image frame.

5. The method of claim 4, wherein, The determination of whether the length of the last row of the current frame image meets the preset condition comprises: when the length of the last row of the current frame image is within the range of the length of each row that can be received by the screen, or the length of the last row of the current frame image is equal to the length of the current frame in the horizontal direction, determining that the length of the last row of the current frame image meets the preset condition; otherwise, determining that the length of the last row of the current frame image does not meet the preset condition.

6. The method according to claim 4 or 5, characterized in that, The method further comprises: if the length of the last row of the current frame image meets the preset condition, directly outputting the vertical synchronization signal and the horizontal synchronization signal corresponding to the next frame image.

7. A driving device of a display panel, characterized by comprising: The method comprises the following steps: a time sequence control unit and a display driving unit, wherein The timing control unit is configured to, in a case where the length of the last row of the current frame image does not satisfy a preset condition, control the timing of the current frame image to continue outputting until the length of the last row of the current frame image satisfies the preset condition, and output a vertical synchronization signal and a horizontal synchronization signal corresponding to a next frame image as signals required by the display driving unit for performing control; The display driving unit is configured to control image display in a display panel according to the signals received from the timing control unit; The timing control unit is configured to, in a case where the length of the last row of the current frame image does not satisfy a preset condition, control the timing of the current frame image to continue outputting until the length of the last row of the current frame image satisfies the preset condition, and output a vertical synchronization signal and a horizontal synchronization signal corresponding to a next frame image as signals required by the display driving unit for performing control; 8. The driving apparatus of the display panel according to claim 7, wherein The timing control unit is configured to, in a case where the length of the last row of the current frame image does not satisfy a preset condition, control the timing of the current frame image to continue outputting until the length of the last row of the current frame image satisfies the preset condition, and output a vertical synchronization signal and a horizontal synchronization signal corresponding to a next frame image as signals required by the display driving unit for performing control.

9. A display device, characterized by comprising: including: The driving apparatus of the display panel according to claim 7 or 8.

10. An electronic device comprising a memory, a processor, and a computer program stored on the memory, wherein the computer program, when executed by the processor, is arranged to perform the method of any one of claims 1 to 9. The processor executes the computer program to implement the steps of the method of any one of claims 4-6.

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