Memory circuitry and methods for forming memory circuitry

Abstract

This application relates to memory circuitry and methods for forming memory circuitry. A method for forming memory circuitry includes forming a transistor individually including one source / drain region and another source / drain region. A channel region is between the one source / drain region and the another source / drain region. A conductive gate is operatively proximate the channel region. A conductive via is formed individually directly electrically coupled to the another source / drain region. A conductor material is formed directly coupled to the one source / drain region. The conductor material is patterned in one direction to form horizontal lines of the conductor material having horizontal trenches between immediately adjacent horizontal conductor material lines. In a self-aligned manner, digit lines are formed individually in individual ones of the trenches between the immediately adjacent conductor material lines.

Description

TECHNICAL FIELD

[0001] Embodiments disclosed herein relate to memory circuitry and methods for forming memory circuitry. BACKGROUND

[0002] Memory is a type of integrated circuitry and is used in computer systems to store data. Memory can be fabricated in one or more arrays of individual memory cells. Memory cells can be written to or read from using digit lines (which can also be referred to as bit lines, data lines, or sense lines) and access lines (which can also be referred to as word lines). Digit lines can electrically interconnect memory cells along columns of an array, and access lines can electrically interconnect memory cells along rows of an array. Each memory cell can be uniquely addressed by a combination of a digit line and an access line.

[0003] Memory cells can be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for a long period of time without being powered. Non-volatile memory is typically designated as memory having a retention time of at least about 10 years. Volatile memory dissipates and thus is refreshed / re-written to maintain data storage. Volatile memory can have a retention time of milliseconds or less. Regardless, memory cells are configured to retain or store memory in at least two different, optional states. In binary systems, the states are considered a “0” or a “1”. In other systems, at least some individual memory cells can be configured to store more than two levels or states of information.

[0004] Capacitors are one type of electronic component that can be used in memory cells. Capacitors have two electrical conductors separated by an electrically insulating material. Energy as an electric field can be stored in such material in an electrostatic manner. Depending on the composition of the insulator material, the stored field will be volatile or non-volatile. For example, a capacitor insulator material comprising only Si02 will be volatile. One type of non-volatile capacitor is a ferroelectric capacitor having at least part of the insulating material as a ferroelectric material. Ferroelectric materials are characterized as having two stable polarization states and can thus comprise programmable materials for capacitors and / or memory cells. The polarization states of a ferroelectric material can be changed by applying a suitable programming voltage, and remain (at least for a period of time) after the programming voltage is removed. Each polarization state has a different charge storage capacitance from the other, which can ideally be used to write (i.e., store) and read memory states without reversing the polarization state until such reversal is desired. Less desirably, in some memories having ferroelectric capacitors, the act of reading a memory state can reverse the polarization. Thus, after determining the polarization state, the memory cell is re-written to place the memory cell in a pre-reading state immediately after the determination of the polarization state. Regardless, due to the bistable nature of the ferroelectric material forming part of the capacitor, a memory cell incorporating a ferroelectric capacitor is ideally non-volatile. Other programmable materials can be used as capacitor insulators to make capacitors non-volatile.

[0005] Field effect transistors are another type of electronic component that can be used in memory cells. These transistors include a pair of conductive source / drain regions with a semiconductive channel region therebetween. A conductive gate is adjacent to the channel region and separated from the channel region by a thin gate insulator. Application of a suitable voltage to the gate allows current to flow through the channel region from one of the source / drain regions to the other. When the voltage is removed from the gate, current flow through the channel region is greatly prevented. Field effect transistors can also include additional structures, for example, a reversible programmable charge storage region as part of a gate structure between the gate insulator and the conductive gate. Regardless, the gate insulator can be programmable, for example, ferroelectric. SUMMARY

[0006] Aspects of the present disclosure provide a memory circuitry, comprising: a substrate comprising transistors individually comprising: a pair of source / drain regions; a channel region between the pair of source / drain regions; and a conductive gate operatively proximate the channel region; a conductor via individually directly electrically coupled to one of the pair of source / drain regions, the conductor via individually comprising, in a vertical cross-section, a vertical portion comprising two sidewalls tapering laterally outward from a top to a bottom; a conductive via individually directly electrically coupled to another of the pair of source / drain regions; a digit line individually directly electrically coupled to the plurality of conductive vias along a line of the plurality of transistors; and a storage element directly electrically coupled to individual ones of the conductor vias.

[0007] Aspects of the present disclosure provide a memory circuitry, comprising: a substrate comprising transistors individually comprising: a pair of source / drain regions; a channel region between the pair of source / drain regions; and a conductive gate operatively proximate the channel region; a conductor via individually directly electrically coupled to one of the pair of source / drain regions; a conductive via individually directly electrically coupled to another of the pair of source / drain regions; a digit line individually directly electrically coupled to the plurality of conductive vias along a line of the plurality of transistors, the digit line individually having, in a vertical cross-section, two sidewalls tapering laterally outward from a top to a bottom; and a storage element directly electrically coupled to individual ones of the conductor vias.

[0008] Aspects of the present disclosure provide a memory circuitry, comprising: a substrate comprising transistors individually comprising: a pair of source / drain regions; a channel region between the pair of source / drain regions; and a conductive gate operatively proximate the channel region; a conductor via individually directly electrically coupled to one of the pair of source / drain regions; a conductive via individually directly electrically coupled to another of the pair of source / drain regions; a digit line individually directly electrically coupled to the plurality of conductive vias along a line of the plurality of transistors; the conductor via individually comprising: a lower conductively-doped semiconductive material directly electrically coupled to the one source / drain region; and an upper metallic material directly electrically coupled to the lower conductively-doped semiconductive material directly above the lower conductively-doped semiconductive material, the upper metallic material covering all top surfaces of the lower conductively-doped semiconductive material; and a storage element directly electrically coupled to the upper metallic material of individual ones of the conductor vias.

[0009] Another aspect of the present disclosure provides a memory circuitry, comprising: a substrate comprising transistors individually comprising: a pair of source / drain regions; a channel region between the pair of source / drain regions; and a conductive gate in operational proximity to the channel region; a conductor via individually directly electrically coupled to one of the source / drain regions in the pair of source / drain regions, the conductor via individually comprising in a vertical cross-section a vertical portion comprising two sidewalls tapering laterally outward from top to bottom; a conductive via individually directly electrically coupled to another of the source / drain regions in the pair of source / drain regions; a digit line individually directly electrically coupled to the plurality of conductive vias along a line of the plurality of transistors, the digit line individually having in a vertical cross-section two sidewalls tapering laterally outward from top to bottom; the conductor via individually comprising: a lower conductively-doped semiconductive material directly electrically coupled to the one source / drain region; and an upper metallic material directly electrically coupled to the lower conductively-doped semiconductive material directly above the lower conductively-doped semiconductive material, the upper metallic material covering all top surfaces of the lower conductively-doped semiconductive material; and a storage element directly electrically coupled to individual ones of the conductor vias.

[0010] Another aspect of the present disclosure provides a memory circuitry, comprising: a substrate comprising transistors individually comprising: a pair of source / drain regions; a channel region between the pair of source / drain regions; and a conductive gate in operational proximity to the channel region; a conductor via individually directly electrically coupled to one of the source / drain regions in the pair of source / drain regions; a conductive via individually directly electrically coupled to another of the source / drain regions in the pair of source / drain regions; a digit line individually directly electrically coupled to the plurality of conductive vias along a line of the plurality of transistors; a storage element directly electrically coupled to individual ones of the conductor vias; and the conductor via individually comprising a portion directly below one of the word lines.

[0011] Another aspect of the present disclosure provides a method for forming memory circuitry, comprising: forming a transistor individually comprising: one source / drain region and another source / drain region; a channel region between the one source / drain region and the another source / drain region; and a conductive gate in operative proximity to the channel region; forming a conductive via individually directly electrically coupled to the another source / drain; forming a conductor material directly coupled to the one source / drain region; patterning the conductor material in one direction to form horizontal lines of the conductor material, the horizontal lines having horizontal trenches between immediately adjacent horizontal conductor material lines; in a self-aligned manner, forming digit lines individually in the individual ones of the trenches between immediately adjacent conductor material lines; after forming the digit lines, patterning the conductor material in another direction at an angle to the one direction to form conductor vias individually directly electrically coupled to the one source / drain region; and forming a plurality of storage elements individually directly electrically coupled to the individual ones of the conductor vias. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figures 1 to 7 Illustrative cross-sectional view of a portion of a DRAM construction according to some embodiments of the present invention.

[0013] Figure 8 Illustrative cross-sectional view of a portion of a DRAM construction according to some embodiments of the present invention.

[0014] Figures 9 to 17 Illustrative sequence of cross-sectional views of a portion of a DRAM construction according to some embodiments of the present invention, during formation of Figures 1 to 7 Figures 1 to 7 DETAILED DESCRIPTION

[0015] Embodiments of the present invention encompass memory circuitry, such as DRAM, and methods for forming memory circuitry, such as DRAM. Reference is made to Figures 1 to 7 A first example embodiment of a DRAM construction is described including Figures 1 to 7 An example fragment of a substrate construction 8 is shown including an array or array region 10 that has been fabricated relative to a base substrate 11. The substrate construction 11 can include any one or more of conductive / conductor / conducting, semiconductive / semiconductor / semiconducting, and insulative / insulator / isolating (i.e., electrically in this context) materials. Various materials are over the base substrate 11. The materials can be patterned in any manner, including by photolithography, etching, and / or other patterning techniques. Figures 1 to 7 ​​The depicted material is to the side, vertically inboard, or vertically outboard of the other portions of the integrated circuit. For example, other portions of the integrated circuit can be fabricated on, around, or somewhere inboard of the base substrate 11. Control circuitry and / or other peripheral circuitry for operating components within the memory array can also be fabricated, and can or can not be wholly or partially within the memory array or sub-array. Moreover, multiple sub-arrays can also be fabricated and operated independently, sequentially, or otherwise, relative to one another. As used in this document, a "sub-array" can also be considered an array.

[0016] The base substrate 11 includes a semiconductive material 12 (e.g., suitably and differently doped single and / or poly crystalline silicon, Ge, SiGe, GaAs, and / or other existing or future developed semiconductive materials), a trench isolation region 14 (e.g., silicon nitride and / or silicon dioxide), and an active region 16 including suitably and differently doped semiconductive material 12. In one embodiment, the construction 8 includes memory cells 75 Figure 5 and 7 , and for clarity in these drawings, has only four outlines 75 shown in Figure 5 and only two outlines 75 in Figure 7 ), e.g., DRAM memory cells, that individually include a field effect transistor device 25 Figure 3 ) and a storage element (e.g., a capacitor 85; Figure 1 and 7 ). However, embodiments of the invention encompass other memory cells and integrated circuit constructions independent of whether they contain memory cells.

[0017] The example transistor devices 25 individually include a pair of source / drain regions, a channel region between the pair of source / drain regions, a conductive gate in operative proximity to the channel region, and a gate insulator between the conductive gate and the channel region. The devices 25 are shown as recessed access devices, with the example construction 8 showing these recessed access devices grouped in individual pairs of such devices. The individual recessed access devices 25 include a buried access line construction 18, e.g., within a trench 19 in the semiconductive material 12. The construction 18 includes a conductive gate material 22 (e.g., a conductive doped semiconductor material and / or a metallic material, including, e.g., elemental W, Ru, and / or Mo) that acts as the conductive gate for the individual device 25. A gate insulator 20 (e.g., silicon dioxide and / or silicon nitride) is between the conductive gate material 22 and the semiconductive material 12 along sidewalls 21 and a base 23 of the individual trench 19. An insulator material 37 (e.g., silicon dioxide and / or silicon nitride) is within the trench 19 over the materials 20 and 22. The individual device 25 includes a pair of source / drain regions 24, 26 (e.g., regions 24, 26 laterally outward from and above the access line construction 18) in an upper portion of the semiconductive material 12 on opposite sides of the individual trench 19. Each of the source / drain regions 24, 26 has at least one portion thereof having a dopant of increased conductivity, which is the greatest concentration of such a dopant within the respective source / drain region 24, 26, e.g., so that this portion is conductive (e.g., has a maximum dopant concentration of at least 1010atoms / cm3). Thus, all or only a portion of each source / drain region 24, 26 can have such a maximum concentration of a dopant of increased conductivity. The source / drain regions 24 and / or 26 can include other doped regions (not shown), e.g., halogen regions, LDD regions, etc. 19 atoms / cm3 3 Thus, all or only a portion of each source / drain region 24, 26 can have such a maximum concentration of a dopant of increased conductivity. The source / drain regions 24 and / or 26 can include other doped regions (not shown), e.g., halogen regions, LDD regions, etc.

[0018] One of the source / drain regions of a pair of source / drain regions (e.g., region 26) in an individual one of a pair of recessed access devices 25 is laterally between the conductive gate material 22 and shared by the pair of devices 25. The other source / drain region of the pair of source / drain regions (e.g., region 24) is not shared by the pair of devices 25. Thus, in example embodiments, each active area region 16 includes two devices 25 (e.g., a pair of devices 25), with each device sharing a central source / drain region 26.

[0019] The example channel regions 27 Figure 1 , 3 , 6, and 7 are in the semiconductive material 12 along the trench sidewalls 21 Figure 6 and 7) under a pair of source / drain regions 24, 26 and around the trench base 23. The channel region 27 can be un-doped or can be suitably doped with conductivity-increasing dopants, which are likely to be of opposite conductivity type to the source / drain regions 24, 26, and for example have a maximum concentration in the channel of no more than 1 x 1018 atoms / cm3. 17 atoms / cm3 3 When a suitable voltage is applied to the gate material 22 of the access line formation 18, a conductive channel is formed within the channel region 27 proximate the gate insulator 20 (e.g., along a channel current flow pipeline / path 29[ Figure 7 ]) enabling current to flow between a pair of source / drain regions 24 and 26 under the access line formation 18 within the individual active area region 16. The dot hatch is shown in a diagrammatic manner to indicate conductivity-modifying dopant concentrations (regardless of type), with denser dot hatch indicating greater dopant concentration and lighter dot hatch indicating lower dopant concentration. Conductivity-modifying dopants can be, and will likely be, in other portions of the material 12 as shown. Only two different dot hatch densities are shown in the material 12 for convenience, and additional dopant concentrations can be used, and constant dopant concentrations in any region are not required.

[0020] The conductor via 36 (e.g., including the conductive / conductor materials 32 and 60) is individually directly electrically coupled to one of the source / drain regions (e.g., 24) in the pair of source / drain regions. One of the storage elements 85 is directly electrically coupled to the individual conductor via 36 (e.g., at a top thereof). In one embodiment, a vertical cross-section (e.g., along the line A-A in FIG. 1) of the individual storage element 85 is shown in FIG. 2. Figure 1The conductor vias 36 individually include a vertical portion 51 having two sidewalls 52, 53 that taper laterally outward from top to bottom in one such embodiment and as shown, the vertical portion 51 is less than all of the respective conductor vias 36 in a vertical cross-section. In one such embodiment, the vertical portion 51 can be considered one vertical portion, where the conductor via 36 individually includes another vertical portion 54 below the one vertical portion 51 in a vertical cross-section. The other portion 54 has one sidewall 55 that tapers laterally outward from top to bottom, and another sidewall 57 that does not taper laterally outward from top to bottom. In one embodiment, the other sidewall 57 is vertical. In one embodiment, the conductor via 36 individually includes a lower conductively-doped semiconductive material 32 (e.g., conductively-doped polysilicon) directly electrically coupled to (in embodiments directly against) one source / drain region 24. The conductor material 60 includes an upper metallic material 60 directly electrically coupled to (in one embodiment directly against) the lower conductively-doped semiconductive material 32 directly above the lower conductively-doped semiconductive material 32. In one embodiment, the upper metallic material 60 covers all of the top surface 61 of the lower conductively-doped semiconductive material 32. In one embodiment, the vertical portion 51 is the upper metallic material 60. In one embodiment, the upper metallic material 60 extends laterally outward beyond at least one side 64 (only one side 64 shown) of the top surface 61 of the lower conductive material 32 in a vertical cross-section (e.g., Figure 1 of the conductor via 36 in a vertical cross-section.

[0021] The conductive via 33 is individually directly electrically coupled to another one of the pair of source / drain regions (e.g., 26). The digit line 39 is individually directly electrically coupled to the plurality of conductive vias 33 along the line of the plurality of transistors 25. The conductive via 33 can have the same or different composition than the composition of the digit line 39. In one embodiment, the digit line 39 individually has two sidewalls 62, 63 that taper laterally inward from top to bottom in a vertical cross-section (e.g., Figure 1 of the conductor via 36 in a vertical cross-section.

[0022] The example insulative material 38 (e.g., silicon nitride and / or silicon dioxide) is around, above, and / or below the example conductive material. The example material 48 (e.g., silicon nitride and / or silicon dioxide) is below the digit line 39 and the insulative material 38, between longitudinally adjacent conductive vias 33 (e.g., Figure 1 、 6 , 7).

[0023] Any other property or aspect as shown and / or described herein with respect to other embodiments can be used in reference to the embodiments shown and described above.

[0024] Figure 8An example alternative construction 8a is shown. Where appropriate, the same reference numbers are used for the above-described embodiments, with some construction differences indicated with a suffix "a" or with different reference numbers. The conductor vias 36a of construction 8a individually include a portion 90 (e.g., of material 32) directly under one of the digit lines 39. Any other properties or aspects as shown and / or described herein with respect to other embodiments can be used.

[0025] Embodiments of the invention encompass methods for forming memory circuitry. Embodiments of the invention encompass memory arrays independent of fabrication methods. However, such memory arrays can have any of the properties as described herein in the method embodiments. Likewise, the above-described method embodiments can incorporate, form and / or have any of the properties described with respect to the device embodiments. Examples of such method embodiments are described with respect to 9-17, where the description is for a method embodiment by a device embodiment. Figures 1 to 7 The pre-construction of the shown construction uses the same reference numbers. In one embodiment, a method for forming a memory circuit includes forming a transistor (e.g., 25) that individually includes one source / drain region (e.g., 24) and another source / drain region (e.g., 26). A channel region (e.g., 27) is between the one source / drain region and the another source / drain region. A conductive gate (e.g., of material 22) is operatively proximate the channel.

[0026] Referring to Figure 9 such cross-sections correspond to Figure 1 cross-sections of

[0027] Referring to Figure 10 a conductor material 60 has been formed and is directly coupled (e.g., by material 32) to the one source / drain region 24.

[0028] Referring to Figure 11 and 12 an optional sacrificial material 83 has been formed over the conductor material 60, and then the conductor material 60 is patterned in one direction (e.g., direction Dl) to form horizontal lines 80 of the conductor material 60, and the horizontal lines 80 have horizontal trenches 82 between immediately adjacent horizontal conductor material lines 80.

[0029] In a self-aligned manner, digit lines are formed individually in the trenches between immediately adjacent horizontal lines of the conductor material. One example of such a manner of operation is shown in Figure 13 and 14 This shows filling and then etching back the insulating material 38 in the trenches 82 to have a top that corresponds to the bottom of the digit lines 39, as shown in Figure 1The insulating material 38 is deposited into the trenches 24 as shown. Thereafter, the insulating material 38 is anisotropically etched in a spacer-like manner to remove such material substantially from above the horizontal surfaces. Thereafter, a conductive material of digit lines 39 is deposited into the remaining volume of the trenches 82, followed by etching back such conductive material to form the digit lines 39 as shown. Figure 15 Subsequent deposition and planarization of the backside of the insulating material 38 over the digit lines 39 is shown.

[0030] After forming the conductive lines 39, and with reference to Figure 16 and 17 The conductor material 60 is patterned in another direction (e.g., D2) that is angled (e.g., at 90°) to the one direction D1 to form conductor vias 36 that are individually directly electrically coupled to one source / drain region 24. A plurality of storage elements (e.g., Figure 1 in 85) and individually directly electrically coupled to individual conductor vias 36 are formed.

[0031] In one embodiment, the formed memory circuitry includes DRAM. In one embodiment, the conductor vias 36 in a vertical cross-section (e.g., Figure 1 ) individually include a vertical portion 51 having two sidewalls 52, 53 that are laterally tapered outward from top to bottom. In one embodiment, the digit lines 39 in a vertical cross-section (e.g., Figure 1 ) individually have two sidewalls 62, 63 that are laterally tapered inward from top to bottom.

[0032] In one embodiment, the conductor vias 36 individually include a lower conductively-doped semiconductive material 32 (e.g., conductively-doped polysilicon) that is directly electrically coupled to (in embodiments directly against) one source / drain region 24. An upper metallic material 60 is directly electrically coupled to the lower conductively-doped semiconductive material 32 directly above the lower conductively-doped semiconductive material 32. In one embodiment, the upper metallic material 60 covers all top surfaces 61 of the lower conductively-doped semiconductive material 32.

[0033] In one embodiment, the conductor vias (e.g., 36a) individually include a portion (e.g., 90) Figure 8 ) directly below one of the digit lines 39.

[0034] Any other property or aspect as shown and / or described herein with respect to other embodiments can be used.

[0035] The above processing or construction can be viewed with respect to an array of components, the components being formed as or within a single stack or single deck of such components, the stack or deck being over or part of an underlying base substrate (but a single stack / deck can have multiple layers). Control and / or other peripheral circuitry for operating or accessing such components within the array can also be formed as part of the final construction, in any location, and in some embodiments can be under the array (e.g., CMOS under array). Regardless, one or more additional such stacks / decks can be provided or fabricated over and / or under the stack / deck shown in the figures or described above. Further, the arrays of components can be the same or different relative to each other in different stacks / decks, and different stacks / decks can have the same or different thicknesses relative to each other. Intervening structures can be provided between vertically adjacent stacks / decks (e.g., additional circuitry and / or dielectric layers). Further, different stacks / decks can be electrically coupled relative to each other. Multiple stacks / decks can be fabricated individually and sequentially (e.g., one on top of the other), or two or more stacks / decks can be fabricated substantially simultaneously.

[0036] The assemblies and structures discussed above can be used in integrated circuits / circuitry and can be incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and business machines, and can include multilayer, multichip modules. The electronic systems can be any of a broad range of systems, such as, for example, cameras, wireless devices, displays, chip sets, set top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0037] In this document, unless otherwise indicated, "vertical," "higher," "upper," "lower," "top," "over," "bottom," "above," "below," "under," "beneath," "upward," and "downward" refer generally to upright directions in the context of the vertical orientation of the substrate during processing. "Horizontal" refers to a direction along a major surface of the substrate and can be within 10 degrees of the general direction of the substrate as it is handled during manufacturing (i.e., within 10 degrees), and vertical is a direction generally orthogonal thereto. Reference to "exactly horizontal" refers to a direction along a major surface of the substrate (i.e., no degrees from the surface) and can be referenced by the substrate as it is handled during manufacturing. Furthermore, "vertical" and "horizontal" as used herein are generally perpendicular directions with respect to each other, and are independent of the orientation of the substrate in three-dimensional space. Additionally, "vertically extending" and "extends vertically" refer to a direction that is at least 45° from exactly horizontal. Furthermore, with respect to field effect transistors, "vertically extending," "vertically extended," "horizontally extending," "horizontally extended," and the like refer to the orientation of the channel length of the transistor, along which current flows between source / drain regions in operation. For bipolar junction transistors, "vertically extending," "vertically extended," "horizontally extending," "horizontally extended," and the like refer to the orientation of the base length, along which current flows between the emitter and collector in operation. In some embodiments, any component, feature, and / or region that extends vertically extends vertically or within 10° of vertical.

[0038] Furthermore, "directly above," "directly below," and "directly under" require at least some lateral overlap (i.e., horizontally) of the two stated regions / materials / components with respect to each other. Additionally, the use of "above" without "directly" preceding it only requires that some portion of the stated region / material / component above the other stated region / material / component is vertically outward of the other stated region / material / component (i.e., regardless of whether there is any lateral overlap of the two stated regions / materials / components). Similarly, the use of "below" and "under" without "directly" preceding it only requires that some portion of the stated region / material / component below the other stated region / material / component is vertically inward of the other stated region / material / component (i.e., regardless of whether there is any lateral overlap of the two stated regions / materials / components).

[0039] Any of the materials, regions, and structures described herein can be uniform or non-uniform, and regardless, continuous or discontinuous over any material on which it is over. When one or more example compositions are provided for any material, the material can comprise, consist essentially of, or consist of the one or more compositions. Further, unless otherwise stated, each material can be formed using any suitable existing or future-developed technique, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation being examples.

[0040] In addition, "thickness" (without a directional adjective in front) used alone is defined as the average straight-line distance through a given material or region, perpendicular from the closest surface of an immediately-adjacent material or region of different composition. In addition, the various materials or regions described herein can have a substantially constant thickness or a variable thickness. If having a variable thickness, unless otherwise indicated, thickness refers to average thickness, and such a material or region will have some minimum thickness and some maximum thickness due to the variable thickness. As used herein, "different composition" only requires that those portions of two stated materials or regions that can be directly against each other be chemically and / or physically different, e.g., if the materials or regions are not uniform. If two stated materials or regions are not directly against each other, then "different composition" only requires that those portions of the two stated materials or regions that are closest to each other be chemically and / or physically different, if such materials or regions are not uniform. In this document, a material, region, or structure is "directly against" another material, region, or structure when there is at least some physical contact between the stated materials, regions, or structures relative to each other. In contrast, "over," "on," "adjacent," "along," and "against" without the "directly" in front encompass both "directly against" and configurations where intervening materials, regions, or structures are such that the stated materials, regions, or structures have no physical touch contact relative to each other.

[0041] Herein, zone-material-assemblies are "electrically coupled" relative to each other if, in normal operation, current is able to flow continuously from one zone-material-assembly to another, and the flow is primarily through movement of subatomic positive and / or negative charges when sufficient subatomic positive and / or negative charges are generated. Another electronic assembly can be between and electrically coupled to the zone-material-assemblies. In contrast, when zone-material-assemblies are said to be "directly electrically coupled," there are no intervening electronic assemblies (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between the directly electrically coupled zone-material-assemblies.

[0042] Any use of "row" and "column" in this document is to facilitate distinguishing one series or orientation of features from another series or orientation of features, and assemblies have been or can be formed along the "rows" and "columns." "Row" and "column" are used synonymously with respect to any series of regions, assemblies, and / or features, regardless of function. Regardless, rows can be straight and / or curved and / or parallel and / or non-parallel with respect to one another, as can columns. Moreover, rows and columns can intersect at 90° or at one or more other angles (i.e., other than a right angle) with respect to one another.

[0043] The composition of any of the conductive / conductor / conducting materials herein can be a metallic material and / or an electrically conductive doped semiconductive / semiconductor / semiconducting material. A "metallic material" is any one or a combination of an elemental metal, any mixture or alloy of two or more elemental metals, and any one or more electrically conductive metal compounds.

[0044] Any use of "selectivity" herein with respect to etch, etching, removing, removal, deposition, forming, and / or formation is a stated material performing the action at a rate of at least 2: 1 by volume with respect to another stated material being acted upon. Moreover, any use of selectively depositing, selectively growing, or selectively forming is depositing, growing, or forming one material with respect to another stated material(s) at a ratio of at least 2: 1 by volume for at least a first 75 Angstroms of deposition, growth, or formation.

[0045] "Self-aligned" or "self-aligning" herein means a technique in which at least one side surface of a subsequently formed structure is defined by depositing a material on a sidewall of a previously formed structure, such that no subsequent photolithography or other processing of the side surface of the subsequently formed structure is needed.

[0046] The use of "or" herein is encompassed by either and both unless otherwise indicated.

[0047] CONCLUSION

[0048] In some embodiments, memory circuitry includes a substrate including transistors individually including a pair of source / drain regions. A channel region is between the pair of source / drain regions. A conductive gate is operatively proximate the channel region. A conductor via is individually directly electrically coupled to one of the source / drain regions of the pair of source / drain regions. The conductor via individually includes, in a vertical cross-section, a vertical portion having two sidewalls that taper laterally outward from top to bottom. A conductive via is individually directly electrically coupled to another of the source / drain regions of the pair of source / drain regions. A digit line is individually directly electrically coupled to the plurality of conductive vias along a line of the plurality of transistors. A storage element is directly electrically coupled to an individual of the conductor vias.

[0049] In some embodiments, memory circuitry includes a substrate including transistors individually including a pair of source / drain regions. A channel region is between the pair of source / drain regions. A conductive gate is operatively proximate the channel region. A conductor via is individually directly electrically coupled to one of the source / drain regions of the pair of source / drain regions. A conductive via is individually directly electrically coupled to another of the source / drain regions of the pair of source / drain regions. A digit line is individually directly electrically coupled to the plurality of conductive vias along a line of the plurality of transistors. The digit line individually has, in a vertical cross-section, two sidewalls that taper laterally inward from top to bottom. A storage element is directly electrically coupled to an individual of the conductor vias.

[0050] In some embodiments, memory circuitry includes a substrate including transistors individually including a pair of source / drain regions. A channel region is between the pair of source / drain regions. A conductive gate is operatively proximate the channel region. A conductor via is individually directly electrically coupled to one of the source / drain regions of the pair of source / drain regions. A conductive via is individually directly electrically coupled to another of the source / drain regions of the pair of source / drain regions. A digit line is individually directly electrically coupled to the plurality of conductive vias along a line of the plurality of transistors. The conductor via individually includes a lower conductively-doped semiconductive material directly electrically coupled to one source / drain region. An upper metallic material is directly electrically coupled to the lower conductively-doped semiconductive material directly above the lower conductively-doped semiconductive material. The upper metallic material covers all top surfaces of the lower conductively-doped semiconductive material. A storage element is directly electrically coupled to the upper metallic material of an individual of the conductor vias.

[0051] In some embodiments, memory circuitry includes a substrate including transistors individually including a pair of source / drain regions. A channel region is between the pair of source / drain regions. A conductive gate is operatively proximate the channel region. A conductor via is individually directly electrically coupled to one of the source / drain regions of the pair of source / drain regions. The conductor via individually includes, in a vertical cross-section, a vertical portion having two sidewalls that taper laterally outward from top to bottom. A conductive via is individually directly electrically coupled to another of the source / drain regions of the pair of source / drain regions. A digit line is individually directly electrically coupled to the plurality of conductive vias along a line of the plurality of transistors. The digit line individually has, in a vertical cross-section, two sidewalls that taper laterally inward from top to bottom. The conductor via individually includes a lower conductively-doped semiconductive material directly electrically coupled to one source / drain region. An upper metallic material is directly electrically coupled to and directly above the lower conductively-doped semiconductive material. The upper metallic material covers all top surfaces of the lower conductively-doped semiconductive material. A storage element is directly electrically coupled to an individual of the conductor vias.

[0052] In some embodiments, memory circuitry includes a substrate including transistors individually including a pair of source / drain regions. A channel region is between the pair of source / drain regions. A conductive gate is operatively proximate the channel region. A conductor via is individually directly electrically coupled to one of the source / drain regions of the pair of source / drain regions. The conductive via is individually directly electrically coupled to another of the source / drain regions of the pair of source / drain regions. A digit line is individually directly electrically coupled to the plurality of conductive vias along a line of the plurality of transistors. A storage element is directly electrically coupled to an individual of the conductor vias. The conductor via individually includes a portion directly below one of the digit lines.

[0053] In some embodiments, a method for forming memory circuitry includes forming transistors individually including one source / drain region and another source / drain region. A channel region is between the one source / drain region and the another source / drain region. A conductive gate is operatively proximate the channel region. Forming conductive vias individually directly electrically coupled to the another source / drain region. Forming a conductor material directly coupled to the one source / drain region. Patterning the conductor material in one direction to form horizontal lines of the conductor material having horizontal trenches between immediately adjacent horizontal conductor material lines. Forming digit lines in a self-aligned manner individually in an individual of the trenches between immediately adjacent conductor material lines. After forming the digit lines, patterning the conductor material in another direction at an angle to the one direction to form conductor vias individually directly electrically coupled to an individual of the one source / drain regions. Forming a plurality of storage elements individually directly electrically coupled to an individual of the conductor vias.

[0054] In compliance with the statute, the subject matter disclosed herein has been described in language more or less specific to structural and methodical features. It is to be understood that the claims are not limited to the specific features shown and described, since the means herein disclosed comprise examples of implementations. The intent is to cover all alternative steps and modifications that can be made to the described embodiments with the scope of equivalents of the claims appended hereto.

Claims

1. Memory circuitry comprising: a substrate comprising transistors, the transistors individually comprising: a pair of source / drain regions; a channel region between the pair of source / drain regions; and a conductive gate operatively proximate the channel region; a conductor via individually directly electrically coupled to one of the source / drain regions in the pair of source / drain regions, the conductor via individually comprising in a vertical cross-section a vertical portion having two sidewalls tapering laterally outward from top to bottom; a conductive via individually directly electrically coupled to another of the source / drain regions in the pair of source / drain regions; a digit line individually directly electrically coupled to a plurality of the conductive vias along a line of a plurality of the transistors; and a storage element directly electrically coupled to an individual of the conductor vias.

2. The memory circuitry of claim 1, wherein in the vertical cross-section, the vertical portion is less than all respective conductor vias.

3. The memory circuitry of claim 2, wherein the vertical portion is one vertical portion, the conductor via individually comprising in the vertical cross-section another vertical portion below the one vertical portion, the another vertical portion having one sidewall tapering laterally outward from top to bottom and another sidewall not tapering laterally outward from top to bottom.

4. The memory circuitry of claim 3, wherein the another sidewall is vertical.

5. The memory circuitry of claim 1, wherein the digit line individually has in the vertical cross-section two sidewalls tapering laterally inward from top to bottom.

6. The memory circuitry of claim 1, wherein the conductor via individually comprises: a lower conductively-doped semiconductive material directly electrically coupled to one source / drain region; and an upper metallic material directly electrically coupled to the lower conductively-doped semiconductive material directly above the lower conductively-doped semiconductive material, the upper metallic material covering all top surfaces of the lower conductively-doped semiconductive material.

7. The memory circuitry of claim 6, wherein the vertical portion is the upper metallic material.

8. The memory circuitry of claim 1, wherein the conductor via individually comprises a portion directly below one of the digit lines.

9. The memory circuitry of claim 8, wherein the portion directly below one of the digit lines is in the vertical cross-section.

10. The memory circuitry of claim 1, wherein the storage element is a capacitor.

11. The memory circuitry of claim 1, comprising DRAM.

12. Memory circuitry comprising: a substrate comprising transistors, the transistors individually comprising: a pair of source / drain regions; a channel region between the pair of source / drain regions; and a conductive gate operatively proximate the channel region; a conductor via individually directly electrically coupled to one of the source / drain regions of the pair of source / drain regions; a conductive via individually directly electrically coupled to the other of the source / drain regions of the pair of source / drain regions; a digit line individually directly electrically coupled to a plurality of the conductive vias along a line of a plurality of the transistors, the digit line individually having two sidewalls that taper laterally inward from top to bottom in a vertical cross-section; and a storage element directly electrically coupled to an individual of the conductor vias.

13. The memory circuitry of claim 12, wherein the conductor via individually comprises: a lower conductively-doped semiconductive material directly electrically coupled to the one source / drain region; and an upper metallic material directly electrically coupled to and directly on top of the lower conductively-doped semiconductive material, the upper metallic material covering all top surfaces of the lower conductively-doped semiconductive material.

14. The memory circuitry of claim 12, wherein the conductor via individually comprises a portion directly under one of the digit lines.

15. Memory circuitry comprising: a substrate comprising transistors, the transistors individually comprising: a pair of source / drain regions; a channel region between the pair of source / drain regions; and a conductive gate operatively proximate the channel region; a conductor via individually directly electrically coupled to one of the source / drain regions of the pair of source / drain regions; a conductive via individually directly electrically coupled to the other of the source / drain regions of the pair of source / drain regions; a digit line individually directly electrically coupled to a plurality of the conductive vias along a line of a plurality of the transistors; the conductor via individually comprising: a lower conductively-doped semiconductive material directly electrically coupled to the one source / drain region; and an upper metallic material directly electrically coupled to and directly on top of the lower conductively-doped semiconductive material, the upper metallic material covering all top surfaces of the lower conductively-doped semiconductive material; and a storage element directly electrically coupled to the upper metallic material of an individual of the conductor vias.

16. The memory circuitry of claim 15, wherein in a vertical cross-section, the upper metallic material extends laterally outward from top to bottom and the upper metallic material extends laterally outward beyond at least one side of the top surface of the lower conductively-doped semiconductive material.

17. The memory circuitry of claim 16, wherein in the vertical cross-section, the upper metallic material extends laterally outward beyond only one side of the top surface of the lower conductively-doped semiconductive material.

18. The memory circuitry of claim 15, wherein the conductor via individually comprises a portion directly under one of the digit lines.

19. Memory circuitry comprising: A substrate comprising transistors, the transistors individually comprising: a pair of source / drain regions; a channel region between the pair of source / drain regions; and a conductive gate in operational proximity to the channel region; a conductor via individually directly electrically coupled to one of the source / drain regions in the pair of source / drain regions, the conductor via individually comprising in vertical cross-section a vertical portion having two sidewalls that taper laterally outward from top to bottom; a conductive via individually directly electrically coupled to the other of the source / drain regions in the pair of source / drain regions; a digit line individually directly electrically coupled to a plurality of the conductive vias along a line of a plurality of the transistors, the digit line individually having in vertical cross-section two sidewalls that taper laterally inward from top to bottom; the conductor via individually comprising: a lower conductively-doped semiconductive material directly electrically coupled to the one source / drain region; and an upper metallic material directly electrically coupled to the lower conductively-doped semiconductive material directly above the lower conductively-doped semiconductive material, the upper metallic material covering all top surfaces of the lower conductively-doped semiconductive material; and a storage element directly electrically coupled to individual ones of the conductor vias.

20. A memory circuitry comprising: a substrate comprising transistors, the transistors individually comprising: a pair of source / drain regions; a channel region between the pair of source / drain regions; and a conductive gate in operational proximity to the channel region; a conductor via individually directly electrically coupled to one of the source / drain regions in the pair of source / drain regions; a conductive via individually directly electrically coupled to the other of the source / drain regions in the pair of source / drain regions; a digit line individually directly electrically coupled to a plurality of the conductive vias along a line of a plurality of the transistors; a storage element directly electrically coupled to individual ones of the conductor vias; and the conductor via individually comprising a portion directly below one of the digit lines.

21. The memory circuitry of claim 20, wherein the portion comprises a conductively-doped semiconductive material.

22. A method for forming memory circuitry, comprising: forming transistors, the transistors individually comprising: one source / drain region and another source / drain region; a channel region between the one source / drain region and the another source / drain region; and a conductive gate in operational proximity to the channel region; forming a conductive via individually directly electrically coupled to the another source / drain; forming a conductor material directly coupled to the one source / drain region; patterning the conductor material in one direction to form horizontal lines of the conductor material, the horizontal lines having horizontal trenches between immediately-adjacent horizontal conductor material lines; in a self-aligned manner, forming a digit line individually in individual ones of the trenches between the immediately-adjacent conductor material lines; patterning the conductor material in another direction that is at an angle to the one direction of water to form conductor vias that are individually directly electrically coupled to the one source / drain region; and forming a plurality of storage elements that are individually directly electrically coupled to individual ones of the conductor vias.

23. The method of claim 22, comprising forming the memory circuitry to include DRAM.

24. The method of claim 22, wherein the conductor vias individually include in vertical cross-section a vertical portion having two sidewalls that taper laterally outward from top to bottom.

25. The method of claim 22, wherein the digit lines individually have in vertical cross-section two sidewalls that taper laterally inward from top to bottom.

26. The method of claim 22, wherein the conductor vias individually comprise: a lower electrically conductively-doped semiconductive material directly electrically coupled to the one source / drain region; and an upper metallic material directly electrically coupled to and directly above the lower electrically conductively-doped semiconductive material, the upper metallic material covering all top surfaces of the lower electrically conductively-doped semiconductive material.

27. The method of claim 22, wherein the conductor vias individually comprise a portion directly below one of the digit lines.

28. The method of claim 22, wherein, the conductor vias individually include in vertical cross-section a vertical portion having two sidewalls that taper laterally outward from top to bottom; and the digit lines individually have in the vertical cross-section two sidewalls that taper laterally inward from top to bottom.

29. The method of claim 28, wherein the conductor vias individually comprise a portion directly below one of the digit lines.

30. The method of claim 22, wherein, the conductor vias individually include in vertical cross-section a vertical portion having two sidewalls that taper laterally outward from top to bottom; and the conductor vias individually comprise: a lower electrically conductively-doped semiconductive material directly electrically coupled to the one source / drain region; and an upper metallic material directly electrically coupled to and directly above the lower electrically conductively-doped semiconductive material, the upper metallic material covering all top surfaces of the lower electrically conductively-doped semiconductive material.

31. The method of claim 30, wherein the conductor vias individually comprise a portion directly below one of the digit lines.

32. The method of claim 22, wherein, the digit lines individually have in vertical cross-section two sidewalls that taper laterally inward from top to bottom; and the conductor vias individually comprise: a lower electrically conductively-doped semiconductive material directly electrically coupled to the one source / drain region; and an upper metallic material directly electrically coupled to and directly above the lower electrically conductively-doped semiconductive material, the upper metallic material covering all top surfaces of the lower electrically conductively-doped semiconductive material. An upper metallic material directly electrically coupled to the lower conductively-doped semiconductive material, the upper metallic material covering all top surfaces of the lower conductively-doped semiconductive material.

33. The method of claim 32 wherein the conductor vias individually include a portion directly beneath one of the digit lines.

34. The method of claim 26 wherein the conductor vias individually include a portion directly beneath one of the digit lines.

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