Low-capacitance silicon pixel detector array chip and its manufacturing method

Abstract

The present invention discloses a low-capacitance silicon pixel detector array chip and a manufacturing method thereof, belonging to the technical field of silicon detectors. The technical problem to be solved is how to improve the energy and position resolution of a soft X-ray or high-energy charged particle detector array chip. It is composed of a pixel unit array. Each pixel unit includes: a substrate, which is a silicon wafer substrate. One side of the substrate serves as a readout surface, and the side opposite to the readout surface serves as a receiving surface; an oxide layer, formed on the readout surface of the substrate and etched with a groove region, and the groove region includes a circular groove region; a cathode electrode, located within the groove region and embedded in the readout surface of the substrate, for serving as a collection electrode; a protection electrode, in a circular ring shape, embedded in the readout surface of the substrate and surrounding the outer periphery of the cathode electrode, for spacing the cathode electrodes between adjacent pixel units; and an anode electrode, embedded in the incident surface of the substrate and covering the entire incident surface of the substrate.

Description

Technical Field

[0001] The present invention relates to the technical field of silicon detectors, and more particularly to a low-capacitance silicon pixel detector array chip and a manufacturing method thereof. Background Art

[0002] Since the development of silicon detectors, the process foundation is relatively mature compared with other semiconductors and is easy to integrate. Therefore, it is very common in various fields of application, such as aerospace, deep space exploration, medical components, industry, etc. Among them, applications in aerospace technology include cameras used in the Chang'e lunar exploration project, core components in medical imaging devices, etc. Pixel detectors have good position resolution ability, and the smaller the size of the array unit, the higher the pixel. However, there are few reports on designs that improve both position resolution and energy resolution, but their application potential is very huge. The position resolution is related to the size of the detector array unit, and the energy resolution is related to the dark current and capacitance of the detector. Both of these are related to the electrode design of the pixel unit. Therefore, by optimizing the design of the electrode and size of the pixel unit, the characteristics of both energy and position resolution can be improved.

[0003] How to improve the energy and position resolution of a soft X-ray or high-energy charged particle detector array chip is a technical problem that needs to be solved. Summary of the Invention

[0004] The technical task of the present invention is to provide a low-capacitance silicon pixel detector array chip and a manufacturing method thereof to solve the problem of how to improve the energy and position resolution of the detector array chip in view of the above deficiencies.

[0005] In a first aspect, a low-capacitance silicon pixel detector array chip of the present invention is composed of a pixel unit array. Each pixel unit includes:

[0006] A substrate, the substrate is a silicon wafer substrate, one side of the substrate serves as a readout surface, and the side opposite to the readout surface serves as a receiving surface;

[0007] An oxide layer, the oxide layer is formed on the readout surface of the substrate and is etched with a groove region, and the groove region includes a circular groove region;

[0008] A cathode electrode, the cathode electrode is located in the groove region and is embedded in the readout surface of the substrate for use as a collection electrode;

[0009] A protection electrode, the protection electrode is in a circular ring shape, is embedded in the readout surface of the substrate and surrounds the outer periphery of the cathode electrode for spacing the cathode electrodes between adjacent pixel units;

[0010] An anode electrode, the anode electrode is embedded in the incident surface of the substrate and covers the entire incident surface of the substrate.

[0011] Preferably, the groove region further includes a plurality of triangular groove regions, the plurality of triangular groove regions are arranged at circumferential intervals and surround the outer periphery of the circular groove region, and one side of each triangular groove region is close to the circular groove region;

[0012] The cathode electrode located in the circular groove region serves as a collecting electrode;

[0013] The cathode electrode located in the triangular groove region serves as a floating electrode for voltage division.

[0014] Preferably, the triangular groove region is an isosceles triangular groove region, and the base of the triangular groove region is close to the circular groove region.

[0015] Preferably, the cathode electrode includes a first doped region implanted into the surface layer of the substrate reading surface and a first conductive metal layer covering the surface of the substrate reading surface, and the first doped region is in contact and cooperation with the first conductive metal layer;

[0016] The anode electrode includes a second doped region implanted into the surface layer of the substrate incident surface and a second conductive metal layer covering the surface of the substrate incident surface, and the second doped region is in contact and cooperation with the second conductive metal layer;

[0017] The protection electrode includes a third doped region implanted into the surface layer of the substrate reading surface.

[0018] Preferably, the thickness of the first doped region is greater than the thickness of the second doped region.

[0019] Preferably, the substrate is an N-type silicon wafer substrate;

[0020] Correspondingly, the first doped region is a P-type doped region;

[0021] Correspondingly, the third doped region is a P-type doped region;

[0022] Correspondingly, the second doped region is an N-type doped region;

[0023] Or, the substrate is a P-type silicon wafer substrate;

[0024] Correspondingly, the first doped region is an N-type doped region;

[0025] Correspondingly, the third doped region is an N-type doped region;

[0026] Correspondingly, the second doped region is a P-type doped region.

[0027] 7. The low-capacitance silicon pixel detector array chip according to claim 4, characterized in that

[0028] The substrate is a silicon wafer substrate with a thickness of 300 - 500 microns;

[0029] The thickness of the first doped region is 0.1 micron - 5 microns, and the doping concentration is 1x10 19 cm -3 ;

[0030] The thickness of the second doped region is 0.1 micron - 5 microns, and the doping concentration is 1x10 19 cm -3 ;

[0031] The triangular groove region is an isosceles triangular groove region with a base length of 10 microns and a height of 15 microns.

[0032] 8. A method for manufacturing a low-capacitance silicon pixel detector array chip, characterized in that it is used to manufacture a low-capacitance silicon pixel detector array chip as described in any one of claims 1 - 7 through the following steps. The method includes:

[0033] Select a silicon wafer and divide the silicon wafer into a pixel unit array;

[0034] Select one side of the silicon wafer as the read surface, and the side opposite to the read surface as the incident surface;

[0035] Inject a plurality of circular doped regions as protection electrodes in the surface layer of the read surface of the silicon wafer, and the protection electrodes correspond to the pixel units one by one;

[0036] Perform gettering oxidation on the read surface of the silicon wafer to form an oxide layer;

[0037] Through spin coating, photolithography, etching, and rinsing processes, etch a plurality of groove regions on the oxide layer. The groove regions correspond to the pixel units one by one, and the protection electrodes surround the outer periphery of the corresponding groove regions. Each groove region includes a circular groove region;

[0038] For each groove region, inject a doped region in the surface layer of the read surface of the silicon wafer by ion implantation, and form a conductive metal layer on the surface of the read surface of the silicon wafer. The doped region and the conductive metal layer cooperate to form a cathode electrode;

[0039] Inject a doped region in the surface layer of the incident surface of the silicon wafer by ion implantation, and form a conductive metal layer on the surface of the incident surface of the silicon wafer. The doped region and the conductive metal layer cooperate to form an anode electrode.

[0040] 9. The method for fabricating a low-capacitance silicon pixel detector array chip according to claim 8, wherein the groove region further includes a plurality of triangular groove regions, the plurality of triangular groove regions are arranged at circumferential intervals and surround the outer periphery of the circular groove region, and one side of each triangular groove region is close to the circular groove region;

[0041] The triangular groove region is an isosceles triangular groove region, and the base of the triangular groove region is close to the circular groove region;

[0042] The cathode electrode located within the circular groove region serves as a collection electrode;

[0043] The cathode electrode located within the triangular groove region serves as a floating electrode for voltage division.

[0044] 10. The method for fabricating a low-capacitance silicon pixel detector array chip according to claim 8 or 9, wherein the thickness of the doped region in the cathode electrode is greater than the thickness of the doped region in the anode electrode.

[0045] The low-capacitance silicon pixel detector array chip and its fabrication method of the present invention have the following advantages:

[0046] 1. A pattern region is etched on the oxide layer of the readout surface of the silicon wafer substrate, and a cathode electrode is formed within the pattern region as a readout electrode. Compared with using the entire plane of the silicon wafer as a readout electrode, forming a readout electrode within the pattern region reduces the area of the readout electrode, has the advantage of low capacitance, and the detector has high sensitivity and can be compatible with the readout circuit;

[0047] 2. The pattern region includes a circular region and a plurality of triangular regions circumferentially distributed around the circular region. The cathode electrode within the triangular region can serve as a floating electrode. Through the design of the floating electrode, the output dark current and capacitance of the detector can be reduced, and the full depletion voltage will also be smaller, without degrading the performance such as the electric field distribution of the detector;

[0048] 3. When the readout electrode is only a single point, the positive potential difference is concentrated near this point, and a higher bias voltage needs to be applied to fully deplete the entire device to reach the working state. However, in the pattern region of the present application, one side of each triangular region is close to the circular region, and the distribution of the floating electrode also has the effect of voltage division, making it easier for the device to deplete.

[0049] 4. The fabrication of this chip can be realized using standard CMOS processes, which is convenient for fabrication. Description of the Drawings

[0050] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the accompanying drawings required in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0051] The present invention will be further described below with reference to the accompanying drawings.

[0052] Figure 1 FIG. is a schematic structural diagram of a low-capacitance silicon pixel detector array chip for Embodiment 1;

[0053] Figure 2 FIG. is a schematic diagram of three-dimensional simulation modeling of a pixel unit of a low-capacitance silicon pixel detector array chip for Embodiment 1;

[0054] Figure 3 FIG. is a cross-section of the three-dimensional electric field distribution and two-dimensional electric field distribution of a pixel unit in a low-capacitance silicon pixel detector array chip for Embodiment 1; Figure 1 ;

[0055] Figure 4 FIG. is a cross-section of the three-dimensional potential distribution and two-dimensional potential distribution of a pixel unit in a low-capacitance silicon pixel detector array chip for Embodiment 1; Figure 2 ;

[0056] Figure 5 FIG. is the IV curve of a low-capacitance silicon pixel detector array chip for Embodiment 1;

[0057] Figure 6 FIG. is the CV curve of a low-capacitance silicon pixel detector array chip for Embodiment 1;

[0058] Figure 7 FIG. is the electron concentration distribution curve of a low-capacitance silicon pixel detector array chip for Embodiment 1;

[0059] Figure 8 FIG. is a schematic process flow diagram of a low-capacitance silicon pixel detector array chip for Embodiment 1;

[0060] In the figure, 1 is the substrate, 2 is the cathode electrode, 3 is the protection electrode, and 4 is the floating electrode. Specific Embodiments

[0061] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can better understand the present invention and be able to implement it. However, the specific embodiments cited are not intended to limit the present invention. Without conflict, the embodiments of the present invention and the technical features in the embodiments can be combined with each other.

[0062] The embodiments of the present invention provide a low-capacitance silicon pixel detector array chip and a manufacturing method thereof, which are used to solve the technical problem of how to improve the energy and position resolution of a soft X-ray or high-energy charged particle detector array chip.

[0063] Embodiment 1:

[0064] As Figure 1 and Figure 2 shown, a low-capacitance silicon pixel detector array chip of the present invention is composed of a pixel unit array. Each pixel unit includes a substrate, an oxide layer, a cathode electrode, a protection electrode, and an anode electrode.

[0065] The substrate is a silicon wafer substrate with a thickness of 100 - 500 microns. One surface of the substrate serves as the readout surface, and the surface opposite to the readout surface serves as the receiving surface.

[0066] The oxide layer is formed on the readout surface of the substrate and is etched with a groove region. The groove region includes a circular region, and the center of the circular region coincides with the center of the substrate.

[0067] The cathode electrode is formed in the groove region, that is, the cathode electrode is formed in the circular groove region. It includes a first heavily doped region implanted into the surface layer of the readout surface of the substrate and a first conductive metal layer formed on the surface of the readout surface of the substrate. The first heavily doped region and the first conductive metal layer are in contact and cooperate with each other as the cathode electrode. The cathode electrode cooperates with subsequent circuits such as an amplifier circuit as a collection electrode.

[0068] The protection electrode is in a circular ring shape, embedded in the readout surface of the substrate and surrounding the outer periphery of the cathode electrode, and is used to separate adjacent cathode electrodes. The protection electrode is a third heavily doped region implanted into the surface layer of the readout surface of the substrate. The third heavily doped region is in a circular ring shape and surrounds the outer periphery of the corresponding cathode electrode, specifically surrounding the outer periphery of the first heavily doped region, and there is a gap between it and the first heavily doped region. Its electrode polarity is the same as that of the first heavily doped region.

[0069] The anode electrode is embedded in the incident surface of the substrate and covers the entire incident surface of the substrate. It includes a second doped region implanted into the surface layer of the incident surface of the substrate and a second conductive metal layer covering the surface of the incident surface of the substrate. The second doped region and the second conductive metal layer are in contact and cooperate with each other as the anode electrode.

[0070] Particles enter from the incident surface, forming electron-hole pairs. The carriers move in the depleted silicon body to form an electrical signal, and the signal is read out through the electrodes on the readout surface and subsequent amplifier circuits.

[0071] For the above-structured pixel unit, compared with a pixel detector whose entire readout surface serves as a readout electrode, the area of the readout electrode on its readout surface is reduced, offering the advantage of low capacitance; and compared with a detector whose readout electrode is just a single point, its depletion voltage will also be reduced (when the readout electrode is just a single point, the positive potential difference on the front side is concentrated near that point, and a higher bias voltage is required to fully deplete the entire device to reach the working state).

[0072] As an example case, this detector consists of 9 pixel units arranged in a 3*3 array. In each pixel unit, the respective structures are as follows:

[0073] Substrate: An N-type silicon wafer substrate with a side length of 100 microns and a thickness of 300 microns is selected;

[0074] Oxide layer: A layer of silicon dioxide is formed on the readout surface of the substrate through gettering oxidation process. On this oxide layer, a circular groove region with a diameter of 30 microns is formed through processes such as spin coating, photolithography, etching, and rinsing. This circular groove region is concentric with the substrate;

[0075] Cathode electrode: It consists of a first doped region located within the circular groove region and embedded in the surface layer of the readout surface and a conductive metal layer located on the surface of the readout surface. The implementation method is as follows: within the circular groove region, p+-doped boron with a doping concentration of 1x10 19 cm -3 and a doping depth of 1 micron is implanted into the surface layer of the readout surface through ion implantation to form a P-type doped region as the first doped region. An aluminum plating layer is formed on the surface of the readout surface, and this aluminum plating layer is in contact with the P-type doped region to form the cathode electrode, which serves as the collection electrode (i.e., the readout electrode);

[0076] Protection electrode: It is the third doped region implanted into the surface layer of the readout surface. The implementation method is as follows: p+-doped boron is implanted into the surface layer of the readout surface to form an annular third doped region. The electrode polarity of this annular doped region is the same as that of the cathode electrode and surrounds the outer periphery of the P-type doped region in the cathode electrode, which can separate the connected cathode electrodes;

[0077] Anode electrode: It consists of a second doped region implanted into the incident surface and a conductive metal layer located on the surface of the incident surface. The implementation method is as follows: across the entire incident surface, n+-doped boron with a doping concentration of 1x10 19 cm -3 and a doping depth of 0.5 micron is implanted into the surface layer of the incident surface through ion implantation to form an N-type doped region as the second doped region. An aluminum plating layer is formed on the surface of the incident surface, and this aluminum plating layer is in contact with the N-type doped region to form the anode electrode.

[0078] As an alternative to the above specific implementation case, the structure is as follows:

[0079] Substrate: Select a P-type silicon wafer substrate with a side length of 100 microns and a thickness of 300 microns;

[0080] Oxide layer: A layer of silicon dioxide is formed on the reading surface of the substrate through a gettering oxidation process. A circular groove region with a diameter of 30 microns is formed on this oxide layer through processes such as spin coating, photolithography, etching, and rinsing. The circular groove region is concentric with the substrate;

[0081] Cathode electrode: It consists of a first doped region located within the circular groove region and embedded in the surface layer of the reading surface and a conductive metal layer located on the surface of the reading surface. The implementation method is as follows: within the circular groove region, n+-doped boron with a doping concentration of 1x10 19 cm -3 and a doping depth of 1 micron is implanted into the surface layer of the reading surface through ion implantation to form an N-type doped region as the first doped region. An aluminum plating layer is formed on the surface of the reading surface. The aluminum plating layer is in contact with the N-type doped region to form the cathode electrode, and this cathode electrode serves as the collection electrode (i.e., the readout electrode);

[0082] Protection electrode: It is the third doped region implanted into the surface layer of the reading surface. The implementation method is as follows: n+-doped boron is implanted into the surface layer of the reading surface to form an annular third doped region. The electrode polarity of this annular doped region is the same as that of the cathode electrode and surrounds the outer periphery of the N-type doped region in the cathode electrode, and can separate the connected cathode electrodes;

[0083] Anode electrode: It consists of a second doped region implanted into the incident surface and a conductive metal layer located on the surface of the incident surface. The implementation method is as follows: throughout the incident surface, p+-doped boron with a doping concentration of 1x10 19 cm-3 and a doping depth of 0.5 micron is implanted into the surface layer of the incident surface through ion implantation to form a P-type doped region as the second doped region. An aluminum plating layer is formed on the surface of the incident surface. The aluminum plating layer is in contact with the P-type doped region to form the anode electrode.

[0084] Considering the effect of the potential voltage division between the anode electrode and the cathode electrode, the pattern of the cathode electrode is improved. Specifically: the groove region etched on the oxide layer includes a circular groove region and multiple triangular groove regions. The multiple triangular groove regions are arranged at intervals in a circular pattern and surround the outer periphery of the circular groove region. One side of each triangular groove region is close to the circular groove region.

[0085] The cathode electrode located within the circular groove region serves as the collection electrode; the cathode electrode located within the triangular groove region serves as a floating electrode for voltage division.

[0086] Give a specific example. The grooved area further includes eight triangular grooved areas, and each of the triangular grooved areas is an isosceles triangular grooved area with a base length of 10 microns and a height of 15 microns. The base of the triangular grooved area is close to the circular grooved area.

[0087] As Figures 3 - 7 shown, with the assistance of the triangular floating electrode, the output dark current and capacitance of the detector can be reduced, and the fully depleted voltage will also be smaller. That is, the distribution of the electrodes in the above structure in this embodiment will also have the effect of potential voltage division, making it easier for the device to be depleted.

[0088] Embodiment 2:

[0089] The present invention relates to a method for fabricating a low-capacitance silicon pixel detector array chip, which is used to fabricate a low-capacitance silicon pixel detector array chip disclosed in Embodiment 1.

[0090] As Figure 8 shown, the method includes the following steps:

[0091] S100. Select a silicon wafer and divide the silicon wafer into a pixel unit array;

[0092] Select one side of the silicon wafer as the read surface, and the side opposite to the read surface as the incident surface.

[0093] As an implementation case of step S100, select an n-type silicon wafer with a thickness of 100 microns, divide it into 9 pixel units, in a 3*3 array, and the silicon wafer substrate corresponding to each pixel unit has a side length of 100 microns and a thickness of 300 microns.

[0094] S200. Inject a plurality of circular doping regions as protection electrodes in the surface layer of the read surface of the silicon wafer, and the protection electrodes correspond to the pixel units one by one.

[0095] As an example of step S200, inject n+ doped boron in the surface layer of the read surface to form a circular doping region. The electrode polarity of the circular doping region is the same as that of the subsequent cathode electrode doping, and it surrounds the outer periphery of the N-type doping region in the cathode electrode, can separate the connected cathode electrodes, is used for voltage division of the first electrode, and can prevent breakdown.

[0096] S300. Perform gettering oxidation on the read surface of the silicon wafer to form an oxide layer.

[0097] As an implementation case of step S300, form a whole-surface covering silicon dioxide layer on the read surface of the substrate through thermal oxidation or PECVD oxidation process.

[0098] S400. Through spin coating, photolithography, etching, and rinsing processes, a plurality of groove regions are etched on the oxide layer. The groove regions correspond to the pixel units one by one, and the protection electrodes surround the outer periphery of the corresponding groove regions. Each groove region includes a circular groove region.

[0099] S500. For each groove region, a doped region is implanted into the surface layer of the silicon wafer reading surface by ion implantation, and a conductive metal layer is formed on the surface of the silicon wafer reading surface. The doped region and the conductive metal layer cooperate to form a cathode electrode.

[0100] The protection electrode is in the shape of a circular ring, embedded in the reading surface of the substrate and surrounding the outer periphery of the cathode electrode, and is used to space adjacent cathode electrodes.

[0101] As an implementation case of step S500, in the circular groove region, a doped boron with a doping concentration of 1x10 19 cm -3 and a doping depth of 1 micron is implanted into the surface layer of the reading surface by ion implantation to form an N-type doped region. An aluminum plating layer is formed on the surface of the reading surface, and the aluminum plating layer is in contact with the N-type doped region to form a cathode electrode, which serves as a collection electrode (i.e., a readout electrode).

[0102] S600. A doped region is implanted into the surface layer of the silicon wafer incident surface by ion implantation, and a conductive metal layer is formed on the surface of the silicon wafer incident surface. The doped region and the conductive metal layer cooperate to form an anode electrode.

[0103] As an implementation case of step S600, on the entire incident surface, a doped boron with a doping concentration of 1x10 19 cm -3 and a doping depth of 0.5 micron is implanted into the surface layer of the incident surface by ion implantation to form a P-type doped region. An aluminum plating layer is formed on the surface of the incident surface, and the aluminum plating layer is in contact with the P-type doped region to form an anode electrode.

[0104] Considering the effect of potential voltage division between the anode electrode and the cathode electrode, the pattern of the cathode electrode is improved. Specifically, the groove regions etched on the oxide layer include a circular groove region and a plurality of triangular groove regions. The plurality of triangular groove regions are arranged at circumferential intervals and surround the outer periphery of the circular groove region. One side of each triangular groove region is close to the circular groove region.

[0105] The cathode electrode located in the circular groove region serves as a collection electrode; the cathode electrode located in the triangular groove region serves as a floating electrode for voltage division.

[0106] Give a specific case. The groove area further includes eight triangular groove areas, and each of the triangular groove areas is an isosceles triangular groove area with a base length of 10 micrometers and a height of 15 micrometers. The base of the triangular groove area is close to the circular groove area.

[0107] The above has detailedly shown and described the present invention through the drawings and preferred embodiments. However, the present invention is not limited to these disclosed embodiments. Based on the above-mentioned multiple embodiments, those skilled in the art can know that the code review means in the above different embodiments can be combined to obtain more embodiments of the present invention, and these embodiments are also within the protection scope of the present invention.

Claims

1. A low-capacitance silicon pixel detector array chip, characterized in that, Composed of a pixel unit array, each pixel unit includes: A substrate, the substrate being a silicon wafer substrate, one side of the substrate serving as a reading surface, and the side opposite to the reading surface serving as a receiving surface; An oxide layer, the oxide layer being formed on the reading surface of the substrate and etched with a groove region, the groove region including a circular groove region and a plurality of triangular groove regions, the plurality of triangular groove regions being arranged at circumferential intervals and surrounding the outer periphery of the circular groove region, the triangular groove regions being isosceles triangular groove regions, and the bottom sides of the triangular groove regions being close to the circular groove region; A cathode electrode, the cathode electrode being located within the groove region and embedded in the reading surface of the substrate for serving as a collecting electrode; A protection electrode, the protection electrode being in a circular ring shape, embedded in the reading surface of the substrate and surrounding the outer periphery of the cathode electrode for spacing the cathode electrodes between adjacent pixel units; An anode electrode, the anode electrode being embedded in the incident surface of the substrate and covering the entire incident surface of the substrate.

2. The low-capacitance silicon pixel detector array chip according to claim 1, wherein: The cathode electrode located within the circular groove region serves as a collecting electrode; The cathode electrode located within the triangular groove region serves as a floating electrode for voltage division.

3. The low-capacitance silicon pixel detector array chip according to any one of claims 1-2, characterized in that, The cathode electrode includes a first doped region implanted into the surface layer of the reading surface of the substrate and a first conductive metal layer covering the surface of the reading surface of the substrate, the first doped region being in contact and cooperation with the first conductive metal layer; The anode electrode includes a second doped region implanted into the surface layer of the incident surface of the substrate and a second conductive metal layer covering the surface of the incident surface of the substrate, the second doped region being in contact and cooperation with the second conductive metal layer; The protection electrode includes a third doped region implanted into the surface layer of the reading surface of the substrate.

4. The low-capacitance silicon pixel detector array chip according to claim 3, wherein, The thickness of the first doped region is greater than the thickness of the second doped region.

5. The low-capacitance silicon pixel detector array chip according to claim 3, characterized in that, The substrate is an N-type silicon wafer substrate; Correspondingly, the first doped region is a P-type doped region; Correspondingly, the third doped region is a P-type doped region; Correspondingly, the second doped region is an N-type doped region; Or, the substrate is a P-type silicon wafer substrate; Correspondingly, the first doped region is an N-type doped region; Correspondingly, the third doped region is an N-type doped region; Correspondingly, the second doped region is a P-type doped region.

6. The low-capacitance silicon pixel detector array chip according to claim 3, wherein: The substrate is a silicon wafer substrate with a thickness of 100 - 500 microns; The thickness of the first doping region is 0.1 to 5 micrometers, and the doping concentration is 1x10 19 cm -3 ; The thickness of the second doped region is 0.1 micrometer to 5 micrometers, and the doping concentration is 1x10 19 cm -3 ; The diameter of the circular groove region is 30 microns; The triangular groove region is an isosceles triangular groove region with a bottom side length of 10 microns and a height of 15 microns.

7. A manufacturing method of a low-capacitance silicon pixel detector array chip, characterized in that, A method for manufacturing a low-capacitance silicon pixel detector array chip as described in any one of claims 1 - 6, the method including: Selecting a silicon wafer and dividing the silicon wafer into a pixel unit array; Selecting one side of the silicon wafer as a reading surface, and the side opposite to the reading surface as an incident surface; Inject a plurality of circular doping regions into the surface layer of the reading surface of the silicon wafer as protection electrodes, and the protection electrodes correspond to the pixel units one by one; Perform gettering oxidation on the reading surface of the silicon wafer to form an oxide layer; Through spin coating, photolithography, etching, and rinsing processes, etch a plurality of groove regions on the oxide layer. The groove regions correspond to the pixel units one by one. The protection electrodes surround the outer periphery of the corresponding groove regions. Each groove region includes a circular groove region and a plurality of triangular groove regions. The plurality of triangular groove regions are arranged at circumferential intervals and surround the outer periphery of the circular groove region. The triangular groove regions are isosceles triangular groove regions, and the bottom sides of the triangular groove regions are close to the circular groove region; For each groove region, inject a doping region into the surface layer of the reading surface of the silicon wafer by ion implantation, and form a conductive metal layer on the surface of the reading surface of the silicon wafer. The doping region corresponding to the reading surface of the silicon wafer and the conductive metal layer corresponding to the reading surface of the silicon wafer cooperate to form a cathode electrode; Inject a doping region into the surface layer of the incident surface of the silicon wafer by ion implantation, and form a conductive metal layer on the surface of the incident surface of the silicon wafer. The doping region corresponding to the incident surface of the silicon wafer and the conductive metal layer corresponding to the incident surface of the silicon wafer cooperate to form an anode electrode.

8. The method for fabricating a low-capacitance silicon pixel detector array chip according to claim 7, wherein The cathode electrode located in the circular groove region serves as a collection electrode; The cathode electrode located in the triangular groove region serves as a floating electrode for voltage division.

9. The method for fabricating a low-capacitance silicon pixel detector array chip according to claim 7 or 8, characterized in that, The thickness of the doping region in the cathode electrode is greater than the thickness of the doping region in the anode electrode.

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