drive device

Abstract

A driving device includes a voltage regulator, a voltage generator, a first P-channel metal oxide semiconductor field effect transistor and a first N-channel metal oxide semiconductor field effect transistor. The voltage regulator is coupled between a first high voltage terminal and an output terminal of the driving device. The voltage regulator receives a first high voltage from the first high voltage terminal and reduces the first high voltage to generate a supply voltage. The voltage generator is coupled between a second high voltage terminal and the output terminal of the driving device. The voltage generator provides a reference voltage to the output terminal of the driving device, the reference voltage being substantially lower than the supply voltage. The first P-channel metal oxide semiconductor field effect transistor is coupled between the voltage regulator and the output terminal of the driving device, and the first N-channel metal oxide semiconductor field effect transistor is coupled between the output terminal of the driving device and a low voltage terminal.

Description

TECHNICAL FIELD

[0001] The present application relates to a driving technique, and more particularly, to a driving device without using an external capacitor. BACKGROUND

[0002] An integrated circuit (IC) includes transistors, such as complementary metal-oxide-semiconductor (CMOS) transistors, for implementing logic circuits. The integrated circuit is usually operated in different power modes, including a run (RUN), a standby (STANDBY), and a stop (STOP) mode, to achieve efficient power management. To reduce the wiring complexity, the integrated circuit receives a single power supply voltage to drive a load when the integrated circuit enters the run mode.

[0003] Figure 1 A schematic diagram of a prior art integrated circuit for driving a load. Figure 2 A waveform diagram of an input signal and nodes of a prior art integrated circuit for driving a load. Please refer to Figure 1 and Figure 2 The integrated circuit 1 includes a buffer 10, a P-channel metal-oxide-semiconductor field effect transistor 11, an N-channel metal-oxide-semiconductor field effect transistor 12, a voltage regulator 13, and conductive terminals 14 and 15. The conductive terminal 15 is coupled to a load 16, which has a parasitic capacitance. The voltage regulator 13 is coupled to a single power supply terminal, which has a voltage represented as VDDA. The voltage regulator 13 receives the voltage VDDA and converts it to a supply voltage VDDIO. In other words, the conductive terminal 14 has the voltage VDDIO. The voltages of the conductive terminals 14 and 15, the P-channel metal-oxide-semiconductor field effect transistor 11, and the N-channel metal-oxide-semiconductor field effect transistor 12 are the voltages of nodes A, B, C, and D, respectively. The buffer 10 receives an input signal IN to drive the P-channel metal-oxide-semiconductor field effect transistor 11 and the N-channel metal-oxide-semiconductor field effect transistor 12, which in turn charges or discharges the load 16. When the voltage of the conductive terminal 15 changes from logic "0" to logic "1", the P-channel metal-oxide-semiconductor field effect transistor 11 immediately receives the voltage VDDIO to generate a large driving current to drive the load 16. At the same time, the large driving current causes undershoot of the voltage of the conductive terminal 14, which causes the load 16 to read incorrect data. The value of the driving current depends on the resistance of the P-channel metal-oxide-semiconductor field effect transistor 11. The conductive terminal 14 has a voltage difference AV. The voltage difference AV is represented by equation (1).

[0004]

[0005] where t represents time, C represents the capacitance value of the external capacitor 17, T represents the integration time which depends on the capacitance value of the load 16, and I(t) represents the driving voltage which is a function of time. Due to the presence of large driving current, the recovery time of the voltage regulator 13 is long and the voltage of the conductive terminal 14 cannot be recovered to VDDIO in real time. In order to stabilize the voltage of the conductive terminal 14, the integrated circuit 1 requires a capacitor to maintain the voltage of the conductive terminal 14. Considering the area of the integrated circuit 1, any capacitor with a capacitance value in the order of micro-farad cannot be integrated in the integrated circuit 1. Therefore, the external capacitor 17 is used to reduce the voltage difference AV and avoid affecting the output voltage level of the integrated circuit 1. However, the external capacitor 17 will increase the material cost of the integrated circuit 1 and the space occupied by the entire module. SUMMARY

[0006] The present application provides a driving device which avoids coupling to any external capacitor to reduce the material cost of the entire module and the space occupied by the entire module.

[0007] In an embodiment of the present application, a driving device is provided, which comprises a voltage regulator, a voltage generator, a first P-channel metal oxide semiconductor field effect transistor and a first N-channel metal oxide semiconductor field effect transistor. The voltage regulator is coupled between a first high voltage terminal and an output terminal of the driving device, wherein the voltage regulator is used to receive a first high voltage of the first high voltage terminal and reduce the first high voltage to generate a supply voltage. The voltage generator is coupled between a second high voltage terminal and the output terminal of the driving device, wherein the voltage generator is used to provide a reference voltage to the output terminal of the driving device, the reference voltage being lower than the supply voltage. The first P-channel metal oxide semiconductor field effect transistor is coupled between the voltage regulator and the output terminal of the driving device, and the first N-channel metal oxide semiconductor field effect transistor is coupled between the output terminal of the driving device and a low voltage terminal.

[0008] Based on the above, the driving device provides the reference voltage to the output terminal of the driving device before the voltage regulator provides the supply voltage to the output terminal of the driving device to weaken the undershoot phenomenon. Therefore, the driving device can avoid coupling to any external capacitor to reduce the material cost of the entire module and the space occupied by the entire module. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 A schematic diagram of a prior art integrated circuit for driving a load.

[0010] Figure 2 A waveform diagram of an input signal and nodes of a prior art integrated circuit for driving a load.

[0011] Figure 3A schematic diagram of a drive device of a first embodiment of the present application.

[0012] Figure 4 A waveform chart of a signal, a first control signal, a second control signal, and a third control signal of a node of a drive device of a first embodiment of the present application.

[0013] Figure 5 A flowchart of charging a load by a drive device of a first embodiment of the present application.

[0014] Figure 6 A flowchart of discharging a load by a drive device of a first embodiment of the present application.

[0015] Figure 7 A schematic diagram of a drive device of a second embodiment of the present application.

[0016] Figure 8 A waveform chart of a signal, a first control signal, a second control signal, and a third control signal of a node of a drive device of a second embodiment of the present application.

[0017] BRIEF DESCRIPTION OF DRAWINGS

[0018] 1…integrated circuit

[0019] 10…buffer

[0020] 11…P-channel metal oxide semiconductor field effect transistor

[0021] 12…N-channel metal oxide semiconductor field effect transistor

[0022] 13…voltage regulator

[0023] 14…conductive terminal

[0024] 15…conductive terminal

[0025] 16…load

[0026] 17…external capacitor

[0027] 2…drive device

[0028] 20…voltage regulator

[0029] 21…voltage generator

[0030] 210…second N-channel metal oxide semiconductor field effect transistor

[0031] 211…third N-channel metal oxide semiconductor field effect transistor

[0032] 212…first electronic switch

[0033] 213 fourth N-channel metal oxide semiconductor field effect transistor

[0034] 214 second electronic switch

[0035] 215 signal controller

[0036] 216 third electronic switch

[0037] 217 fourth electronic switch

[0038] 218 second P-channel metal oxide semiconductor field effect transistor

[0039] 22 first N-channel metal oxide semiconductor field effect transistor

[0040] 23 first P-channel metal oxide semiconductor field effect transistor

[0041] 24 conductive terminal

[0042] 25 output terminal

[0043] 26 signal buffer

[0044] 3 load

[0045] VDDA voltage

[0046] VDDIO supply voltage

[0047] A, B, C, D, E, F node

[0048] IN input signal

[0049] VDDA1 first high voltage

[0050] VDDA2 second high voltage

[0051] C1 first control signal

[0052] C2 second control signal

[0053] C3 third control signal

[0054] VREF reference voltage

[0055] T1, T2 period

[0056] S10, S11, S12, S13, S14 step

[0057] B1 high bias

[0058] S1, S2 signal

[0059] B2 low bias DETAILED DESCRIPTION

[0060] Embodiments of the application will be further described with reference to the following text in conjunction with the associated drawings. Whenever possible, like reference numerals are used in the drawings and the description to refer to the same or like parts. In the drawings, the shape and thickness of components can be exaggerated for the sake of clarity. It is to be understood that the components not specifically shown or described in the drawings or the specification can take forms well known to those skilled in the art. Various changes and modifications can be made to the embodiments described and illustrated herein, based on the teachings of the present application.

[0061] Unless specifically stated otherwise, some of the conditions or words, e.g., "can," "could," "might," or "may," used in the specification are intended to convey that certain embodiments of the present application can include, possibly among other things, that the feature, component, or step can not be needed, or can be optional. In other embodiments, the feature, component, or step can be required.

[0062] Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular component, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" are not necessarily referring to the same embodiment. Furthermore, the described components, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0063] In this specification, certain terms have been used for brevity, clarity and understanding. However, no unnecessary limitations are to be implied therefrom because such terms are used for descriptive purposes only and are intended to be broadly construed. The description and claims can use "including," "comprising," "carrying," "containing," or "having," and their derivatives, to mean "including but not limited to". It is to be understood that other embodiments can be utilized and operational changes can be made without departing from the scope of the present application. Accordingly, the specification and drawings are to be regarded in an illustrative, rather than a restrictive, sense.

[0064] The present disclosure is described in particular with the following examples which are intended to be illustrative only since modifications of detail can be made thereto by those skilled in the art without departing from the spirit and scope of the disclosure. The scope of the disclosure is to be accorded the broadest interpretation of the appended claims so as to encompass all equivalent methods and devices. Throughout the specification and claims, unless the context clearly dictates otherwise, the meaning of "a," "an," and "the" include one or at least one, and the meaning of "including" includes but is not limited to. Additionally, as used in this disclosure the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Also, the use of "adapted to" herein is intended to cover the structure described herein, whether or not the structure is so adapted. Furthermore, the use of "in" as used herein includes "in" and "on." The words "comprise," "comprising," "include," "including," and "contains," "containing," or variations thereof, as used herein, are intended to be equivalent to the word "comprising" and are intended to not exclude the presence of other elements or components. Throughout the specification and claims, unless the context clearly dictates otherwise, the meaning of "about" includes ±10% and preferably includes ±5% of the value or range recited. Furthermore, numerical quantities given herein are approximate, meaning that the term "about" can be inferred even if not expressly stated. When numerical ranges are provided herein, the range is intended to include all values and sub-ranges within the range, unless the context clearly indicates otherwise. For example, every numerical value is a range including the value and endpoints. The disclosure is not limited to the embodiments set forth herein, but includes all changes, modifications and alterations of the embodiments within the scope of the claims.

[0065] As used herein, the terms "substantially," "around," "about," or "approximately" shall generally mean within 20%, more preferably within 10%, of a given value or range. Furthermore, numerical quantities given herein are approximate, meaning that the term "about" can be inferred even if not expressly stated. When numerical ranges are provided herein, the range is intended to include all values and sub-ranges within the range, unless the context clearly indicates otherwise. For example, every numerical value is a range including the value and endpoints.

[0066] In the following description, a driving device is provided. Before a voltage regulator provides a supply voltage to an output terminal of the driving device, the driving device provides a reference voltage to the output terminal of the driving device to weaken the phenomenon of voltage undershoot. Therefore, the driving device can avoid coupling to any external capacitor to reduce the material cost of the whole module and the space occupied by the whole module.

[0067] Figure 3A schematic diagram of a driving device of a first embodiment of the present application. Figure 4 A waveform diagram of a signal of a node of a driving device, a first control signal, a second control signal and a third control signal of a first embodiment of the present application. Figure 5 A flowchart of a driving device charging a load of a first embodiment of the present application. Please refer to Figure 3 Figure 4 Figure 5 A first embodiment of the present application is introduced as follows. In the first embodiment, a driving device 2 is coupled to a load 3, and the load 3 has a parasitic capacitance. The driving device 2 can be integrated in an integrated circuit. The driving device 2 includes a voltage regulator 20, a voltage generator 21, a first N-channel metal-oxide-semiconductor field-effect transistor 22, a first P-channel metal-oxide-semiconductor field-effect transistor 23, a conductive terminal 24 and an output terminal 25. The voltage regulator 20 can be implemented as a low-dropout regulator (LDO), but the present application is not limited thereto. The output terminal 25 can be a digital output terminal or a serial peripheral interface (SPI), but the present application is not limited thereto. The voltage regulator 20 is coupled to a first high-voltage terminal and the conductive terminal 24, and a first high voltage of the first high-voltage terminal is denoted as VDDA1. The voltage generator 21 is coupled to a second high-voltage terminal and the output terminal 25, and a second high voltage of the second high-voltage terminal is denoted as VDDA2. The first high voltage VDDA1 is substantially equal to or different from the second high voltage VDDA2. The second high-voltage terminal can be replaced by the first high-voltage terminal. The first high-voltage terminal and the second high-voltage terminal can be external voltage sources or implemented by external capacitors. The output terminal 25 of the driving device 2 is coupled to the load 3. Voltages of nodes E and F represent voltages of the conductive terminal 24 and the output terminal 25, respectively. The first N-channel metal-oxide-semiconductor field-effect transistor 22 is coupled between the output terminal 25 and a low-voltage terminal. The low-voltage terminal can be a ground terminal, but the present application is not limited thereto. A source and a drain of the first N-channel metal-oxide-semiconductor field-effect transistor 22 can be coupled to the low-voltage terminal and the output terminal 25 of the driving device 2, respectively. Alternatively, the drain and the source of the first N-channel metal-oxide-semiconductor field-effect transistor 22 can be coupled to the low-voltage terminal and the output terminal 25, respectively. The first P-channel metal-oxide-semiconductor field-effect transistor 23 is coupled between the voltage regulator 20 and the output terminal 25. The first P-channel metal-oxide-semiconductor field-effect transistor 23 and the voltage regulator 20 are coupled to the conductive terminal 24 together. A source and a drain of the first P-channel metal-oxide-semiconductor field-effect transistor 23 can be coupled to the voltage regulator 20 and the output terminal 25, respectively. Alternatively, the drain and the source of the first P-channel metal-oxide-semiconductor field-effect transistor 23 can be coupled to the voltage regulator 20 and the output terminal 25, respectively.

[0068] ​​The charging process of the driving device 2 is described as follows. In step S10, the voltage regulator 20 receives the first high voltage VDDA1 of the first high voltage terminal and lowers the first high voltage VDDA1 to generate the supply voltage VDDIO. The supply voltage is substantially lower than the first high voltage VDDA1. For example, the supply voltage VDDIO ranges from 1.4 to 1.8 volts, and the first high voltage VDDA1 can be 3.3 volts. The voltage generator 21 receives the first control signal C1. The gate of the first N-channel metal oxide semiconductor field effect transistor 22 receives the second control signal C2 corresponding to the first control signal C1. The gate of the first P-channel metal oxide semiconductor field effect transistor 23 receives the third control signal C3 corresponding to the second control signal C2. The first control signal C1, the second control signal C2, and the third control signal C3 can be digital signals, but the present application is not limited thereto. In step S10, the first control signal C1, the second control signal C2, the third control signal C3, and the node F are logic "0", logic "1", logic "1", and logic "0", respectively. The first control signal C1 controls the voltage generator 21 to stop charging the load 3. The second control signal C2 turns on the first N-channel metal oxide semiconductor field effect transistor 22. The third control signal C3 turns off the first P-channel metal oxide semiconductor field effect transistor 23.

[0069] In step S11, when the voltage of the first control signal C1 changes from logic "0" to logic "1", the first control signal C1 and the second high voltage VDDA2 of the second high voltage terminal drive the voltage generator 21 to provide the reference voltage VREF to the output terminal 25 of the driving device 2, and spend a time period T1 to charge the load 3 to the reference voltage VREF via the output terminal 25. When the first control signal C1 and the second high voltage VDDA2 of the second high voltage terminal drive the voltage generator 21 to provide the reference voltage VREF to the output terminal 25 of the driving device 2, and charge the load 3 to the reference voltage VREF via the output terminal 25, the second control signal C2 turns off the first N-channel metal oxide semiconductor field effect transistor 22, and the third control signal C3 turns off the first P-channel metal oxide semiconductor field effect transistor 23. In the time period T1, the supply voltage VDDIO is not affected by turning off the first P-channel metal oxide semiconductor field effect transistor 23. The reference voltage VREF is substantially higher than the low voltage of the low voltage terminal and lower than the supply voltage VDDIO. In fact, the reference voltage VREF is close to the supply voltage VDDIO. In step S11, the voltages of the second control signal C2 and the third control signal C3 are logic "0" and logic "1", respectively.

[0070] In step S12, after the reference voltage VREF is supplied to the output terminal 25 of the driving device 2, the second control signal C2 turns off the first N-channel metal oxide semiconductor field effect transistor 22, the third control signal C3 turns on the first P-channel metal oxide semiconductor field effect transistor 23, the supply voltage VDDIO is supplied to the output terminal 25 of the driving device 2 via the first P-channel metal oxide semiconductor field effect transistor 23, and the load 3 is charged to the supply voltage VDDIO via the first P-channel metal oxide semiconductor field effect transistor 23 and the output terminal 25. In step S12, the first control signal C1, the second control signal C2, the third control signal C3 and the voltage of the node F are logic "1", logic "0", logic "0" and logic "1", respectively. In step S12, because the reference voltage VREF is close to the supply voltage VDDIO, the driving current through the first P-channel metal oxide semiconductor field effect transistor 23 is very small. Although the voltage of the node E drops by the voltage difference AV immediately because of the very small driving current, the voltage difference AV is small, and the voltage variation of the node E is also very small. Therefore, the voltage of the node E can meet the voltage specification of the load 3. The voltage of the node F is logic "1" for a period T2. Before the voltage regulator 20 supplies the supply voltage VDDIO to the output terminal 25 of the driving device 2, the driving device 2 supplies the reference voltage VREF to the output terminal 25 of the driving device 2 to weaken the condition of voltage undershoot of the conductive terminal 24. Therefore, the driving device 2 can be free from coupling any external capacitor, thereby reducing the material cost of the whole module and the space occupied by the whole module.

[0071] Figure 6 The flow chart of discharging the load by the driving device of the first embodiment of the present application. Please refer to Figure 3 、 Figure 4 and Figure 6, the discharging process of the driving device 2 is described as follows. In step S13, when the voltage of the first control signal CI changes from logic "1" to logic "0", the first control signal CI controls the voltage generator 21 to stop providing the reference voltage VREF to the output terminal 25 of the driving device 2, and to stop charging the load 3. When the first control signal CI controls the voltage generator 21 to stop providing the reference voltage VREF and to stop charging the load 3, the second control signal C2 turns off the first N-channel metal oxide semiconductor field effect transistor 22, and the third control signal C3 turns off the first P-channel metal oxide semiconductor field effect transistor 23, to stop providing the supply voltage VDDIO to the output terminal 25, and to stop charging the load 3 to the supply voltage VDDIO. In step S13, the second control signal C2, the third control signal C3 and the voltage of the node F are logic "0", logic "1" and logic "1", respectively. The first N-channel metal oxide semiconductor field effect transistor 22 and the first P-channel metal oxide semiconductor field effect transistor 23 are not turned on at the same time, to avoid the voltage level of the output terminal 25 being unstable.

[0072] After step S13, step S14 is performed. In step S14, when the first control signal CI controls the voltage generator 21 to stop providing the reference voltage VREF and to stop charging the load 3, the second control signal C2 turns on the first N-channel metal oxide semiconductor field effect transistor 22, and discharges the load 3 to a low voltage via the output terminal 25, and the third control signal C3 turns off the first P-channel metal oxide semiconductor field effect transistor 23, to stop providing the supply voltage VDDIO and to stop charging the load 3 to the supply voltage VDDIO. In other words, the voltage of the node F is logic "0". Therefore, during the operation of the driving device 2, the voltage of the output terminal 25 is a digital voltage. Furthermore, step S13 is ideally negligible. If the same result can be achieved, it is not necessary to perform step S13. Figures 5 to 6 The order of the steps in the flowchart shown is not necessarily performed, and Figures 5 to 6 The steps shown are not necessarily performed consecutively, i.e. other steps can be inserted therebetween.

[0073] In another embodiment of the present application, the driving device 2 can further comprise a signal buffer 26 coupled to the gates of the first N-channel metal oxide semiconductor field effect transistor 22 and the first P-channel metal oxide semiconductor field effect transistor 23. The signal buffer 26 receives the first control signal CI and inversely adjusts the waveform of the first control signal CI to generate the third control signal C3 and the second control signal C2.

[0074] Figure 7 A schematic diagram of a driving device according to a second embodiment of the present application. Figure 8Waveform diagrams of the signals, the first control signal, the second control signal and the third control signal for the nodes of the driving device of the second embodiment of the present application. Please refer to Figure 7 With Figure 8 The second embodiment of the present application is introduced as follows. The second embodiment differs from the first embodiment in the voltage generator 21. In the second embodiment, the voltage generator 21 can include a second N-channel metal oxide semiconductor field effect transistor 210, a third N-channel metal oxide semiconductor field effect transistor 211, a first electronic switch 212, a fourth N-channel metal oxide semiconductor field effect transistor 213, a second electronic switch 214, a signal controller 215, a third electronic switch 216 and a fourth electronic switch 217. The third N-channel metal oxide semiconductor field effect transistor 211 serves as a source follower. The second N-channel metal oxide semiconductor field effect transistor 210 and the third N-channel metal oxide semiconductor field effect transistor 211 form a current mirror. The first electronic switch 212, the second electronic switch 214, the third electronic switch 216 and the fourth electronic switch 217 can be channel metal oxide semiconductor field effect transistors or bipolar junction transistors, but the present application is not limited thereto. The drain of the second N-channel metal oxide semiconductor field effect transistor 210 is coupled to the second high voltage terminal. The gate of the second N-channel metal oxide semiconductor field effect transistor 210 is coupled to its drain. The source of the second N-channel metal oxide semiconductor field effect transistor 210 is coupled to the voltage regulator 20. The drain of the third N-channel metal oxide semiconductor field effect transistor 211 is coupled to the second high voltage terminal. The source of the third N-channel metal oxide semiconductor field effect transistor 211 is coupled to the output terminal 25. The first electronic switch 212 is coupled between the gate of the second N-channel metal oxide semiconductor field effect transistor 210 and the gate of the third N-channel metal oxide semiconductor field effect transistor 211. The drain of the fourth N-channel metal oxide semiconductor field effect transistor 213 is coupled to the output terminal 25 and the source of the third N-channel metal oxide semiconductor field effect transistor 211. The source of the fourth N-channel metal oxide semiconductor field effect transistor 213 is coupled to the low voltage terminal. The second electronic switch 214 is coupled between the gate of the fourth N-channel metal oxide semiconductor field effect transistor 213 and a high bias terminal, the high bias of which is denoted by B1. The signal controller 215 is coupled to the control terminals of the first electronic switch 212 and the second electronic switch 214. The third electronic switch 216 is coupled between the low voltage terminal and the gate of the third N-channel metal oxide semiconductor field effect transistor 211. The control terminal of the third electronic switch 216 is coupled to the signal controller 215.

[0075] In operation of the voltage generator 21, the second N-channel metal oxide semiconductor field effect transistor 210 receives the supply voltage VDDIO, and the signal controller 215 receives the first control signal C1. The signal controller 215 controls the signals of the first and second electronic switches 212 and 214 as S1. The signal controller 215 controls the signals of the third and fourth electronic switches 216 and 217 as S2. When the voltage of the first control signal C1 changes from logic "0" to logic "1", the first control signal C1 drives the signal controller 215 to turn on the first and second electronic switches 212 and 214, and to turn off the third and fourth electronic switches 216 and 217. In other words, when the voltage of the first control signal C1 changes from logic "0" to logic "1", the voltages of the signals S1 and S2 are logic "1" and logic "0", respectively. When the first control signal C1 drives the signal controller 215 to turn on the first and second electronic switches 212 and 214, the second high voltage VDDA2 and the high bias B1 of the high bias terminal drive the second N-channel metal oxide semiconductor field effect transistor 210, the third N-channel metal oxide semiconductor field effect transistor 211 and the fourth N-channel metal oxide semiconductor field effect transistor 213 to provide the reference voltage VREF, and to charge the load 3 to the reference voltage VREF via the first and second electronic switches 212 and 214. By adjusting the drain current, the channel length and the channel width of the second and third N-channel metal oxide semiconductor field effect transistors 210 and 211, the gate-source voltage of the second N-channel metal oxide semiconductor field effect transistor 210 can be substantially lower than the gate-source voltage of the third N-channel metal oxide semiconductor field effect transistor 211, so that the output terminal 25 cannot charge the conductive terminal 24. In practice, the gate-source voltage of the second N-channel metal oxide semiconductor field effect transistor 210 is close to the gate-source voltage of the third N-channel metal oxide semiconductor field effect transistor 211.

[0076] When the first control signal C1 drives the signal controller 215 to turn off the first and second electronic switches 212 and 214, the first control signal C1 drives the signal controller 215 to turn on the third and fourth electronic switches 216 and 217, and the low voltage drives the third and fourth N-channel metal oxide semiconductor field effect transistors 211 and 213 to stop providing the voltage, and to stop charging the load 3 via the third and fourth electronic switches 216 and 217. In other words, when the first control signal C1 drives the signal controller 215 to turn off the first and second electronic switches 212 and 214, the voltages of the signals S1 and S2 are logic "0" and logic "1", respectively.

[0077] In some embodiments of the present application, the driving device 2 can further include a second P-channel metal oxide semiconductor field effect transistor 218 coupled between the second high voltage terminal and the drain of the second N-channel metal oxide semiconductor field effect transistor 210. The gate of the second P-channel metal oxide semiconductor field effect transistor 218 receives a low bias voltage B2 to keep the second P-channel metal oxide semiconductor field effect transistor 218 on. Thus, the second N-channel metal oxide semiconductor field effect transistor 210 receives the second high voltage VDDA2 through the second P-channel metal oxide semiconductor field effect transistor 218.

[0078] The above description is only the preferred embodiment of the present application, not intended to limit the scope of the present application. Therefore, any changes and modifications made in accordance with the shape, structure, features and spirit described in the claims of the present application should be included in the claims of the present application.

Claims

1. A drive device characterized by comprising: Comprising: a voltage regulator coupled between a first high voltage terminal and an output terminal of the driving device, wherein the voltage regulator is configured to receive a first high voltage from the first high voltage terminal and to reduce the first high voltage to generate a supply voltage; a voltage generator coupled between a second high voltage terminal and the output terminal of the driving device, wherein the voltage generator is configured to provide a reference voltage to the output terminal of the driving device, the reference voltage being lower than the supply voltage; a first P-channel metal-oxide-semiconductor field-effect transistor coupled between the voltage regulator and the output terminal of the driving device; and a first N-channel metal-oxide-semiconductor field-effect transistor coupled between the output terminal of the driving device and a low voltage terminal; wherein the voltage generator comprises: a second N-channel metal-oxide-semiconductor field-effect transistor coupled between the second high voltage terminal and the voltage regulator; a third N-channel metal-oxide-semiconductor field-effect transistor coupled between the second high voltage terminal and the output terminal of the driving device; a first electronic switch coupled between the second N-channel metal-oxide-semiconductor field-effect transistor and the third N-channel metal-oxide-semiconductor field-effect transistor; a fourth N-channel metal-oxide-semiconductor field-effect transistor coupled between the output terminal of the driving device, the third N-channel metal-oxide-semiconductor field-effect transistor and the low voltage terminal; a second electronic switch coupled between the fourth N-channel metal-oxide-semiconductor field-effect transistor and a high bias voltage terminal; and a signal controller coupled to control terminals of the first electronic switch and the second electronic switch. Further comprising a signal buffer coupled to the first N-channel metal-oxide-semiconductor field-effect transistor.

2. The drive apparatus according to claim 1, wherein The voltage generator further comprises:

3. The drive apparatus according to claim 1, wherein a third electronic switch coupled between the low voltage terminal and the third N-channel metal-oxide-semiconductor field-effect transistor, a control terminal of the third electronic switch being coupled to the signal controller; and a fourth electronic switch coupled between the low voltage terminal and the fourth N-channel metal-oxide-semiconductor field-effect transistor, a control terminal of the fourth electronic switch being coupled to the signal controller. Further comprising a second P-channel metal-oxide-semiconductor field-effect transistor coupled between the second high voltage terminal and the second N-channel metal-oxide-semiconductor field-effect transistor.

4. The drive apparatus according to claim 1, wherein The output terminal is a digital output terminal, a voltage on the digital output terminal being a digital voltage.

5. The drive apparatus according to claim 1, wherein The first high voltage of the first high voltage terminal is equal to a second high voltage of the second high voltage terminal.

6. The drive apparatus according to claim 1, wherein ​

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