Dcoc calibration circuit and method for xgs-pon bm-la

Abstract

The application provides a low-cost design scheme suitable for common-mode recovery of an XGS-PON OLT BM-LA. A DCOC module calibration circuit is composed of a low-pass filter, an amplifier, a comparator, a digital controller and a current differential DAC. The low-pass filter and the amplifier respectively extract and scale the DC offset; the comparator distinguishes the polarity of the DC offset; the digital controller increases or decreases the output value of the current differential DAC according to the comparison result of the CMP until the DC offset calibration is completed.

Description

Technical Field

[0001] The present invention relates to a direct current offset (DCOC) calibration circuit and method for a burst mode limiting amplifier (BM-LA) of a 10G passive optical network receiver (XGS-PON). Background Art

[0002] The patent application of this invention is a continuation application of CN2022108300371. Based on CN2022108300371, a DC offset calibration circuit and method for a burst mode limiting amplifier of a 10G passive optical network receiver are further proposed.

[0003] Statement: To avoid duplication and save space, the contents of CN2022108300371 are deemed to be part of the description of this application, and some contents will not be repeated in this application. The inventor / applicant reserves the right to incorporate all or part of the contents of CN2022108300371 into the present application documents by reference.

[0004] Existing Gigabit Passive Optical Network (GPON / XGS-PON) OLT receivers primarily consist of modules such as an avalanche photodiode (APD), a burst-mode transimpedance amplifier (BM-TIA), and a burst-mode limiting amplifier (BM-LA). In traditional simple AC coupling, the common-mode recovery time of a BM-LA receiver and the signal's low-frequency energy loss are mutually constrained. Traditional direct current offset calibration (DCOC) feedback loops typically have loop bandwidths in the MHz or even kHz range, resulting in calibration times of tens to hundreds of microseconds. However, the XGS-PON protocol's long-term target for common-mode recovery time is less than 25.6ns. This poses significant challenges to high-speed common-mode recovery and offset calibration in BM-LA designs.

[0005] Existing DCOC loops require a clock source up to 6.25 GHz, and both the digital circuits and digital-to-analog converters (DACs) in the DCOC loop must operate at 6.25 GHz. This makes the design extremely difficult, demanding, and expensive, making it unsuitable for low-cost XGS-PON receivers. The high-speed digital DCOC loop described in Chen KC, Emami AA (25-Gb / s avalanche photodetector-based burst-mode optical receiver with 2.24-ns reconfiguration time in 28-nm CMOS [J]. IEEE Journal of Solid-State Circuits, vol. 54, pp. 1–12, 2019) requires advanced processing and is costly. Summary of the Invention

[0006] Statement: The patent application of this invention is a continuation application based on CN2022108300371. To avoid duplication of content, some contents will not be repeated in this application. The contents in CN2022108300371 are deemed to be part of the description of this application. The inventor / applicant reserves the right to incorporate all or part of the contents in CN2022108300371 into the present application documents by reference.

[0007] The present invention aims to provide a low-cost design for a DC offset calibration circuit for XGS-PON OLT BM-LA. The proposed DCOC calibration circuit utilizes a single-pass CNC calibration method, with DC offset calibration performed only when the chip is powered on or the system is idle. After the single calibration, the current-mode DAC is locked, and the remaining circuits in the calibration loop are disabled to reduce chip power consumption.

[0008] The specific technical solution for achieving the purpose of the present invention is:

[0009] A DC offset calibration (DCOC) feedback loop for a burst mode limiting amplifier (BM-LA) in a 10G passive optical network (XG-PON) receiver is disclosed. The fast common-mode recovery circuit for the burst mode limiting amplifier in the 10G passive optical network receiver includes a dynamic time constant control unit (RC_CONTROL), a burst mode limiting amplifier (BM-LA), and a DC offset calibration circuit (DCOC).

[0010] A dynamic time constant control unit (RC_CONTROL) has signal input terminals In+ and In-, which are respectively connected to the signal input terminal of a burst mode limiting amplifier (BM-LA) through two identical capacitors C. A first resistor R and a first controllable switch are connected in parallel between the signal input terminal In+ of the dynamic time constant control unit (RC_CONTROL) and the input common-mode voltage terminal through the capacitor C. A second resistor R and a second controllable switch are connected in parallel between the signal input terminal In- of the dynamic time constant control unit (RC_CONTROL) and the input common-mode voltage terminal through the capacitor C. Control terminals of the first controllable switch and the second controllable switch are both connected to an OR gate (OR) circuit, and two input terminals of the OR gate (OR) circuit are respectively connected to a reset terminal (RST, Reset) and a DOC_ON signal terminal of a DC offset calibration (DCOC) feedback loop.

[0011] The DCOC module calibration circuit consists of a low-pass filter, amplifier, comparator, digital controller, and current differential DAC. The low-pass filter and amplifier extract and scale the DC offset, respectively; the comparator determines the polarity of the DC offset; and the digital controller increases or decreases the output value of the current differential DAC based on the comparator's comparison result until DC offset calibration is complete.

[0012] The output signal of the dynamic time constant control unit (RC_CONTROL) is transmitted to a burst mode limiting amplifier, which is composed of a first operational amplifier, a second operational amplifier, a third operational amplifier, and a fourth operational amplifier connected in sequence.

[0013] The output signal of the burst mode limiting amplifier (BM-LA) is output to the low-pass filter input of the DC offset calibration circuit (DCOC). After low-pass filtering, it is output to the amplifier and comparator in sequence. The output signal of the comparator is transmitted to the input of the digital controller.

[0014] The input signal of the current differential DAC comes from the output of the first operational amplifier of the burst mode limiting amplifier (BM-LA). The output signal of the current differential DAC is also transmitted to the digital controller. The digital controller controls the operating state of the dynamic time constant control unit (RC_CONTROL) through an OR gate circuit.

[0015] The digital controller has a DOC_ON port, which is connected to one of the inputs of the OR gate of the dynamic time constant control unit (RC_CONTROL). Taking into account the characteristics of burst systems, calibration is initiated by setting DOC_ON to 1 and shorting the resistor in RC_CONTROL. This operation significantly attenuates the input signal to the burst mode limiting amplifier (BM-LA), significantly reducing input signal interference with the DC offset calibration loop and simplifying the LPF design. After calibration, the digital controller Dig locks the DAC value and sets DOC_ON to 0, shutting down all circuits in the DCOC loop except the DAC.

[0016] The inventors have thus far elaborated in detail the working principle, technical solutions, and technical effects of the present invention. Any matters not described in detail in this specification are prior art known to those skilled in the art and should not be considered as insufficient disclosure of the invention by the present specification.

[0017] In addition, abbreviations not specifically described in this application are all common abbreviations in the fields of optical communications and electronic science. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 : BM-LA DCOC block diagram of the present invention.

[0019] Figure 2 : BM-LA DCOC specific circuit diagram of the present invention.

[0020] Figure 3 : Small signal response of the DCOC comparator when the input signal is transmitted to the comparator under different conditions. DETAILED DESCRIPTION

[0021] To facilitate understanding of the present invention, the technical solutions of the present invention are specifically described below with reference to examples.

[0022] A DC offset calibration (DCOC) feedback loop for a burst mode limiting amplifier (BM-LA) in a 10G passive optical network (XGS-PON) receiver is disclosed. The fast common-mode recovery circuit for the burst mode limiting amplifier in the 10G passive optical network receiver includes a dynamic time constant control unit (RC_CONTROL), a burst mode limiting amplifier (BM-LA), and a DC offset calibration circuit (DCOC).

[0023] A dynamic time constant control unit (RC_CONTROL) has signal input terminals In+ and In-, each connected to a signal input terminal of a burst mode limiting amplifier (BM-LA) via two identical capacitors C. A first resistor R and a first controllable switch are connected in parallel between the signal input terminal In+ of the dynamic time constant control unit (RC_CONTROL) and the input common-mode voltage terminal via capacitor C. A second resistor R and a second controllable switch are connected in parallel between the signal input terminal In- of the dynamic time constant control unit (RC_CONTROL) and the input common-mode voltage terminal via capacitor C. Control terminals of the first and second controllable switches are both connected to an OR gate (OR) circuit, the two signal input terminals of which are connected to a reset terminal (RST, Reset) and a DOC_ON terminal of a DC offset correction (DCOC) feedback loop, respectively. Extremely shortening the time constant of the RC circuit is achieved by applying a high-level signal (i.e., RST = 1) to the reset terminal (RST, Reset).

[0024] like Figure 1 As shown in Figure 1, the DCOC module calibration circuit consists of a low-pass filter (LPF), an amplifier (F), a comparator (CMP), a digital controller (DIG), and a current differential DAC. The low-pass filter (LPF) and amplifier (F) extract and scale the DC offset, respectively; the comparator (CMP) determines the polarity of the DC offset; and the digital controller (DIG) increases or decreases the output value of the current differential DAC based on the comparison result of the comparator (CMP) until DC offset calibration is complete.

[0025] In the present invention, the digital controller DIG specifically selects a digital binary state machine to implement the above functions. The digital binary state machine is well known to those skilled in the art.

[0026] The output signal of the dynamic time constant control unit (RC_CONTROL) is transmitted to the burst mode limiting amplifier.

[0027] Figure 1 The specific DC offset calibration circuit (DCOC) in Figure 2 As shown, the burst mode limiting amplifier comprises a first operational amplifier 1st, a second operational amplifier 2st, a third operational amplifier 3st, and a fourth operational amplifier 4st, connected in sequence. The output signal of the first operational amplifier 1st is also transmitted to the input of a current differential DAC, and the output signal of the current differential DAC is transmitted to a digital controller DIG. The structure of the current differential DAC is well known in the art.

[0028] The low-pass filter (LPF) is an RC-structured low-pass filter. Resistors R are connected in series to both input terminals IN+ and IN-, followed by a capacitor C in parallel. Preferably, R = 40 kΩ and C = 10 pF. The signals at the input terminals IN+ and IN- of the low-pass filter (LPF) are derived from the output of the fourth operational amplifier (4st) of the burst mode limiting amplifier (BM-LA).

[0029] The output signal of the burst mode limiting amplifier (BM-LA) is output to the input end of the low-pass filter LPF of the DC offset calibration circuit (DCOC). After low-pass filtering, it is output to the amplifier F and the comparator CMP in sequence. The output signal of the comparator CMP is transmitted to the input end of the digital controller DIG.

[0030] The input signal of the current differential DAC comes from the output of the first operational amplifier (1st) of the burst mode limiting amplifier (BM-LA). The output signal of the current differential DAC is also transmitted to the digital controller DIG. The digital controller DIG controls the operating state of the dynamic time constant control unit (RC_CONTROL) through an OR gate (OR) circuit.

[0031] The main design parameters of the DCOC circuit are shown in Table 1.

[0032] Table 1 Main design parameters of DCOC circuit

[0033] Module Parameters or indicators LPF bandwidth <![CDATA[f LPF =200kHz]]> amplifier F=2,equivalent input offset<2mV Comparator Equivalent input offset <4mV Dig Digital binary state machine DAC 6-bit current DAC Operating frequency 2MHz

[0034] Taking into account the characteristics of burst systems, calibration starts by setting DOC_ON to 1 and shorting the resistor in RC_CONTROL. This significantly attenuates the input signal to the burst-mode limiting amplifier (BM-LA), significantly reducing input signal interference with the DC offset calibration loop and simplifying the LPF design. After calibration, the digital controller Dig locks the DAC value, sets DOC_ON to 0, and shuts down all circuits in the DCOC loop except the DAC, reducing overall circuit power consumption.

[0035] Traditional continuous-mode DCOC feedback loops cannot meet the required 25.6ns operating speed. To reduce chip costs, the DCOC calibration circuit in this invention uses a single-shot CNC calibration method. DC offset calibration is performed only when the chip is powered on or the system is idle. After the single calibration, the current-mode DAC is locked, and the remaining circuits in the calibration loop are shut down to reduce chip power consumption.

[0036] Figure 3 The small signal response of the input signal transmitted to the DCOC comparator under different conditions is as follows:

[0037] 1) When DCOC is enabled, DOC_ON is always 0, meaning DCOC does not participate in time constant control. To make the input signal's effect on the comparator less than 0dB, the bandwidth of the low-pass filter (LPF) must be as low as 1kHz.

[0038] 2) When DCOC is enabled, DOC_ON is set to 1, which resets RC_CONTROL. Even if the LPF bandwidth is increased 200 times (200 kHz), the input signal still experiences over 20dB of attenuation when it reaches the comparator. Therefore, by employing collaborative design, the LPF bandwidth can be widened from 1 kHz to 200 kHz, reducing the chip area occupied by the LPF circuit by 200 times and lowering chip costs.

[0039] The simulation results demonstrate the effectiveness of the fast common-mode recovery and offset calibration circuit. It takes only 14ns to restore the input common-mode level to 99.99%, and the DCOC loop is simple and easy to implement.

[0040] As described above, in the present invention, due to the working mechanism of the OR gate (OR) circuit, the level of the DOC_ON terminal of the DC offset calibration (DCOC) feedback loop will not affect the working mechanism and performance of the dynamic time constant control unit (RC_CONTROL) regarding fast common mode recovery. Similarly, the level of the RST terminal will not affect the working mechanism and performance of the DCOC calibration circuit regarding DC offset calibration.

[0041] Table 2 compares the parameters of published BM-LA designs. As can be seen from Table 2, reference [1] uses DC coupling and high-speed digital-to-analog conversion to shorten the common-mode recovery time of burst signals to 2.24ns. The DCOC loop in this solution requires a 6.25GHz clock source, and both the digital circuits and DAC in the DCOC loop must operate at 6.25GHz. This results in a complex circuit structure, high process requirements, and high cost. The design proposed in this paper achieves a burst signal common-mode recovery time of 14ns, and the DCOC circuit structure is simple and low-cost.

[0042] Table 2 Summary of the latest designs for BM-LA related common-mode recovery time and offset calibration

[0043]

[0044] The relevant literature mentioned in Table 2 is listed as follows:

[0045] [1]Chen KC, Emami AA 25-gb / s avalanche photodetector-based burst-mode optical receiver with 2.24-ns reconfiguration time in 28-nm cmos[J]. IEEEJournal of Solid-State Circuits, vol.54, pp.1–12,03 2019.

[0046] [2]Coudyzer G, Ossieur P, Bauwelinck J, et al.A 25gbaud pam-4linearburst-mode receiver with analog gain-and offset control in 0.25m sige: cbicmos, IEEE Journal of Solid-State Circuits, vol.55, pp.1–1,04 2020.

[0047] [3]Lee SH, Kim J, Le Q, et al. A single chip 2.5-gb / s burst-mode optical receiver with wide dynamic range. IEEE Photonics Technology Letters, vol.23, pp.85–87,02 2011.

[0048] In summary, the design proposed in this paper is one of the few solutions with the simplest DCOC circuit structure that meets the 25.6ns recovery time requirement specified by the XGS-PON protocol standard. This solution reduces chip costs and is suitable for XGS-PON receivers.

[0049] Note: In the present invention, the word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.

[0050] The use of ordinal numbers such as "first," "second," and "third" in the specification and claims to modify corresponding elements does not in itself mean that the elements have any ordinal number, nor does it represent the order of one element relative to another or the order in the manufacturing method. The use of such ordinal numbers is only used to clearly distinguish one element with a certain name from another element with the same name.

Claims

1. A DCOC calibration circuit for an XGS-PON burst mode limiting amplifier, characterized by: The fast common-mode recovery circuit of the XGS-PON burst mode limiting amplifier includes three parts: a dynamic time constant control unit (RC_CONTROL), a burst mode limiting amplifier (BM-LA), and a DC offset (DCOC) calibration circuit; The DCOC calibration circuit (DC offset calibration circuit) consists of a low-pass filter, an amplifier, a comparator, a digital controller, and a current differential DAC; The output signal of the dynamic time constant control unit (RC_CONTROL) is transmitted to the burst mode limiting amplifier; The output signal of the burst mode limiting amplifier (BM-LA) is output to the low-pass filter input of the DC offset calibration circuit (DCOC). After low-pass filtering, it is output to the amplifier and comparator in sequence. The output signal of the comparator is transmitted to the input of the digital controller. The output signal of the burst mode limiting amplifier (BM-LA) is output to the low-pass filter input of the DC offset (DCOC) calibration circuit. After low-pass filtering, it is output to the amplifier and comparator in sequence. The output signal of the comparator is transmitted to the input of the digital controller. The digital controller has a DOC_ON port connected to one of the input terminals of the OR gate in the dynamic time constant control unit (RC_CONTROL); The low-pass filter and amplifier extract and scale the DC offset, respectively. The comparator determines the polarity of the DC offset. Based on the comparator's comparison result, the digital controller increases or decreases the output value of the current differential DAC until DC offset calibration is complete.

2. The DCOC calibration circuit according to claim 1, wherein: The burst mode limiting amplifier (BM-LA) is composed of a first operational amplifier, a second operational amplifier, a third operational amplifier, and a fourth operational amplifier connected in sequence; the output signal of the first operational amplifier is also transmitted to the input end of the current differential DAC, and the output signal of the current differential DAC is transmitted to the digital controller DIG.

3. The DCOC calibration circuit according to claim 1, wherein: The output signal of the burst mode limiting amplifier (BM-LA) is output to the low-pass filter input of the DC offset calibration circuit (DCOC). After low-pass filtering, it is output to the amplifier and comparator in sequence. The output signal of the comparator is transmitted to the input of the digital controller.

4. The DCOC calibration circuit according to claim 1, wherein: The input signal of the current differential DAC is from the output of the first operational amplifier of the burst mode limiting amplifier (BM-LA); the output signal of the current differential DAC is also transmitted to the digital controller; The digital controller controls the working state of the dynamic time constant control unit (RC_CONTROL) through an OR gate circuit.

5. The DCOC calibration circuit according to claim 4, wherein: The output signal of the current differential DAC is also transmitted to the digital controller; the digital controller controls the working state of the dynamic time constant control unit (RC_CONTROL) through an OR gate circuit.

6. The DCOC calibration circuit according to claim 1, wherein: The low-pass filter LPF is an RC-structured low-pass filter. A resistor R is connected in series to both input terminals IN+ and IN-, and a capacitor C is connected in parallel after the resistor R. The signals at the input terminals IN+ and IN- of the low-pass filter LPF are derived from the output terminal of the fourth operational amplifier 4st in the burst mode limiting amplifier (BM-LA).

7. The DCOC calibration circuit according to claim 6, wherein: R=40KΩ, C=10pF.

8. The DCOC calibration circuit according to claim 1, wherein: When calibration starts, DOC_ON is set to 1 and the resistor in RC_CONTROL is shorted, which significantly attenuates the input signal of the burst mode limiting amplifier (BM-LA). This greatly reduces the interference of the input signal on the DC offset calibration loop and simplifies the design of the low-pass filter. After calibration, the digital controller Dig locks the DAC value and sets DOC_ON to 0, and shuts down the DCOC loop circuit except the DAC to reduce the power consumption of the XGS-PON burst mode limiting amplifier.

9. The DCOC calibration circuit according to claim 1, wherein: A dynamic time constant control unit (RC_CONTROL) has signal input terminals In+ and In-, which are respectively connected to the signal input terminal of a burst mode limiting amplifier (BM-LA) through two identical capacitors C. A first resistor R and a first controllable switch are connected in parallel between the signal input terminal In+ of the dynamic time constant control unit (RC_CONTROL) and the input common-mode voltage terminal through the capacitor C. A second resistor R and a second controllable switch are connected in parallel between the signal input terminal In- of the dynamic time constant control unit (RC_CONTROL) and the input common-mode voltage terminal through the capacitor C. Control terminals of the first controllable switch and the second controllable switch are both connected to an OR gate (OR) circuit, and two input terminals of the OR gate (OR) circuit are respectively connected to a reset terminal (RST, Reset) and a DOC_ON signal terminal of a DC offset calibration (DCOC) feedback loop.

10. A DCOC calibration method for an XGS-PON burst mode limiting amplifier, the method being implemented based on the DCOC calibration circuit according to any one of claims 1 to 9, characterized in that: The digital controller has a DOC_ON port connected to one of the input terminals of the OR gate in the dynamic time constant control unit (RC_CONTROL); When calibration starts, DOC_ON is set to 1 and the resistor in RC_CONTROL is shorted, which significantly attenuates the input signal of the burst mode limiting amplifier (BM-LA). This greatly reduces the interference of the input signal on the DC offset calibration loop and simplifies the design of the low-pass filter. After calibration, the digital controller Dig locks the DAC value and sets DOC_ON to 0, and shuts down the DCOC loop circuit except the DAC to reduce the power consumption of the XGS-PON burst mode limiting amplifier.

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