limiter circuit

Abstract

The application provides a limiter circuit, which comprises a plurality of transmission lines connected in series, one end of the transmission lines serving as an input end of a radio frequency signal, the other end of the transmission lines being connected with an input end of an amplifier, and an output end of the amplifier serving as an output end of the radio frequency signal; a limiter branch connected between adjacent transmission lines and the amplifier in series, each limiter branch comprising a first symmetric branch and a second symmetric branch, the first symmetric branch and the second symmetric branch in each limiter branch being symmetrically distributed on both sides of the transmission line, so that the parasitic capacitance of each limiter branch is consistent and evenly distributed; and a bias control circuit connected with the first symmetric branch and the second symmetric branch in each limiter branch, so that the current and the density of each limiter branch are the same under the same size. The limiter circuit of the application improves the insertion loss and the effective power tolerance of the limiter circuit.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a limiter circuit. Background Technology

[0002] As a critical first-stage module in the receive link of an RF transceiver system, the low-noise amplifier (LNOA) is often susceptible to damage or burnout due to high-power blocking interference signals or high-power leakage signals from the transmit link. Therefore, a limiter protection design is typically required to restrict the power of the signal entering the LNOA to a level suitable for safe reception. The LNOA limiter design must possess sufficiently strong power limiting protection capabilities while minimizing impedance mismatch, insertion loss, and noise contribution to avoid impacting the impedance matching, noise, gain, linearity, and other intrinsic RF performance characteristics of the LNOA in small-signal reception.

[0003] Please see Figure 1 Off-chip limiter architectures generally have strong power protection capabilities, but usually require the introduction of an additional system impedance matching network. Its parasitic effects can affect the limiter bandwidth and degrade insertion loss, thus contributing noise.

[0004] Please see Figure 2 and Figure 3 The on-chip integrated limiter architecture incorporates parasitic effects into the on-chip low-noise amplifier input impedance matching network. It utilizes the broadband distribution effect of transmission lines to reduce the impact of parasitic capacitance on impedance matching, bandwidth, and insertion loss. This can improve insertion loss and impedance matching to a certain extent and increase bandwidth. However, the impedance effect of the distributed transmission lines will bring about voltage distribution effects, resulting in uneven current distribution in different branches of the limiter. This limits the improvement of impedance matching, bandwidth, power protection capability, and insertion loss of the integrated limiter.

[0005] Therefore, a novel on-chip integrated limiter and circuit design is needed to improve bandwidth and impedance matching and insertion loss, thereby enhancing the power protection capability of the limiter. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a limiter circuit to solve the problem that in the prior art, the on-chip integrated limiter architecture incorporates parasitic effects into the on-chip low-noise amplifier input impedance matching network and uses the broadband distribution effect of the transmission line to reduce the impact of parasitic capacitance on impedance matching, bandwidth and insertion loss. This can improve insertion loss and impedance matching to a certain extent and increase bandwidth. However, the impedance effect of the distributed transmission line will bring voltage distribution effect, which will cause the current distribution of different branches of the limiter to be uneven, thus limiting the improvement of impedance matching, bandwidth, power protection capability and insertion loss of the integrated limiter.

[0007] To achieve the above and other related objectives, the present invention provides a limiter circuit, comprising:

[0008] Multiple transmission lines are connected in series. One end of the transmission line serves as the input terminal of the radio frequency signal, and the other end of the transmission line is connected to the input terminal of an amplifier. The output terminal of the amplifier serves as the output terminal of the radio frequency signal.

[0009] Limiter branches are sequentially connected between adjacent transmission lines and amplifiers. Each limiter branch includes a first and a second symmetrical branch. The first and second symmetrical branches in each limiter branch are symmetrically distributed on both sides of the transmission line, so that the parasitic capacitance of each limiter branch is consistent in size and evenly distributed.

[0010] A bias control circuit is connected to the first and second symmetrical branches in each of the limiter branches, such that the size and current of each of the limiter branches are the same.

[0011] Preferably, the first symmetrical branch in each of the limiter branches includes a first PMOS, a second PMOS, a first diode, and a first bias resistor, and the second symmetrical branch includes a first NMOS, a second NMOS, a second diode, and a second bias resistor. One end of the first bias resistor is connected to the gates of the first and second PMOS, and one end of the second bias resistor is connected to the gates of the first and second NMOS, respectively. The cathode of the first diode is connected to the anode of the second diode and connected between two adjacent transmission lines or between adjacent transmission lines and the amplifier. The drain of the first PMOS is connected to the drain of the first NMOS. The gate of the second PMOS is connected to the gate of the first PMOS and to the anode of the first diode. The drain of the second PMOS is connected to the source of the first PMOS. The gate of the first NMOS is connected to the gate of the second NMOS. The source of the first NMOS is connected to the drain of the second NMOS. The substrate electrode of the first PMOS is connected to the substrate electrode of the second PMOS, and the substrate electrode of the first NMOS is connected to the substrate electrode of the second NMOS.

[0012] Preferably, one end of the bias control circuit is connected to the chip's operating voltage Vdd, and the bias control circuit also includes a first to a third voltage output terminal, wherein the voltages output by the first and second output terminals are both positive, and the voltage output by the third voltage output terminal is negative.

[0013] Preferably, the first voltage output terminal is connected to the other end of the first bias resistor in each of the first symmetrical branches through a voltage divider structure.

[0014] Preferably, the second voltage output terminal is connected to the source electrode of the second PMOS and the substrate electrode of the second PMOS in each of the first symmetrical branches through the voltage divider structure.

[0015] Preferably, the third voltage output terminal is connected to the other end of the second bias resistor in each of the second symmetrical branches through the voltage divider structure.

[0016] Preferably, the voltage divider structure is a variable resistor series adjustment structure or a MOSFET voltage divider adjustment circuit.

[0017] Preferably, the limiter circuit further includes a limiter control feedback unit, which is used to obtain the power of the limiter circuit. If the power is lower than or equal to the design threshold, the limiter circuit is turned off.

[0018] Preferably, the limiter control feedback unit includes a power detection module and a first to three voltage selection module. The power detection module is used to obtain the power of the limiter circuit, and the first to three voltage selection module is used to switch the output voltage of the first to three voltage output terminals according to the power. If the power is lower than or equal to the design threshold, the output of the first to three voltage selection module is the output voltage of the second voltage output terminal, the ground 0 voltage, and the output voltage VCC, respectively, thus turning off the limiter circuit. Conversely, the output of the first to three voltage selection module is the output voltage of the first to three voltage output terminals, respectively, thus turning on the limiter circuit.

[0019] Preferably, the limiter branch includes a first to a third limiter branch.

[0020] As described above, the limiter circuit of the present invention has the following beneficial effects:

[0021] This invention employs MOSFETs for distributed integrated limiter branch design, utilizing gate bias voltage to compensate for the uneven current and voltage distribution caused by transmission line distribution effects. This ensures that different limiter branches have the same current and density under the same size, while the parasitic capacitance of each branch is relatively consistent and evenly distributed, improving impedance matching and bandwidth, and enhancing insertion loss. The forward and reverse designs of each branch use N-type and P-type MOSFETs to improve noise and linearity performance. The power coupling of each limiter branch employs a diode coupling protection design, increasing the power voltage during turn-on and the gate withstand voltage during turn-off. Adding a two-stage stacked source-drain structure reduces parasitic capacitance and improves source-drain withstand voltage, comprehensively improving power limiting withstand protection capability. An added limiter control feedback design generates control signals based on power detection to turn the limiter on and off. Turning off the limiter at low power input reduces parasitic capacitance and noise, further improving the system's insertion loss, bandwidth, and noise performance. This improves the insertion loss and effective power withstand capability of the limiter circuit. Attached Figure Description

[0022] Figure 1 The diagram shows a schematic of an off-chip limiter architecture in the prior art.

[0023] Figure 2 The diagram shows an on-chip integrated limiter architecture of the prior art.

[0024] Figure 3 The diagram shows the branch current distribution of an on-chip integrated limiter architecture in the prior art.

[0025] Figure 4 The diagram shown is a schematic diagram of the limiter circuit structure according to an embodiment of the present invention;

[0026] Figure 5 The diagram shown is a schematic diagram of the limiter control feedback unit structure according to an embodiment of the present invention.

[0027] Figure 6 The diagram shown is a simulation analysis diagram of the insertion loss and impedance of the limiter circuit in an embodiment of the present invention.

[0028] Figure label:

[0029] First PMOS MP1

[0030] Second PMOS MP2

[0031] First diode Dp

[0032] Second diode Dn

[0033] First NMOS MN1

[0034] Second NMOS MN2

[0035] First transmission line TL1

[0036] Second transmission line TL2

[0037] Third transmission line TL3

[0038] Amplifier LNA

[0039] First bias resistor Rgp

[0040] Second bias resistor Rgn

[0041] First resistor Rp1

[0042] Second resistor Rp2

[0043] Third resistor Rp3

[0044] Fourth resistor Rp4

[0045] Fifth resistor Rn1

[0046] Sixth resistor Rn2

[0047] Seventh resistor Rn3

[0048] Eighth resistor Rn4

[0049] First voltage output terminal Vp

[0050] Second voltage output terminal Vd

[0051] Third voltage output terminal Vn

[0052] First voltage selection module 101

[0053] Second voltage selection module 102

[0054] Third voltage selection module 103 Detailed Implementation

[0055] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0056] Please see Figure 4 The present invention provides a limiter circuit, comprising:

[0057] Multiple transmission lines are connected in series. One end of the transmission line serves as the input terminal of the radio frequency signal, and the other end of the transmission line is connected to the input terminal of the amplifier LNA. The output terminal of the amplifier LNA serves as the output terminal of the radio frequency signal.

[0058] Limiter branches are sequentially connected between adjacent transmission lines and amplifiers (LNAs). Each limiter branch includes a first and a second symmetrical branch. The first and second symmetrical branches in each limiter branch are symmetrically distributed on both sides of the transmission line, so that the parasitic capacitance of each limiter branch is consistent in size and evenly distributed.

[0059] In an embodiment of the present invention, the first symmetrical branch in each limiter branch includes a first PMOS MP1, a second PMOS MP2, a first diode Dp, and a first bias resistor Rgp; the second symmetrical branch includes a first NMOS MN1, a second NMOS MN2, a second diode Dn, and a second bias resistor Rgn. One end of the first bias resistor Rgp is connected to the gates of the first and second PMOS transistors, and one end of the second bias resistor Rgn is connected to the gates of the first and second NMOS transistors, respectively. The cathode of the first diode Dp is connected to the anode of the second diode Dn, and they are connected between two adjacent transmission lines or between an adjacent transmission line and an amplifier LNA. The drain of the first PMOS MP1 is connected to the drain of the first NMOS MN1. The gate of the second PMOS MP2 is connected to the gate of the first PMOS MP1 and to the anode of the first diode Dp. The drain of the second PMOS MP2 is connected to the source of the first PMOS MP1. The gate of the first NMOS MN1 is connected to the gate of the second NMOS MN2. The source of MN1 is connected to the drain of the second NMOS MN2, the substrate electrode of the first PMOS MP1 is connected to the substrate electrode of the second PMOS MP2, and the substrate electrode of the first NMOS MN1 is connected to the substrate electrode of the second NMOS MN2. Rnp1 is used to characterize the substrate resistance of the first PMOS MP1, Rpb2 is used to characterize the substrate resistance of the second PMOS MP2, Rnb1 is used to characterize the substrate resistance of the first NMOS MN1, and Rnb2 is used to characterize the substrate resistance of the second NMOS MN2. That is, a distributed integrated limiter branch design is carried out using MOS transistors. The gate bias voltage is used to compensate for the current and voltage imbalance caused by the transmission line distribution effect, so that the current and density of different limiter branches are the same under the same size. At the same time, the parasitic capacitance of each branch is relatively consistent and evenly distributed, which improves the impedance matching and bandwidth effect and improves the insertion loss. The forward and reverse designs of each branch use N-type and P-type MOS to improve noise and linearity performance; the coupling power of each limiter branch adopts a diode coupling protection design, which increases the turn-on power voltage when turned on and increases the gate withstand voltage when turned off. The source-drain structure is increased to a two-stage stack to reduce parasitic capacitance and improve the source-drain withstand voltage, thus comprehensively improving the power limiting withstand protection capability.

[0060] The bias control circuit is connected to the first and second symmetrical branches in each limiter branch, so that the size and current of each limiter branch are the same, that is, the size of the devices in each limiter branch is the same and the node current is the same. Since the current density = current / limiter branch size, the current density of each limiter branch is also the same.

[0061] In an embodiment of the present invention, one end of the bias control circuit is connected to the chip's operating voltage Vdd. The bias control circuit also includes a first to a third voltage output terminal (Vp, Vd, Vn). The voltage output by the first output terminal Vp is positive, the voltage output by the second output terminal Vd is positive, and the voltage output by the third voltage output terminal Vn is negative.

[0062] In an embodiment of the present invention, the first voltage output terminal Vp is connected to the other end of the first bias resistor Rgp in each first symmetrical branch through a voltage divider structure.

[0063] In an embodiment of the present invention, the second voltage output terminal Vd is connected to the substrate electrode of the source of the second PMOS MP2 and the substrate electrode of the second PMOS MP1 in each first symmetrical branch through a voltage divider structure.

[0064] In an embodiment of the present invention, the third voltage output terminal Vn is connected to the other end of each second bias resistor Rgn in each second symmetrical branch through a voltage divider structure.

[0065] In embodiments of the present invention, the voltage divider structure is a variable resistor series adjustment structure or a MOSFET voltage divider adjustment circuit. Specifically, for example, when the limiter branch includes the first to third limiter branches (limiter branches 1 to 3), the voltage divider structure of the first voltage output terminal Vp is the first to fourth variable resistors or the first to fourth MOSFETs (Rp1 to Rp4) connected in series, where Rp1 to Rp4 are used to characterize the resistance of the variable resistors or MOSFETs. The voltage divider structure of the third voltage output terminal Vn is the fifth to eighth resistors or the fifth to eighth MOSFETs (Rn1 to Rn4) connected in series, where Rn1 to Rn4 are used to characterize the resistance of the variable resistors or MOSFETs.

[0066] In an embodiment of the present invention, please refer to Figure 5 The limiter circuit also includes a limiter control feedback unit, which is used to obtain the power of the limiter circuit. If the power is lower than or equal to the design threshold, the limiter circuit is turned off. That is, the limiter control feedback design is added. The control signal generated according to the power detection is used to turn the limiter off and on. The limiter is turned off when the power input is low, which reduces parasitic capacitance and parasitic noise, and can further improve the insertion loss bandwidth and noise performance of the system.

[0067] In an embodiment of the present invention, the limiter control feedback unit includes a power detection module and a first to third voltage selection module (101 to 103). The power detection module is used to obtain the power of the limiter circuit, and the first to third voltage selection module (101 to 103) is used to switch the output voltage of the first to third voltage output terminals according to the power magnitude. If the power is lower than or equal to the design threshold, the output of the first to third voltage selection module (101 to 103) is the output voltage of the second voltage output terminal Vd, the ground 0 voltage, and the output voltage VCC, respectively, and the limiter circuit is turned off. Conversely, the output of the first to third voltage selection module (101 to 103) is the output voltage of the first to third voltage output terminals, respectively, and the limiter circuit is turned on.

[0068] In an embodiment of the present invention, the limiter branch includes a first to a third limiter branch (limiter branches 1 to 3), that is, it includes three transmission lines connected in series (first transmission line TL1, second transmission line TL2, and third transmission line TL3). One end of the transmission line serves as the input terminal of the radio frequency signal, and the other end of the transmission line is connected to the input terminal of the amplifier LNA. The output terminal of the amplifier LNA serves as the output terminal of the radio frequency signal. The insertion loss and impedance simulation analysis of its limiter circuit are as follows: Figure 6 As shown, the impedance and insertion loss of the limiter circuit in the prior art are shown as curves 101 and 201, respectively. The impedance and insertion loss of the limiter circuit in this embodiment are shown as curves 102 and 202, respectively. While improving the insertion loss, the effective power tolerance is improved by 3dB.

[0069] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0070] In summary, this invention employs MOSFETs for distributed integrated limiter branch design, utilizing gate bias voltage to compensate for the uneven current and voltage distribution caused by transmission line distribution effects. This ensures that different limiter branches have the same current and density under the same size, while maintaining relatively consistent and balanced parasitic capacitance across branches. This improves impedance matching and bandwidth, and enhances insertion loss. The forward and reverse designs of each branch utilize N-type and P-type MOSFETs to improve noise and linearity performance. Diode coupling protection is used for the power coupling of each limiter branch, increasing the power voltage during startup and enhancing gate withstand voltage during shutdown. The addition of a two-stage stacked source-drain structure reduces parasitic capacitance and improves source-drain withstand voltage, comprehensively enhancing power limiting withstand protection. A limiter control feedback design is added, generating control signals based on power detection to turn the limiter on and off. Turning off the limiter at low power input reduces parasitic capacitance and noise, further improving the system's insertion loss, bandwidth, and noise performance. This improves the insertion loss and effective power withstand capability of the limiter circuit. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0071] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A clipper circuit, characterized by include: Multiple transmission lines are connected in series. One end of the transmission line serves as the input terminal of the radio frequency signal, and the other end of the transmission line is connected to the input terminal of an amplifier. The output terminal of the amplifier serves as the output terminal of the radio frequency signal. Limiter branches are sequentially connected between adjacent transmission lines and amplifiers. Each limiter branch includes a first and a second symmetrical branch. The first and second symmetrical branches in each limiter branch are symmetrically distributed on both sides of the transmission line, so that the parasitic capacitance of each limiter branch is consistent in size and evenly distributed. A bias control circuit is connected to the first and second symmetrical branches in each of the limiter branches, such that the size and current of each of the limiter branches are the same. Each of the first symmetrical branches in the limiter branch includes a first PMOS, a second PMOS, a first diode, and a first bias resistor. The second symmetrical branch includes a first NMOS, a second NMOS, a second diode, and a second bias resistor. One end of the first bias resistor is connected to the gates of the first and second PMOS, respectively. One end of the second bias resistor is connected to the gates of the first and second NMOS, respectively. The cathode of the first diode is connected to the anode of the second diode and connected between two adjacent transmission lines or between adjacent transmission lines and the amplifier. The drain of the first PMOS is connected to the drain of the first NMOS. The gate of the second PMOS is connected to the gate of the first PMOS and connected to the anode of the first diode. The drain of the second PMOS is connected to the source of the first PMOS. The gate of the first NMOS is connected to the gate of the second NMOS. The source of the first NMOS is connected to the drain of the second NMOS. The substrate electrode of the first PMOS is connected to the substrate electrode of the second PMOS. The substrate electrode of the first NMOS is connected to the substrate electrode of the second NMOS.

2. The clipper circuit of claim 1, wherein: One end of the bias control circuit is connected to the chip's operating voltage Vdd. The bias control circuit also includes a first to a third voltage output terminal. The voltages output by the first and second voltage output terminals are both positive, and the voltage output by the third voltage output terminal is negative.

3. The clipper circuit of claim 2, wherein: The first voltage output terminal is connected to the other end of the first bias resistor in each of the first symmetrical branches through a voltage divider structure.

4. The clipper circuit of claim 3, wherein: The second voltage output terminal is connected to the source electrode of the second PMOS and the substrate electrode of the second PMOS in each of the first symmetrical branches through the voltage divider structure.

5. The clipper circuit of claim 4, wherein: The third voltage output terminal is connected to the other end of the second bias resistor in each of the second symmetrical branches through the voltage divider structure.

6. The clipper circuit of claim 3 or 4 or 5, characterized in that: The voltage divider structure is a variable resistor series adjustment structure or a MOSFET voltage divider adjustment circuit.

7. The clipper circuit of claim 1, wherein: The limiter circuit also includes a limiter control feedback unit, which is used to obtain the power of the limiter circuit. If the power is lower than or equal to the design threshold, the limiter circuit is turned off.

8. The clipper circuit of claim 7, wherein: The limiter control feedback unit comprises a power detection module and first to third voltage selection modules, the power detection module is used for acquiring the power of the limiter circuit, and the first to third voltage selection modules are used for switching the output voltages of the first to third voltage output terminals according to the size of the power; wherein if the power is lower than or equal to the design threshold, the outputs of the first to third voltage selection modules are respectively the output voltage of the second voltage output terminal, the ground 0 voltage and the output voltage VCC to turn off the limiter circuit, otherwise the outputs of the first to third voltage selection modules are respectively the output voltages of the first to third voltage output terminals to turn on the limiter circuit.

9. The clipper circuit of claim 1, wherein: The limiter branch comprises first to third limiter branches.

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