A low-power level shifter for ultra-wide voltage conversion

Abstract

A low-power level converter for ultra-wide voltage conversion. A pull-down circuit is configured to pull node Q1 down to a low level when the level of the low-voltage power domain is high, and to pull node Q2 down to a low level when the level of the low-voltage power domain is low. While the pull-down circuit is pulling node Q1 down to a low level, a first charging circuit is configured to output current to node Q2, causing the potential of node Q2 to rise. While the pull-down circuit is pulling node Q2 down to a low level, a second charging circuit is configured to output current to node Q1, causing the potential of node Q1 to rise. A complementary pull-up circuit is configured to pull node Q2 up to a high level in the high-voltage power domain when node Q1 is low, and to pull node Q1 up to a high level in the high-voltage power domain when node Q2 is low. Because competition between the complementary pull-up and pull-down circuits is eliminated or reduced, the voltage difference range during level conversion is wide, reducing conversion energy consumption during level conversion.

Description

Technical Field

[0001] The present invention relates to the technical field of signal processing, and in particular to a low-power level converter for ultra-wide range voltage conversion. Background Art

[0002] Modern, complex systems-on-chip (SoCs) have widely adopted multiple power domains to meet performance requirements while reducing power consumption. Level shifters are needed between these power domains to facilitate data transmission. For example, in a multi-supply voltage system, a level shifter is used to transfer signals from the low-voltage (VDDL) power domain to the high-voltage (VDDH) power domain. Traditional level shifter structures include various types, such as cross-coupled level shifters (CCLS) and current mirror level shifters (CMLS). Cross-coupled level shifters achieve near-zero static power consumption through complementary pull-up networks (PUN) and pull-down networks (PDN). However, the voltage difference range between the converted levels during level shifting is limited, resulting in high conversion energy consumption. Current mirror level shifters, on the other hand, increase the voltage difference range during level shifting through current mirror circuits. However, these current mirror level shifters draw higher static currents during level shifting, resulting in additional static power consumption. Summary of the Invention

[0003] The main technical problem solved by the present invention is how to increase the voltage difference range of the level during level conversion and reduce the static current.

[0004] According to a first aspect, an embodiment provides a low-power level converter for ultra-wide range voltage conversion, comprising: a pull-down circuit, a complementary pull-up circuit, a first charging circuit, a second charging circuit, and a level output module;

[0005] The first control terminal of the pull-down circuit is used to input the level of the low-voltage power domain, and the second control terminal is used to input a level of the opposite level type of the low-voltage power domain. The first output terminal of the pull-down circuit is respectively connected to the first output terminal and the second control terminal of the complementary pull-up circuit to form a node Q1. The second output terminal of the pull-down circuit is respectively connected to the second output terminal and the first control terminal of the complementary pull-up circuit to form a node Q2.

[0006] The control end of the first charging circuit is used to input the level of the low-voltage power domain, and the output end is connected to the node Q2. The control end of the second charging circuit is used to input the level type opposite to the level type of the low-voltage power domain, and the output end is connected to the node Q1.

[0007] The input end of the level output module is used to be connected to at least the node Q1 or the node Q2, and the level output module is used to output the level of the high-voltage power domain according to at least the potential of the node Q1 or the node Q2, and the level of the high-voltage power domain is the same type as the level of the low-voltage power domain;

[0008] In which, the pull-down circuit is used to pull down the node Q1 to a low level when the level of the low-voltage power domain is a high level, and to pull down the node Q2 to a low level when the level of the low-voltage power domain is a low level. In the process of the pull-down circuit pulling down the node Q1 to a low level, the first charging circuit is used to output current to the node Q2, so that the potential of the node Q2 rises. In the process of the pull-down circuit pulling down the node Q2 to a low level, the second charging circuit is used to output current to the node Q1, so that the potential of the node Q1 rises. The complementary pull-up circuit is used to pull up the node Q2 to the high level of the high-voltage power domain when the node Q1 is a low level, and to pull up the node Q1 to the high level of the high-voltage power domain when the node Q2 is a low level.

[0009] According to a second aspect, an embodiment provides a low-power level converter for ultra-wide range voltage conversion, comprising: a pull-down circuit, a complementary pull-up circuit, a first charging circuit, a second charging circuit, and a level output module;

[0010] The first control terminal and the second control terminal of the pull-down circuit are both used to input the level of the low-voltage power domain, the first output terminal of the pull-down circuit is respectively connected to the first output terminal and the second control terminal of the complementary pull-up circuit, and form a node Q1, and the second output terminal of the pull-down circuit is respectively connected to the second output terminal and the first control terminal of the complementary pull-up circuit, and form a node Q2;

[0011] The control terminals of the first charging circuit and the second charging circuit are both used to input the voltage level of the low-voltage power domain, the output terminal of the first charging circuit is connected to the node Q2, and the output terminal of the second charging circuit is connected to the node Q1;

[0012] The input end of the level output module is at least used to connect to the node Q1 or the node Q2, and the level output module is used to output the level of the high-voltage power domain according to the potential of the node Q1 or the node Q2, and the level of the high-voltage power domain is the same as the level of the low-voltage power domain;

[0013] In which, the pull-down circuit is used to pull down the node Q1 to a low level when the level of the low-voltage power domain is a high level, and to pull down the node Q2 to a low level when the level of the low-voltage power domain is a low level. In the process of the pull-down circuit pulling down the node Q1 to a low level, the first charging circuit is used to output current to the node Q2, so that the potential of the node Q2 rises. In the process of the pull-down circuit pulling down the node Q2 to a low level, the second charging circuit is used to output current to the node Q1, so that the potential of the node Q1 rises. The complementary pull-up circuit is used to pull up the node Q2 to the high level of the high-voltage power domain when the node Q1 is a low level, and to pull up the node Q1 to the high level of the high-voltage power domain when the node Q2 is a low level.

[0014] According to the low-power level shifter for ultra-wide voltage conversion in the above-described embodiment, by charging node Q2 via the first charging circuit or charging node Q1 via the second charging circuit, competition between the complementary pull-up circuit and the pull-down circuit at node Q1 or node Q2 can be eliminated or reduced, allowing node Q1 or node Q2 to be smoothly pulled to a low level by the pull-down circuit, thereby achieving level conversion. Because competition between the complementary pull-up circuit and the pull-down circuit is eliminated or reduced, the voltage difference range during level conversion can be widened, and the conversion energy consumption during level conversion can also be reduced. Furthermore, because the first and second charging circuits only briefly charge node Q1 or node Q2 while the pull-down circuit is pulling node Q1 or node Q2 to a low level, the first and second charging circuits consume only a small amount of power, without adding additional power consumption, thereby reducing the overall power consumption of the level shifter. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A cross-coupled level converter in the background art;

[0016] Figure 2 A circuit diagram of a low-power level converter for ultra-wide range voltage conversion according to an embodiment;

[0017] Figure 3 A schematic diagram of switching from high-level conversion to low-level conversion of a low-power level converter for ultra-wide voltage conversion according to an embodiment;

[0018] Figure 4 A schematic diagram of switching from low-level conversion to high-level conversion of a low-power level converter for ultra-wide range voltage conversion according to an embodiment;

[0019] Figure 5 FIG. 4 is a circuit diagram of a low-power level converter for ultra-wide range voltage conversion according to another embodiment. DETAILED DESCRIPTION

[0020] The present invention will be further described in detail below by means of specific embodiments in conjunction with the accompanying drawings. Similar elements in different embodiments are numbered with associated similar elements. In the following embodiments, many detailed descriptions are provided to enable the present application to be better understood. However, those skilled in the art will readily appreciate that some of the features may be omitted in different circumstances, or may be replaced by other elements, materials, or methods. In some cases, some operations related to the present application are not shown or described in the specification. This is to avoid the core portion of the present application being overwhelmed by excessive descriptions, and for those skilled in the art, it is not necessary to describe these related operations in detail. They will fully understand the related operations based on the description in the specification and the general technical knowledge in the art.

[0021] In addition, the features, operations, or characteristics described in the specification may be combined in any appropriate manner to form various embodiments. Furthermore, the steps or actions in the method description may be reordered or adjusted in a manner readily apparent to those skilled in the art. Therefore, the various sequences in the specification and drawings are provided solely for the purpose of clearly describing a particular embodiment and are not intended to be mandatory, unless otherwise specified.

[0022] The serial numbers assigned to components herein, such as "first," "second," etc., are used solely to distinguish the objects being described and do not convey any sequential or technical meaning. References to "connection" and "coupling" herein, unless otherwise specified, include both direct and indirect connections (couplings).

[0023] Please refer to Figure 1 The cross-coupled level converter includes a complementary pull-up network formed by transistors P9 and P10, and a pull-down network formed by transistors N9 and N10, which can achieve near-zero static power consumption. However, during level conversion, for example, when switching from a high-level conversion to a low-level conversion, current competition occurs between the weak pull-down network driven by VDDL and the strong complementary pull-up network driven by VDDH. For example, current competition occurs between transistors P9 and N9 at node Q4, and between transistors P10 and N10 at node Q5. This can lead to level conversion failures and result in higher conversion energy consumption. Therefore, to reduce level conversion failures, the voltage difference range between the converted levels during level conversion can only be limited.

[0024] In an embodiment of the present invention, during the level shifting process, the connection node between the pull-down circuit and the complementary pull-up circuit is charged by the first charging circuit or the second charging circuit. This eliminates or reduces current competition between the pull-down circuit and the complementary pull-up circuit, thereby increasing the voltage difference range during level shifting and reducing conversion energy consumption. Furthermore, the charging time of the first and second charging circuits is short, which does not significantly increase power consumption, thereby reducing the overall power consumption of the level shifter.

[0025] It should be noted that the transistor in the present invention, unless otherwise specified, can be a transistor of any structure, such as a bipolar junction transistor (BJT), a field effect transistor (FET) or a thin film transistor (TFT). When the transistor is a bipolar transistor, its control electrode refers to the base of the bipolar transistor, the first electrode can be the collector or emitter of the bipolar transistor, and the corresponding second electrode can be the emitter or collector of the bipolar transistor. In actual application, the "emitter" and "collector" can be interchanged according to the signal flow direction; when the transistor is a field effect transistor, its control electrode refers to the gate of the field effect transistor, the first electrode can be the drain or source of the field effect transistor, and the corresponding second electrode can be the source or drain of the field effect transistor. In actual application, the "source" and "drain" can be interchanged according to the signal flow direction.

[0026] Example 1:

[0027] This embodiment provides a low-power level converter for ultra-wide range voltage conversion, which is used to convert the level (IN) of the low-voltage power domain to the level (OUT) of the high-voltage power domain, for example, converting the high level VDDL of the low-voltage power domain to the high level VDDH of the high-voltage power domain, or converting the low level of the low-voltage power domain to the low level of the high-voltage power domain. In the following embodiments, the high-voltage power domain and the low-voltage power domain share the same ground for illustration, that is, the ground potential of the high-voltage power domain and the low-voltage power domain is the same. Please refer to Figure 2 The low-power level converter for ultra-wide range voltage conversion includes a pull-down circuit 10, a complementary pull-up circuit 20, a first charging circuit 30, a second charging circuit 40 and a level output module 50, which are described in detail below.

[0028] The pull-down circuit 10 comprises a power supply terminal, a first control terminal, a second control terminal, a first output terminal, and a second output terminal. The first control terminal of the pull-down circuit 10 is used to input the voltage level (IN) of the low-voltage power domain, such as a low level or a high level. The second control terminal of the pull-down circuit 10 is used to input the voltage level (INB) of the opposite type to the voltage level of the low-voltage power domain. For example, when the voltage level of the low-voltage power domain is high, the voltage level of the low-voltage power domain is input. The power supply terminal of the pull-down circuit 10 is connected to the ground potential. The pull-down circuit 10 is used to control the output of its first and second output terminals based on the voltage level of its control terminal. For example, when the voltage level of the low-voltage power domain is high, the pull-down circuit 10 outputs a low voltage through its first output terminal; otherwise, it outputs a low voltage through its second output terminal. Therefore, the pull-down circuit 10 can pull the voltage level of its first or second output terminal down to a low level based on the voltage level of the low-voltage power domain. In some embodiments, the level of the low-voltage power domain input to the first control terminal of the pull-down circuit 10 may be converted by an inverter and then input to the second control terminal of the pull-down circuit 10 .

[0029] The complementary pull-up circuit 20 has a power supply terminal, a first control terminal, a second control terminal, a first output terminal, and a second output terminal. The first output terminal and the second control terminal of the complementary pull-up circuit 20 are connected to the first output terminal of the pull-down circuit 10, forming a node Q1. The second output terminal and the first control terminal of the complementary pull-up circuit 20 are connected to the second output terminal of the pull-down circuit 10, forming a node Q2. The power supply terminal of the complementary pull-up circuit 20 is connected to the high voltage power supply domain, VDDH. The complementary pull-up circuit 20 is configured to control the output of its first and second output terminals based on the voltage level of its control terminal. For example, when the first control terminal input is low, the complementary pull-up circuit 20 outputs the high voltage power supply domain, VDDH, through its first output terminal; conversely, when the first control terminal input is low, the complementary pull-up circuit 20 outputs the high voltage power supply domain, VDDH, through its second output terminal. Thus, the complementary pull-up circuit 20 can pull the voltage level of its first or second output terminal up to the high voltage power supply domain, VDDH, based on the voltage level of its control terminal.

[0030] The control terminal of the first charging circuit 30 is used to input the voltage level of the low-voltage power domain, and the output terminal of the first charging circuit 30 is connected to node Q2. When the pull-down circuit 10 pulls node Q1 down to a low level, that is, when the voltage level of the low-voltage power domain changes from a low level to a high level, the first charging circuit 30 is used to output current to node Q2 through its output terminal, thereby charging node Q2 and raising its voltage.

[0031] The control terminal of the second charging circuit 40 is configured to input a voltage level that is opposite to that of the low-voltage power domain. The output terminal of the second charging circuit 40 is connected to node Q1. When the pull-down circuit 10 pulls node Q2 down to a low level, i.e., when the voltage level of the low-voltage power domain changes from a high level to a low level, the second charging circuit 40 is configured to output current to node Q1 through its output terminal, thereby charging node Q1 and raising its potential. In some embodiments, the voltage level of the low-voltage power domain input to the control terminal of the first charging circuit 30 can be converted by an inverter before being input to the control terminal of the second charging circuit 40.

[0032] The level output module 50 is used to output the level of the high-voltage power domain based on the potential of node Q1 or node Q2. The level of the high-voltage power domain is of the same type as the level of the low-voltage power domain. In some embodiments, the input end of the level output module 50 is connected to node Q1. When node Q1 is pulled down to a low level by the pull-down circuit 10, the level output module 50 outputs the high level VDDH of the high-voltage power domain. When node Q1 is pulled up to the high level VDDH of the high-voltage power domain by the complementary pull-up circuit 20, the level output module 50 outputs the low level of the high-voltage power domain, thereby converting the level of the low-voltage power domain to the level of the high-voltage power domain. In some embodiments, the input end of the level output module 50 is connected to node Q2. When node Q2 is pulled up to the high level VDDH of the high-voltage power domain by the complementary pull-up circuit 20, the level output module 50 outputs the high level VDDH of the high-voltage power domain. When node Q2 is pulled down to a low level by the pull-down circuit 10, the level output module 50 outputs the low level of the high-voltage power domain.

[0033] The following describes the operating principle of a low-power level shifter for ultra-wide voltage conversion.

[0034] Please refer to Figure 2 When the level shifter performs a low-level shift from the low-voltage power domain to the high-voltage power domain, the first control terminal of the pull-down circuit 10 inputs the low-voltage power domain's low level, while the second control terminal of the pull-down circuit 10 inputs the high-voltage power domain's VDDL. Consequently, node Q2 is pulled down to a low level, causing the first control terminal of the complementary pull-up circuit 20 to input a low level, thereby pulling node Q1 up to the high-voltage power domain's VDDH. The level output module 50 then outputs the low-voltage power domain's low level based on the potential of node Q1 or node Q2. This allows the level shifter to output a low-voltage power domain's low level when inputting a low-voltage power domain's low level.

[0035] Please refer to Figure 2When the level converter performs a high-level conversion from the low-voltage power domain to the high-voltage power domain, the first control terminal of the pull-down circuit 10 inputs the high-level voltage VDDL of the low-voltage power domain, and the second control terminal of the pull-down circuit 10 inputs the low-level voltage of the low-voltage power domain. Therefore, the node Q1 is pulled down to a low level, causing the second control terminal of the complementary pull-up circuit 20 to input a low level, so that the node Q2 is pulled up to the high-level voltage VDDH of the high-voltage power domain. Then, the level output module 50 outputs the high-level voltage VDDH of the high-voltage power domain according to the potential of node Q1 or node Q2. This allows the level converter to output the high-level voltage VDDH of the high-voltage power domain when the high-level voltage VDDL of the low-voltage power domain is input.

[0036] Please refer to Figure 3 When the level shifter switches from high-level conversion in the low-voltage power domain to low-level conversion in the high-voltage power domain, the high level VDDL input to the low-voltage power domain, as inputted to the first control terminal of the pull-down circuit 10 and the control terminal of the first charging circuit 30, becomes low, while the low level input to the low-voltage power domain, as inputted to the second control terminal of the pull-down circuit 10 and the control terminal of the second charging circuit 40, becomes high. At this point, since nodes Q1 and Q2 remain in the states they were in during the high-level conversion, that is, the potential of node Q1 is low, and the potential of node Q2 is high, as inputted to the high-voltage power domain, VDDH. Therefore, when the second output terminal of the pull-down circuit 10 pulls the potential of node Q2 down to a low level, it needs to compete with the second output terminal of the complementary pull-up circuit 20, potentially leading to the possibility of level conversion failure. However, at this point, since the output terminal of the second charging circuit 40 can charge node Q1, the potential of node Q1 increases, for example, to a high level. This causes the second control terminal of the complementary pull-up circuit 20 to change from a low level to a high level, rendering the second output terminal of the complementary pull-up circuit 20 unable to maintain the pull-up of node Q2 to the high level VDDH of the high-voltage power supply domain, or reducing its ability to do so. This reduces or even eliminates the competition between the pull-down circuit 10 and the complementary pull-up circuit 20 at node Q2. Consequently, node Q2 is pulled down to a low level by the pull-down circuit 10, causing the first control terminal of the complementary pull-up circuit 20 to input a low level. At this point, the output terminal of the second charging circuit 40 stops charging node Q1, and node Q1 is pulled up to the high level VDDH of the high-voltage power supply domain by the complementary pull-up circuit 20. Finally, the level output module 50 outputs a low level of the high-voltage power supply domain.

[0037] Please refer to Figure 4When the level shifter switches from low-level conversion (from the low-voltage power domain to the high-voltage power domain) to high-level conversion, the low-level voltage input from the low-voltage power domain to the first control terminal of the pull-down circuit 10 and the control terminal of the first charging circuit 30 becomes high, while the high-level voltage VDDL input from the low-voltage power domain to the second control terminal of the pull-down circuit 10 and the control terminal of the second charging circuit 40 becomes low. At this point, since nodes Q1 and Q2 remain in the state they were in during the low-level conversion, that is, the potential of node Q1 is the high-level voltage VDDH of the high-voltage power domain, and the potential of node Q2 is low. Therefore, when the first output terminal of the pull-down circuit 10 pulls the potential of node Q1 down to a low level, it needs to compete with the first output terminal of the complementary pull-up circuit 20, thus also potentially causing the level shift to fail. To this end, the output terminal of the first charging circuit 30 charges node Q2, causing the potential of node Q2 to rise, for example, to a high level. This causes the first control terminal of the complementary pull-up circuit 20 to change from a low level to a high level, rendering the first output terminal of the complementary pull-up circuit 20 unable to maintain the pull-up of node Q1 to the high level VDDH of the high-voltage power supply domain, or reducing its ability to do so. Consequently, node Q1 is pulled down to a low level by the pull-down circuit 10, causing the second control terminal of the complementary pull-up circuit 20 to input a low level. At this point, the output terminal of the first charging circuit 30 stops charging node Q2, and node Q2 is pulled up to the high level VDDH of the high-voltage power supply domain by the complementary pull-up circuit 20. Finally, the level output module 50 outputs the high level VDDH of the high-voltage power supply domain.

[0038] As can be seen from the above embodiments, when the level shifter maintains a low-level or high-level conversion from the low-voltage power domain to the high-voltage power domain, the potential of node Q1 or node Q2 can be maintained at the high level VDDH of the high-voltage power domain through the complementary pull-up circuit 20, or the potential of node Q1 or node Q2 can be maintained at a low level through the pull-down circuit 10, and then the low or high level of the high-voltage power domain is output through the output module. Because the output terminal and the control terminal of the complementary pull-up circuit 20 are cross-coupled, the output terminals of the complementary pull-up circuit 20 and the pull-down circuit 10 are also cross-output, thereby achieving lower static power consumption.

[0039] As can be seen from the above embodiment, when the level shifter switches from low-level conversion in the low-voltage power domain to high-level conversion, the first charging circuit 30 charges node Q2 to eliminate or reduce competition between the complementary pull-up circuit 20 and the pull-down circuit 10 at node Q1, allowing node Q1 to smoothly switch from the high-voltage power domain's high level VDDH to a low level. When the level shifter switches from high-level conversion in the low-voltage power domain to high-voltage power domain to low-level conversion, the second charging circuit 40 charges node Q1 to eliminate or reduce competition between the complementary pull-up circuit 20 and the pull-down circuit 10 at node Q2, allowing node Q2 to smoothly switch from the high-voltage power domain's high level VDDH to a low level. Because competition between the complementary pull-up circuit 20 and the pull-down circuit 10 is eliminated or reduced, the voltage difference range during level conversion can be widened, for example, the voltage difference between the high-voltage power domain's high level VDDH and the high-voltage power domain can be large, and conversion energy consumption during level conversion can also be reduced. Furthermore, since the first charging circuit 30 and the second charging circuit 40 only briefly charge the node Q1 or the node Q2 when the pull-down circuit 10 pulls the node Q1 or the node Q2 down to a low level, the first charging circuit 30 and the second charging circuit 40 consume only a relatively small amount of power without increasing additional power consumption, thereby reducing the overall power consumption of the level converter.

[0040] Please refer to Figure 2 In some embodiments, the level output module 50 includes an inverting unit, which is used to invert the type of the input level and then output it. The power supply terminal of the inverting unit is connected to the high level VDDH of the high-voltage power domain, the input terminal of the inverting unit is connected to the node Q1, and the output terminal of the inverting unit is used to output the level of the high-voltage power domain. When the potential of the node Q1 is a low level, the inverting unit inverts the low level and outputs the high level VDDH of the high-voltage power domain. When the potential of the node Q1 is the high level VDDH of the high-voltage power domain, the inverting unit inverts the high level VDDH of the high-voltage power domain and outputs the low level of the high-voltage power domain. In some embodiments, the inverting unit can be implemented by an inverter. Since the node Q1 can reach the full swing of the high level VDDH of the high-voltage power domain, there will be no large static current when the inverter performs inverted output, thereby achieving low-power inverted output.

[0041] In some embodiments, the inverting unit is used to invert the type of input level twice before outputting it. The power supply terminal of the inverting unit is connected to the high level VDDH of the high-voltage power supply domain, the input terminal of the inverting unit is connected to node Q2, and the output terminal of the inverting unit is used to output the level of the high-voltage power supply domain. When the potential of node Q2 is a low level, the inverting unit inverts the low level twice and outputs the ground level of the high-voltage power supply domain. When the potential of node Q2 is a high level VDDH of the high-voltage power supply domain, the inverting unit inverts the high level VDDH of the high-voltage power supply domain twice and outputs the high level VDDH of the high-voltage power supply domain. In some embodiments, the inverting unit can be implemented using two cascaded inverters.

[0042] Please refer to Figure 2 、 Figure 3 and Figure 4 In some embodiments, the pull-down circuit 10 includes a transistor N3 and a transistor N4, and the complementary pull-up circuit 20 includes a transistor P3 and a transistor P4. The first electrode of transistor N3 is connected to the first output terminal and the second control terminal of the complementary pull-up circuit 20, namely, the second electrode of transistor P3 and the control electrode of transistor P4, respectively, to form a node Q1. The first electrode of transistor N4 is connected to the second output terminal and the first control terminal of the complementary pull-up circuit 20, namely, the control electrode of transistor P3 and the second electrode of transistor P4, respectively, to form a node Q2. The second electrodes of transistor N3 and transistor N4 are both connected to ground potential, and the first electrodes of transistor P3 and transistor P4 are both connected to the high voltage level VDDH of the high voltage power domain. The control electrode of transistor N3 is used to input the voltage level of the low voltage power domain, and the control electrode of transistor N4 is used to input the voltage level of the opposite type to that of the low voltage power domain.

[0043] Transistor N3 is configured to be turned on when the level of the low-voltage power domain is high to pull node Q1 down to a low level. Transistor N4 is configured to be turned on when the level of the low-voltage power domain is low to pull node Q2 down to a low level. Transistor P4 is configured to be turned on when node Q1 is low to pull node Q2 up to a high level VDDH of the high-voltage power domain. Transistor P3 is configured to be turned on when node Q2 is low to pull node Q1 up to a high level VDDH of the high-voltage power domain.

[0044] As can be seen from the above, when the voltage level of the low-voltage power domain is low, transistors N4 and P3 are turned on, causing the potential of Q1 to be the high voltage power domain's high voltage level VDDH, and the potential of node Q2 to be low. When the voltage level of the low-voltage power domain is high, transistors N3 and P4 are turned on, causing the potential of node Q1 to be low, and the potential of node Q2 to be the high voltage power domain's high voltage level VDDH. Because transistors N3, N4, P3, and P4 are all cross-connected, near-zero static power consumption is achieved between pull-down circuit 10 and complementary pull-up circuit 20. At the same time, when the level of the low-voltage power domain switches from a low level to a high level, or from a high level to a low level, there is current competition between transistors P3 and N3 at node Q1, and there is current competition between transistors P4 and N4 at node Q2. Therefore, the first charging circuit 30 is required to charge node Q2, thereby weakening the driving strength of transistor P3 and reducing its pull-up strength, making it easier for transistor N3 to pull node Q1 to a low level. The second charging circuit 40 charges node Q1, weakening the driving strength of transistor P4 and reducing its pull-up strength, making it easier for transistor N4 to pull node Q2 to a low level, thereby eliminating the competition between the complementary pull-up circuit 20 and the pull-down circuit 10.

[0045] In this embodiment, transistors N3 and N4 are N-type transistors, whose first electrodes are both sources, whose second electrodes are both drains, and whose control electrodes are both gates. Transistors P3 and P4 are P-type transistors, whose first electrodes are both drains, whose second electrodes are both sources, and whose control electrodes are both gates. It is understood that the type of transistors can be changed or the connection method can be adaptively modified as needed to achieve the same effect.

[0046] Please refer to Figure 2 and Figure 4 In some embodiments, the first charging circuit 30 includes a first current mirror circuit 32, a transistor N1, and a transistor N2. In some embodiments, the first current mirror circuit 32 includes a transistor P1 and a transistor P2. The power supply terminal of the first current mirror circuit 32 is connected to the high voltage level VDDH of the high voltage power domain, that is, the first electrodes of transistors P1 and P2. The first output terminal of the first current mirror circuit 32 is connected to the first electrode of transistor N1, that is, the second electrode of transistor P1. The second electrode of transistor P1 is also connected to its control electrode and the control electrode of transistor P2. The second output terminal of the first current mirror circuit 32 is connected to node Q2, that is, the second electrode of transistor P2. The second electrode of transistor N1 is connected to the first electrode of transistor N2, and the second electrode of transistor N2 is connected to the ground potential. The control electrode of transistor N1 is connected to node Q1, and the control electrode of transistor N2 is used to input the voltage level of the low voltage power domain.

[0047] Transistor N2 is configured to be turned on when the voltage level of the low-voltage power domain is high, and transistor N1 is configured to be turned on when the voltage level of node Q1 is high. When both transistors N1 and N2 are turned on, transistors P1 and P2 are also turned on, and current is output to node Q2 through the second electrode of transistor P2.

[0048] As can be seen from the above description, transistors N1 and N2 are used to control the on / off state of the first current mirror circuit 32. Specifically, only when both transistors N1 and N2 are turned on simultaneously does the first current mirror circuit 32 output current to node Q2. In this embodiment, when the level shifter maintains a low-level transition from the low-voltage power domain to the high-voltage power domain, only transistor N1 is turned on. At this time, the first current mirror circuit 32 is turned off and does not generate any quiescent current. When the level converter switches from low-level conversion (from the low-voltage power domain to the high-voltage power domain) to high-level conversion, competition exists between the pull-down circuit 10 and the complementary pull-up circuit 20, maintaining nodes Q1 and Q2 at the high-voltage power domain's high level VDDH and low level, respectively. At this time, both transistors N1 and N2 are turned on, thereby enabling the first current mirror circuit 32 to charge node Q2, successfully switching the level converter from low-level conversion (from the low-voltage power domain to the high-voltage power domain) to high-level conversion. After the successful switching, nodes Q1 and Q2 are again maintained at the low-level and high-voltage power domain's high level VDDH, respectively, ensuring that the complementary pull-up and pull-down circuits are in a state without quiescent current. At this time, only transistor N2 is turned on, thereby disabling the first current mirror circuit 32 again, and similarly, no quiescent current is generated. Therefore, the first charging circuit 30 can alleviate the competition between the complementary pull-up circuit 20 and the pull-down circuit 10, while simultaneously preventing the generation of quiescent current and excessive power consumption.

[0049] Please refer to Figure 2 and Figure 3 In some embodiments, the second charging circuit 40 includes a second current mirror circuit 42, a transistor N5, and a transistor N6. In some embodiments, the second current mirror circuit 42 includes a transistor P5 and a transistor P6. The power supply terminal of the second current mirror circuit 42 is connected to the high voltage VDDH of the high voltage power domain, that is, the first electrodes of transistors P5 and P6. The first output terminal of the second current mirror circuit 42 is connected to the first electrode of transistor N5, that is, the second electrode of transistor P6. The second electrode of transistor P6 is also connected to its control electrode and the control electrode of transistor P5. The second output terminal of the second current mirror circuit 42 is connected to node Q1, that is, the second electrode of transistor P5. The second electrode of transistor N5 is connected to the first electrode of transistor N6, the second electrode of transistor N6 is connected to ground potential, the control electrode of transistor N5 is connected to node Q2, and the control electrode of transistor N6 is used to input a voltage level of the opposite type to that of the low voltage power domain.

[0050] Transistor N6 is configured to be turned on when the voltage level of the low-voltage power domain is low, and transistor N5 is configured to be turned on when the voltage level of node Q2 is high. When both transistors N5 and N6 are turned on, transistors P5 and P6 are also turned on, and current is output to node Q1 through the second electrode of transistor P5.

[0051] As can be seen from the above, the operating principle of the second charging circuit 40 in this embodiment is the same as that of the first charging circuit 30. Therefore, the second charging circuit 40 can also alleviate the competition between the complementary pull-up circuit 20 and the pull-down circuit 10, while not generating static current or excessive power consumption. This will not be further described here. In this embodiment, the pull-up strength of the complementary pull-up circuit 20 is dynamically adjusted by the first and second charging circuits 30 and 40, thereby enabling the level shifter to have good delay scalability. Even when the difference between the high voltage level VDDL of the low-voltage power domain and the high voltage level VDDH of the high-voltage power domain is small, the delay is also reduced.

[0052] In this embodiment, transistors N1, N2, N5, and N6 are N-type transistors, whose first electrodes are all sources, whose second electrodes are all drains, and whose control electrodes are all gates. Transistors P1, P2, P5, and P6 are P-type transistors, whose first electrodes are all drains, whose second electrodes are all sources, and whose control electrodes are all gates. It is understood that the transistor type can be changed or the connection method can be adaptively modified as needed to achieve the same effect.

[0053] Please refer to Figure 2 and Figure 5 In some embodiments, the pull-down circuit 10 includes a pull-down unit and a voltage drop unit. In some embodiments, the pull-down unit includes a transistor N3 and a transistor N4. The first terminal of the voltage drop unit is connected to the first output terminal and the second control terminal of the complementary pull-up circuit 20, namely, the second electrode of transistor P3 and the control electrode of transistor P4, respectively, to form a node Q1. The power supply terminal of the pull-down unit is connected to the ground potential, namely, the second electrodes of transistor N3 and transistor N4. The second terminal of the voltage drop unit is connected to the first output terminal of the pull-down unit, namely, the first electrode of transistor N3, to form a node Q3. The first control terminal of the pull-down unit is used to input the voltage level of the low-voltage power domain, namely, the control electrode of transistor N3. The second control terminal of the pull-down unit is used to input the voltage level of the opposite type to the voltage level of the low-voltage power domain, namely, the control electrode of transistor N4. The second output terminal of the pull-down unit is connected to the second output terminal and the first control terminal of the complementary pull-up circuit 20, namely, the first electrode of transistor N4 is connected to the control electrode of transistor P3 and the second electrode of transistor P4, respectively, to form a node Q2.

[0054] The voltage drop unit is configured to generate a predetermined voltage drop between its first and second terminals. Transistor N3 is configured to turn on when the voltage level of the low-voltage power domain is high, thereby pulling node Q3 down to a low level and, through the voltage drop unit, pulling node Q1 down to a low level. Transistor N4 is configured to turn on when the voltage level of the low-voltage power domain is low, thereby pulling node Q2 down to a low level.

[0055] As can be seen from the above, because the voltage drop unit can generate a voltage drop between nodes Q1 and Q3, the potential of node Q1 is always greater than that of node Q3. This can further weaken transistor P3 when transistors N3 and P3 compete at node Q1, thereby further improving the speed of the level converter switching from low-level conversion to high-level conversion when switching from the low-voltage power domain to the high-voltage power domain. It is understandable that the voltage drop unit can also be connected between transistors P4 and N4, in which case node Q2 can be connected to the input terminal of the level output module 50.

[0056] In some embodiments, the voltage drop unit includes a transistor N8 , wherein a first electrode of the transistor N8 is connected to its control electrode, a second electrode of the transistor P3 , and a control electrode of the transistor P4 to form a node Q1 , and a second electrode of the transistor N8 is connected to a first electrode of the transistor N3 .

[0057] In some embodiments, the voltage drop unit includes a resistor, a first end of which is connected to the second electrode of transistor P3 and the control electrode of transistor P4 to form a node Q1 , and a second end of which is connected to the first electrode of transistor N3 .

[0058] In some embodiments, the voltage drop unit includes a diode, the anode of which is connected to the second electrode of P3 and the control electrode of transistor P4 to form a node Q1, and the cathode of which is connected to the first electrode of transistor N3.

[0059] Please refer to Figure 2 and Figure 5 In some embodiments, the level output module 50 includes a transistor P7 and a transistor N7. A first electrode of transistor P7 is connected to the high level VDDH of the high voltage power domain, a control electrode of transistor P7 is connected to node Q1, a second electrode of transistor P7 is connected to the first electrode of transistor N7, a second electrode of transistor N7 is connected to ground potential, and a control electrode of transistor N7 is connected to node Q3. When node Q1 is at the high level VDDH of the high voltage power domain, transistor N7 is turned on, and the node between transistors P7 and N7 outputs a low level. When node Q3 is at a low level, transistor P7 is turned on, and the node between transistors P7 and N7 outputs the high level VDDH of the high voltage power domain.

[0060] Example 2:

[0061] This embodiment provides a low-power level converter for ultra-wide range voltage conversion. The difference between this embodiment and the first embodiment is that the first control terminal and the second control terminal of the pull-down circuit 10 are both used to input the level (IN) of the low-voltage power domain, and the control terminals of the first charging circuit 30 and the second charging circuit 40 are both used to input the level (IN) of the low-voltage power domain. The difference is described in detail below.

[0062] Please refer to Figure 5 In some embodiments, the pull-down circuit 10 includes a pull-down unit and a voltage drop unit. In some embodiments, the pull-down unit includes transistors N3 and N4. The first terminal of the voltage drop unit is connected to the first output terminal and the second control terminal of the complementary pull-up circuit 20, namely, the second electrode of transistor P3 and the control electrode of transistor P4, respectively, to form a node Q1. The second terminal of the voltage drop unit is connected to the first output terminal of the pull-down unit, namely, the first electrode of transistor N3, to form a node Q3. The first control terminal of the pull-down unit is used to input the voltage level of the low-voltage power domain, namely, the control electrode of transistor N3. The second control terminal of the pull-down unit is used to input the voltage level of the low-voltage power domain, namely, the second electrode of transistor N4. The second output terminal of the pull-down unit is connected to the second output terminal and the first control terminal of the complementary pull-up circuit 20, namely, the first electrode of transistor N4 is connected to the control electrode of transistor P3 and the second electrode of transistor P4, respectively, to form a node Q2. The second electrode of transistor N3 is connected to ground potential, and the control electrode of transistor N4 is connected to the high voltage level VDDL of the low-voltage power domain.

[0063] The voltage drop unit is configured to generate a predetermined voltage drop between its first and second terminals. Transistor N3 is configured to turn on when the voltage level of the low-voltage power domain is high, thereby pulling node Q3 down to a low level and, through the voltage drop unit, pulling node Q1 down to a low level. Transistor N4 is configured to turn on when the voltage level of the low-voltage power domain is low, thereby pulling node Q2 down to a low level.

[0064] As can be seen from the above, since the voltage drop unit can generate a voltage drop between node Q1 and node Q3, the potential of node Q1 is always greater than that of node Q3, so that when transistor N3 and transistor P3 compete at node Q1, transistor P3 is further weakened, thereby further improving the speed of the level converter switching from the low-voltage power domain to the high-voltage power domain from the low-level conversion to the high-level conversion. It is understandable that the voltage drop unit can also be connected between transistor P4 and transistor N4. In this case, node Q2 can be connected to the input end of the level output module 50.

[0065] Please refer to Figure 5In some embodiments, the second charging circuit 40 includes a second current mirror circuit 42, a transistor N5, and a transistor N6. In some embodiments, the second current mirror circuit 42 includes a transistor P5 and a transistor P6. The power supply terminal of the second current mirror circuit 42 is connected to the high voltage VDDH of the high voltage power domain, that is, the first electrodes of transistors P5 and P6. The first output terminal of the second current mirror circuit 42 is connected to the first electrode of transistor N5, that is, the second electrode of transistor P6. The second electrode of transistor P6 is also connected to its control electrode and the control electrode of transistor P5. The second output terminal of the second current mirror circuit 42 is connected to node Q1, that is, the second electrode of transistor P5. The second electrode of transistor N5 is connected to the first electrode of transistor N6. The second electrode of transistor N6 is used to input the voltage level of the low voltage power domain. The control electrode of transistor N5 is connected to node Q2, and the control electrode of transistor N6 is connected to the high voltage VDDL of the low voltage power domain.

[0066] Transistor N6 is configured to be turned on when the voltage level of the low-voltage power domain is low, and transistor N5 is configured to be turned on when the voltage level of node Q2 is high. When both transistors N5 and N6 are turned on, transistors P5 and P6 are also turned on, and current is output to node Q1 through the second electrode of transistor P5.

[0067] As can be seen from the above, since the control electrodes of transistors N4 and N6 both input the high level VDDL of the low-voltage power domain, and then are directly controlled to be turned on and off by the level of the low-voltage power domain input by the second electrode, the speed of the level converter switching from high-level conversion of the low-voltage power domain to high-voltage power domain to low-level conversion can be further improved.

[0068] Please refer to Figure 5 and Figure 2 In some embodiments, transistors P1, P2, P3, P4, P5, and P6 are all high threshold voltage (HVT) transistors. Transistor N2, N6, and N8 are all low threshold voltage (LVT) transistors. Meanwhile, transistors N1, N3, N4, N5, N7, and P7 are all normal threshold voltage (RVT) transistors. This embodiment uses multi-threshold voltage transistors with a long channel length and a multi-finger structure to implement the proposed level converter, thereby achieving a better balance between conversion speed, overall power, and area efficiency.

[0069] The above examples are used to illustrate the present invention, which are only used to help understand the present invention and are not intended to limit the present invention. Those skilled in the art can make several simple deductions, modifications or substitutions based on the concept of the present invention.

Claims

1. A low-power level converter for ultra-wide range voltage conversion, characterized in that: include: A pull-down circuit, a complementary pull-up circuit, a first charging circuit, a second charging circuit and a level output module; The first control terminal of the pull-down circuit is used to input the level of the low-voltage power domain, and the second control terminal is used to input a level of the opposite level type of the low-voltage power domain. The first output terminal of the pull-down circuit is respectively connected to the first output terminal and the second control terminal of the complementary pull-up circuit to form a node Q1. The second output terminal of the pull-down circuit is respectively connected to the second output terminal and the first control terminal of the complementary pull-up circuit to form a node Q2. The control end of the first charging circuit is used to input the level of the low-voltage power domain, and the output end is connected to the node Q2. The control end of the second charging circuit is used to input the level type opposite to the level type of the low-voltage power domain, and the output end is connected to the node Q1. The input end of the level output module is used to be connected to at least the node Q1 or the node Q2, and the level output module is used to output the level of the high-voltage power domain according to at least the potential of the node Q1 or the node Q2, and the level of the high-voltage power domain is the same type as the level of the low-voltage power domain; In which, the pull-down circuit is used to pull down the node Q1 to a low level when the level of the low-voltage power domain is a high level, and to pull down the node Q2 to a low level when the level of the low-voltage power domain is a low level. In the process of the pull-down circuit pulling down the node Q1 to a low level, the first charging circuit is used to output current to the node Q2, so that the potential of the node Q2 rises. In the process of the pull-down circuit pulling down the node Q2 to a low level, the second charging circuit is used to output current to the node Q1, so that the potential of the node Q1 rises. The complementary pull-up circuit is used to pull up the node Q2 to the high level of the high-voltage power domain when the node Q1 is a low level, and to pull up the node Q1 to the high level of the high-voltage power domain when the node Q2 is a low level.

2. The low-power level converter for ultra-wide range voltage conversion according to claim 1, wherein: The pull-down circuit includes a transistor N3 and a transistor N4; The first electrode of the transistor N3 is respectively connected to the first output terminal and the second control terminal of the complementary pull-up circuit to form a node Q1, the first electrode of the transistor N4 is respectively connected to the second output terminal and the first control terminal of the complementary pull-up circuit to form a node Q2, the second electrodes of the transistor N3 and the transistor N4 are both connected to the ground potential, the control electrode of the transistor N3 is used to input the level of the low-voltage power domain, and the control electrode of the transistor N4 is used to input a level of the opposite type to the level of the low-voltage power domain; The transistor N3 is turned on when the level of the low-voltage power domain is high to pull the node Q1 down to a low level. The transistor N4 is turned on when the level of the low-voltage power domain is low to pull the node Q2 down to a low level.

3. The low-power level converter for ultra-wide range voltage conversion according to claim 1, wherein: The second charging circuit includes a second current mirror circuit, a transistor N5 and a transistor N6; A first output terminal of the second current mirror circuit is connected to a first electrode of the transistor N5, a second output terminal is connected to a node Q1, a second electrode of the transistor N5 is connected to a first electrode of the transistor N6, a second electrode of the transistor N6 is connected to a ground potential, a control electrode of the transistor N5 is connected to a node Q2, and a control electrode of the transistor N6 is used to input a level opposite to that of the low-voltage power domain; The transistor N6 is used to be turned on when the level of the low-voltage power domain is low, and the transistor N5 is used to be turned on when the node Q2 is high. The second current mirror circuit is used to output current to the node Q1 through the second output terminal when both the transistor N5 and the transistor N6 are turned on, until the potential of the node Q2 is pulled down to a low level by the pull-down circuit, so that the transistor N5 is turned off.

4. The low-power level converter for ultra-wide range voltage conversion according to claim 3, wherein: The second current mirror circuit includes a transistor P5 and a transistor P6; The first electrodes of the transistors P5 and P6 are both connected to the high level of the high-voltage power supply domain, the second electrode of the transistor P6 is respectively connected to its control electrode, the control electrode of the transistor P5 and the first electrode of the transistor N5, and the second electrode of the transistor P5 is connected to the node Q1. When the transistors N5 and N6 are both turned on, the transistors P5 and P6 are also turned on and output current to the node Q1 through the second electrode of the transistor P5.

5. The low-power level converter for ultra-wide range voltage conversion according to claim 1, wherein: The pull-down circuit includes a pull-down unit and a voltage drop unit; The first end of the voltage drop unit is respectively connected to the first output end and the second control end of the complementary pull-up circuit to form a node Q1, the second end of the voltage drop unit is connected to the first output end of the pull-down unit to form a node Q3, the first control end of the pull-down unit is used to input the level of the low-voltage power domain, the second control end is used to input the level type opposite to the level type of the low-voltage power domain, and the second output end is respectively connected to the second output end and the first control end of the complementary pull-up circuit to form a node Q2; The voltage drop unit is used to generate a preset voltage drop between its first end and the second end, and the pull-down unit is used to pull the node Q3 down to a low level when the level of the low-voltage power domain is a high level, and pull the node Q1 down to a low level through the voltage drop unit, and pull the node Q2 down to a low level when the level of the low-voltage power domain is a low level.

6. The low-power level converter for ultra-wide range voltage conversion according to claim 5, wherein: The pull-down unit includes a transistor N3 and a transistor N4; A first electrode of the transistor N3 is connected to the second end of the voltage drop unit, a first electrode of the transistor N4 is respectively connected to the second output end and the first control end of the complementary pull-up circuit to form a node Q2, second electrodes of the transistor N3 and the transistor N4 are both connected to the ground potential, a control electrode of the transistor N3 is used to input a level of the low-voltage power domain, and a control electrode of the transistor N4 is used to input a level of a type opposite to that of the low-voltage power domain; The transistor N3 is turned on when the level of the low-voltage power domain is high to pull the node Q1 down to a low level. The transistor N4 is turned on when the level of the low-voltage power domain is low to pull the node Q2 down to a low level.

7. The low-power level converter for ultra-wide range voltage conversion according to claim 5, wherein: The voltage drop unit includes a transistor N8, a first electrode of the transistor N8 is respectively connected to its control electrode, the first output terminal and the second control terminal of the complementary pull-up circuit to form a node Q1, and a second electrode of the transistor N8 is connected to the first output terminal of the pull-down unit; Alternatively, the voltage drop unit includes a resistor, a first end of the resistor is respectively connected to the first output end and the second control end of the complementary pull-up circuit to form a node Q1, and a second end of the resistor is connected to the first output end of the pull-down unit; Alternatively, the voltage drop unit includes a diode, an anode of the diode is respectively connected to the first output terminal and the second control terminal of the complementary pull-up circuit to form a node Q1, and a cathode of the diode is connected to the first output terminal of the pull-down unit.

8. The low-power level converter for ultra-wide range voltage conversion according to claim 5, wherein: The level output module includes a transistor P7 and a transistor N7; The first electrode of the transistor P7 is connected to the high level of the high-voltage power supply domain, the control electrode is connected to the node Q1, the second electrode is connected to the first electrode of the transistor N7, the second electrode of the transistor N7 is connected to the ground potential, and the control electrode is connected to the node Q3. When the node Q1 is the high level of the high-voltage power supply domain, the transistor N7 is turned on and the node between the transistor P7 and the transistor N7 outputs a low level. When the node Q3 is the low level, the transistor P7 is turned on and the node between the transistor P7 and the transistor N7 outputs a high level of the high-voltage power supply domain.

9. The low-power level converter for ultra-wide range voltage conversion according to claim 1, wherein: The complementary pull-up circuit includes a transistor P3 and a transistor P4; The first electrodes of the transistor P3 and the transistor P4 are both connected to the high level of the high-voltage power domain, the second electrode of the transistor P3 and the control electrode of the transistor P4 are connected to the first output end of the pull-down circuit to form a node Q1, and the control electrode of the transistor P3 and the second electrode of the transistor P4 are connected to the second output end of the pull-down circuit to form a node Q2; The transistor P4 is used to be turned on when the node Q1 is at a low level to pull the node Q2 up to a high level in the high voltage power domain. The transistor P3 is used to be turned on when the node Q2 is at a low level to pull the node Q1 up to a high level in the high voltage power domain.

10. The low-power level converter for ultra-wide range voltage conversion according to claim 1, wherein: The first charging circuit includes a first current mirror circuit, a transistor N1 and a transistor N2; A first output terminal of the first current mirror circuit is connected to a first electrode of the transistor N1, a second output terminal is connected to a node Q2, a second electrode of the transistor N1 is connected to a first electrode of the transistor N2, a second electrode of the transistor N2 is connected to a ground potential, a control electrode of the transistor N1 is connected to the node Q1, and a control electrode of the transistor N2 is used to input a voltage level of the low-voltage power domain; The transistor N2 is used to be turned on when the level of the low-voltage power domain is high, and the transistor N1 is used to be turned on when the node Q1 is high. The first current mirror circuit is used to output current to the node Q2 through the second output terminal when both the transistor N1 and the transistor N2 are turned on, until the potential of the node Q1 is pulled to a low level by the pull-down circuit, so that the transistor N1 is turned off.

11. The low-power level converter for ultra-wide range voltage conversion according to claim 1, wherein: The level output module includes an inverting unit; The power supply end of the inverting unit is connected to the high level of the high-voltage power domain, the input end of the inverting unit is connected to the node Q1, the output end is used to output the level of the high-voltage power domain, and the inverting unit is used to invert the type of the level of the node Q1 and then output it; Alternatively, the input end of the inverting unit is connected to the node Q2, the output end is used to output the level of the high voltage power domain, and the inverting unit is used to invert the type of the level of the node Q2 twice before outputting it.

12. A low-power level converter for ultra-wide range voltage conversion, characterized in that: include: A pull-down circuit, a complementary pull-up circuit, a first charging circuit, a second charging circuit and a level output module; The first control terminal and the second control terminal of the pull-down circuit are both used to input the level of the low-voltage power domain, the first output terminal of the pull-down circuit is respectively connected to the first output terminal and the second control terminal of the complementary pull-up circuit, and form a node Q1, and the second output terminal of the pull-down circuit is respectively connected to the second output terminal and the first control terminal of the complementary pull-up circuit, and form a node Q2; The control terminals of the first charging circuit and the second charging circuit are both used to input the voltage level of the low-voltage power domain, the output terminal of the first charging circuit is connected to the node Q2, and the output terminal of the second charging circuit is connected to the node Q1; The input end of the level output module is at least used to connect to the node Q1 or the node Q2, and the level output module is used to output the level of the high-voltage power domain according to the potential of the node Q1 or the node Q2, and the level of the high-voltage power domain is the same as the level of the low-voltage power domain; In which, the pull-down circuit is used to pull down the node Q1 to a low level when the level of the low-voltage power domain is a high level, and to pull down the node Q2 to a low level when the level of the low-voltage power domain is a low level. In the process of the pull-down circuit pulling down the node Q1 to a low level, the first charging circuit is used to output current to the node Q2, so that the potential of the node Q2 rises. In the process of the pull-down circuit pulling down the node Q2 to a low level, the second charging circuit is used to output current to the node Q1, so that the potential of the node Q1 rises. The complementary pull-up circuit is used to pull up the node Q2 to the high level of the high-voltage power domain when the node Q1 is a low level, and to pull up the node Q1 to the high level of the high-voltage power domain when the node Q2 is a low level.

13. The low-power level converter for ultra-wide range voltage conversion according to claim 12, wherein: The pull-down circuit includes a pull-down unit and a voltage drop unit; The first end of the voltage drop unit is respectively connected to the first output end and the second control end of the complementary pull-up circuit to form a node Q1, the second end of the voltage drop unit is connected to the first output end of the pull-down unit to form a node Q3, the first control end and the second control end of the pull-down unit are both used to input the level of the low-voltage power domain, and the second output end is respectively connected to the second output end and the first control end of the complementary pull-up circuit to form a node Q2; The voltage drop unit is used to generate a preset voltage drop between its first end and the second end, and the pull-down unit is used to pull the node Q3 down to a low level when the level of the low-voltage power domain is a high level, and pull the node Q1 down to a low level through the voltage drop unit, and pull the node Q2 down to a low level when the level of the low-voltage power domain is a low level.

14. The low-power level converter for ultra-wide range voltage conversion according to claim 13, wherein: The pull-down unit includes a transistor N3 and a transistor N4; The first electrode of the transistor N3 is connected to the second end of the voltage drop unit to form a node Q3, the second electrode of the transistor N3 is connected to the ground potential, the first electrode of the transistor N4 is respectively connected to the second output end and the first control end of the complementary pull-up circuit to form a node Q2, the control electrode of the transistor N3 and the second electrode of the transistor N4 are both used to input the level of the low-voltage power domain, and the control electrode of the transistor N4 is connected to the high level of the low-voltage power domain; The transistor N3 is turned on when the level of the low-voltage power domain is high to pull the node Q3 down to a low level. The transistor N4 is turned on when the level of the low-voltage power domain is low to pull the node Q2 down to a low level.

15. The low-power level converter for ultra-wide range voltage conversion according to claim 13, wherein: The level output module includes a transistor P7 and a transistor N7; The first electrode of the transistor P7 is connected to the high level of the high-voltage power supply domain, the control electrode is connected to the node Q1, the second electrode is connected to the first electrode of the transistor N7, the second electrode of the transistor N7 is connected to the ground potential, and the control electrode is connected to the node Q3. When the node Q1 is the high level of the high-voltage power supply domain, the transistor N7 is turned on and the node between the transistor P7 and the transistor N7 outputs a low level. When the node Q3 is the low level, the transistor P7 is turned on and the node between the transistor P7 and the transistor N7 outputs a high level of the high-voltage power supply domain.

16. The low-power level converter for ultra-wide range voltage conversion according to claim 13, wherein: The voltage drop unit includes a transistor N8, a first electrode of the transistor N8 is respectively connected to its control electrode, the first output terminal and the second control terminal of the complementary pull-up circuit to form a node Q1, and a second electrode of the transistor N8 is connected to the first output terminal of the pull-down unit to form a node Q3; Alternatively, the voltage drop unit includes a resistor, a first end of the resistor is connected to the first output end and the second control end of the complementary pull-up circuit respectively to form a node Q1, and a second end of the resistor is connected to the first output end of the pull-down unit to form a node Q3; Alternatively, the voltage drop unit includes a diode, the anode of the diode is respectively connected to the first output terminal and the second control terminal of the complementary pull-up circuit to form a node Q1, and the cathode of the diode is connected to the first output terminal of the pull-down unit to form a node Q3.

17. The low-power level converter for ultra-wide range voltage conversion according to claim 12 or 14, characterized in that: The second charging circuit includes a second current mirror circuit, a transistor N5 and a transistor N6; A first output terminal of the second current mirror circuit is connected to a first electrode of the transistor N5, a second output terminal is connected to a node Q1, a second electrode of the transistor N5 is connected to a first electrode of the transistor N6, a second electrode of the transistor N6 is used to input a level of the low-voltage power domain, a control electrode of the transistor N5 is connected to a node Q2, and a control electrode of the transistor N6 is connected to a high level of the low-voltage power domain; The transistor N6 is used to be turned on when the level of the low-voltage power domain is low, and the transistor N5 is used to be turned on when the node Q2 is high. The second current mirror circuit is used to output current to the node Q1 through the second output terminal when both the transistor N5 and the transistor N6 are turned on, until the potential of the node Q2 is pulled down to a low level by the pull-down circuit, so that the transistor N5 is turned off.

18. The low-power level converter for ultra-wide range voltage conversion according to claim 17, wherein: The second current mirror circuit includes a transistor P5 and a transistor P6; The first electrodes of the transistors P5 and P6 are both connected to the high level of the high-voltage power supply domain, the second electrode of the transistor P6 is respectively connected to its control electrode, the control electrode of the transistor P5 and the first electrode of the transistor N5, and the second electrode of the transistor P5 is connected to the node Q1. When the transistors N5 and N6 are both turned on, the transistors P5 and P6 are also turned on and output current to the node Q1 through the second electrode of the transistor P5.

19. The low-power level converter for ultra-wide range voltage conversion according to claim 12, wherein: The complementary pull-up circuit includes a transistor P3 and a transistor P4; The first electrodes of the transistor P3 and the transistor P4 are both connected to the high level of the high-voltage power domain, the second electrode of the transistor P3 and the control electrode of the transistor P4 are connected to the first output end of the pull-down circuit to form a node Q1, and the control electrode of the transistor P3 and the second electrode of the transistor P4 are connected to the second output end of the pull-down circuit to form a node Q2; The transistor P4 is used to be turned on when the node Q1 is at a low level to pull the node Q2 up to a high level in the high voltage power domain. The transistor P3 is used to be turned on when the node Q2 is at a low level to pull the node Q1 up to a high level in the high voltage power domain.

20. The low-power level converter for ultra-wide range voltage conversion according to claim 12, wherein: The first charging circuit includes a first current mirror circuit, a transistor N1 and a transistor N2; A first output terminal of the first current mirror circuit is connected to a first electrode of the transistor N1, a second output terminal is connected to a node Q2, a second electrode of the transistor N1 is connected to a first electrode of the transistor N2, a second electrode of the transistor N2 is connected to a ground potential, a control electrode of the transistor N1 is connected to the node Q1, and a control electrode of the transistor N2 is used to input a voltage level of the low-voltage power domain; The transistor N2 is used to be turned on when the level of the low-voltage power domain is high, and the transistor N1 is used to be turned on when the node Q1 is high. The first current mirror circuit is used to output current to the node Q2 through the second output terminal when both the transistor N1 and the transistor N2 are turned on, until the potential of the node Q1 is pulled to a low level by the pull-down circuit, so that the transistor N1 is turned off.

21. The low-power level converter for ultra-wide range voltage conversion according to claim 20, wherein: The first current mirror circuit includes a transistor P1 and a transistor P2; The first electrodes of the transistors P1 and P2 are both connected to the high level of the high-voltage power supply domain, the second electrode of the transistor P1 is respectively connected to its control electrode, the control electrode of the transistor P2 and the first electrode of the transistor N1, and the second electrode of the transistor P2 is connected to the node Q2. When the transistors N1 and N2 are both turned on, the transistors P1 and P2 are also turned on and output current to the node Q2 through the second electrode of the transistor P2.

22. The low-power level converter for ultra-wide range voltage conversion according to claim 12, wherein: The level output module includes an inverting unit; The power supply end of the inverting unit is connected to the high level of the high-voltage power domain, the input end of the inverting unit is connected to the node Q1, the output end is used to output the level of the high-voltage power domain, and the inverting unit is used to invert the type of the level of the node Q1 and then output it; Alternatively, the input end of the inverting unit is connected to the node Q2, the output end is used to output the level of the high voltage power domain, and the inverting unit is used to invert the type of the level of the node Q2 twice before outputting it.

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