Sub-block interleaving for polar coding systems, procedures, and signaling

Abstract

A system, method, and tool for interleaving coded bits are disclosed. A wireless transmit / receive unit (WTRU) may generate a plurality of polarity coded bits using polarity coding. The WTRU may group the plurality of polarity coded bits into sub-blocks of equal size in a sequential manner. The WTRU may apply sub-block interleaving to the sub-blocks using an interleaver pattern. The sub-blocks associated with a subset of the sub-blocks may be interleaved, and sub-blocks associated with another subset of the sub-blocks may not be interleaved. The sub-block interleaving may include interleaving on the sub-blocks without interleaving bits associated with each of the sub-blocks. The WTRU may concatenate bits from each of the interleaved sub-blocks to generate interleaved bits, and store the interleaved bits associated with the interleaved sub-blocks in a circular buffer. The WTRU may select a plurality of bits from the interleaved bits for transmission.

Description

[0001] This application is a divisional application of Chinese patent application No. 201880020225.X, entitled “Sub-block interleaving for polar coding systems, processes and signaling”, filed on March 21, 2018, the contents of which are incorporated herein by reference.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims the benefit of U.S. Provisional Patent Application No. 62 / 474,875 filed on March 22, 2017, U.S. Provisional Patent Application No. 62 / 500,887 filed on May 3, 2017, U.S. Provisional Patent Application No. 62 / 519,700 filed on June 14, 2017, U.S. Provisional Patent Application No. 62 / 545,615 filed on August 15, 2017, and U.S. Provisional Patent Application No. 62 / 556,104 filed on September 8, 2017, the contents of which are incorporated herein by reference. Background Art

[0004] Mobile communications are continuously evolving. The fifth generation of mobile communication technology may be referred to as 5G. 5G mobile wireless communication systems may implement various radio access technologies (RATs), including New Radio (NR). NR use cases may include, for example, extreme mobile broadband (eMBB), ultra-reliable and low-latency communications (URLLC), and massive machine-type communications (mMTC). Existing coding schemes and processing of coded bits used to transmit control information and / or data are supplemented by new coding schemes and processing mechanisms for coded bits. Summary of the Invention

[0005] Disclosed are systems, methods, and tools for interleaving polarity-coded bits as part of rate matching. A wireless transmit / receive unit (WTRU) may generate a plurality of polarity-coded bits using polarity coding. The plurality of polarity-coded bits may be generated using a mother code length. The WTRU may divide the plurality of polarity-coded bits into sub-blocks of equal size. The polarity-coded bits may be divided into sub-blocks in a sequential manner. The length of each sub-block may be a ratio of the mother code length to the number of sub-blocks. The WTRU may apply sub-block interleaving to the sub-blocks using an interleaver pattern. The interleaver pattern may be given by d1() in the following equation:

[0006] Subblocks associated with a subset of the subblocks are interleaved, while subblocks associated with another subset of the subblocks are not interleaved. The subblock-based interleaving includes interleaving across the subblocks without interleaving the bits associated with each subblock. For example, groups of bits or subblocks may be interleaved, while bits within a subblock may not be interleaved. The interleaved subblock subsets are contiguous and non-overlapping with the non-interleaved subblock subsets.

[0007] The WTRU may concatenate bits from each interleaved sub-block to generate interleaved bits. For example, the concatenated bits may be formed based on the interleaved sub-blocks, while the bits within each of the sub-blocks are not interleaved. The bits associated with each interleaved sub-block may be concatenated sequentially. The WTRU may store the interleaved bits associated with the interleaved sub-block in a circular buffer. The WTRU may select a plurality of bits (e.g., a plurality of consecutive bits) from the interleaved bits for transmission. The plurality of bits may be stored consecutively in the circular buffer. The plurality of bits may be selected based on a rate matching scheme. The rate matching scheme may be determined based on a mother code length, a rate matching output size, and a code rate. The rate matching scheme may be one of a repetition scheme, a puncturing scheme, or a shortening scheme. For example, when the rate matching output size is greater than the mother code length, the rate matching scheme may be a repetition scheme. When the rate matching output size is less than the mother code length, the rate matching scheme may be a shortening scheme or a puncturing scheme. The selection between the shortening scheme and the puncturing scheme may be based on the code rate.

[0008] The first subset of interleaved subblocks may include middle subblocks of the plurality of subblocks, while the second subset of non-interleaved subblocks may be an even number of subblocks. The second subset of subblocks may include an equal number of subblocks on each side of the first subset of subblocks. The third subset of interleaved subblocks may be adjacent to the second subset of subblocks. The fourth subset of non-interleaved subblocks may include the first subset of subblocks, the second subset of subblocks, and subblocks outside the third subset of subblocks. The fourth subset of subblocks may be adjacent to the third subset of subblocks. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A is a system diagram illustrating an exemplary communication system in which one or more disclosed embodiments may be implemented.

[0010] Figure 1B is a diagram showing that according to an embodiment, Figure 1A A system diagram of an exemplary wireless transmit / receive unit (WTRU) for use within a communication system is shown.

[0011] Figure 1C is a diagram showing that according to an embodiment, Figure 1AA system diagram of an exemplary radio access network (RAN) and an exemplary core network (CN) used within the illustrated communication system.

[0012] Figure 1D is a diagram showing that according to an embodiment, Figure 1A A system diagram of another exemplary RAN and another exemplary CN used within the communication system is shown.

[0013] Figure 2 An exemplary polar encoder is shown.

[0014] Figure 3 An exemplary polar encoding is shown.

[0015] Figure 4 An example of parity check (PC) polar encoding is shown.

[0016] Figure 5 An example of processing control information using polarity encoding is shown.

[0017] Figure 6 An exemplary implementation of rate matching control is shown.

[0018] Figure 7 Exemplary rate matching is shown.

[0019] Figure 8 An exemplary bit selection is shown.

[0020] Figure 9 An exemplary bit selection is shown.

[0021] Figure 10 An exemplary bit selection is shown.

[0022] Figure 11 An exemplary bit selection is shown.

[0023] Figure 12 An exemplary bit selection is shown.

[0024] Figure 13 An exemplary encoding of a cyclic redundancy check (CRC)-assisted (CA) polar code with a long CRC is shown.

[0025] Figure 14 An exemplary distribution of decoding of CA polar codes with long CRC is shown.

[0026] Figure 15 An exemplary encoding of a CA polar code with two separate CRCs is shown.

[0027] Figure 16 An exemplary decoding of a CA polar code with two separate CRCs is shown.

[0028] Figure 17 An exemplary encoding of a PC polar code is shown.

[0029] Figure 18 An exemplary decoding of PC polar code is shown.

[0030] Figure 19 An exemplary decoding of PC polar code with CA list selection is shown.

[0031] Figure 20 An exemplary block error rate (BLER) comparison between sub-block based puncturing and existing shortening schemes is shown.

[0032] Figure 21 An exemplary sub-block interleaver for polar code rate matching with 8 sub-blocks is shown.

[0033] Figure 22 An exemplary sub-block interleaver for polar code rate matching is shown with 16 sub-blocks.

[0034] Figures 23A-23C An exemplary sub-block interleaver for polar code rate matching is shown with 32 sub-blocks.

[0035] Figure 24 An exemplary 16-quadrature amplitude modulation (QAM) modulation is shown.

[0036] Figure 25 An exemplary 16QAM modulation is shown.

[0037] Figure 26 An exemplary 16QAM modulation with 4 partitions is shown.

[0038] Figure 27 An exemplary Quadrature Phase Shift Keying (QPSK) modulation with 2 segments is shown.

[0039] Figure 28 An exemplary QPSK modulation with 2 partitions is shown.

[0040] Figure 29 An exemplary QPSK modulation with 5 partitions is shown.

[0041] Figure 30 An exemplary channel interleaver is shown.

[0042] Figure 31 An interleaving example is shown.

[0043] Figure 32 An exemplary block interleaver of depth 5 is shown.

[0044] Figure 33An exemplary performance comparison of different interleavers at a tapped delay line (TDL)-A channel model with a delay spread of 100 ns, 1 / 2 code rate, and QPSK modulation is shown.

[0045] Figure 34 An exemplary performance comparison of different interleavers at a TDL-A channel model with a delay spread of 100 ns, a code rate of 1 / 2, and 16QAM modulation is shown.

[0046] Figure 35 An exemplary performance comparison of different interleavers at a TDL-A channel model with a delay spread of 100 ns, a code rate of 1 / 2, and 16QAM modulation is shown.

[0047] Figure 36 An example of the performance improvement that can be observed using a column-wise interleaver is shown.

[0048] Figures 37-48 Shown are exemplary performance comparisons of various exemplary methods and schemes disclosed herein.

[0049] Figure 49 An exemplary triangular interleaver is shown.

[0050] Figure 50 An exemplary triangular interleaver is shown.

[0051] Figure 51 An exemplary polar coding system is shown. DETAILED DESCRIPTION

[0052] Now will be described with reference to the different drawings about the specific embodiment of illustrative examples.While this description provides detailed examples about possible implementations, it should be noted that these details are intended as examples and in no way limit the scope of the present application.

[0053] Figure 1A1 is a diagram illustrating an exemplary communication system 100 in which one or more disclosed embodiments may be implemented. The communication system 100 may be a multiple access system that provides content such as voice, data, video, messaging, broadcast, etc. to multiple wireless users. The communication system 100 may enable multiple wireless users to access such content by sharing system resources, including wireless bandwidth. For example, the communication system 100 may utilize one or more channel access methods, such as code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), orthogonal FDMA (OFDMA), single carrier FDMA (SC-FDMA), zero-tailing unique word DFT-spread OFDM (ZT UW DTS-s OFDM), unique word OFDM (UW-OFDM), resource block filtered OFDM, and filter bank multi-carrier (FBMC).

[0054] like Figure 1A As shown, the communication system 100 may include wireless transmit / receive units (WTRUs) 102a, 102b, 102c, 102d, RAN 104 / 113, CN 106 / 115, public switched telephone network (PSTN) 108, the Internet 110, and other networks 112. However, it will be appreciated that the disclosed embodiments contemplate any number of WTRUs, base stations, networks, and / or network components. Each of the WTRUs 102a, 102b, 102c, 102d may be any type of device configured to operate and / or communicate in a wireless environment. For example, any of the WTRUs 102a, 102b, 102c, 102d may be referred to as a “station” and / or “STA,” which may be configured to transmit and / or receive wireless signals and may include a user equipment (UE), a mobile station, a fixed or mobile subscriber unit, a subscription-based unit, a pager, a cellular phone, a personal digital assistant (PDA), a smartphone, a laptop, a netbook, a personal computer, a wireless sensor, a hotspot or Mi-Fi device, an Internet of Things (IoT) device, a watch or other wearable device, a head-mounted display (HMD), a vehicle, a drone, medical devices and applications (e.g., telesurgery), industrial devices and applications (e.g., robots and / or other wireless devices operating in industrial and / or automated process chain environments), consumer electronic devices, and devices operating on commercial and / or industrial wireless networks, etc. Any of the WTRUs 102a, 102b, 102c, 102d may be interchangeably referred to as a UE.

[0055] The communication system 100 may also include a base station 114a and / or a base station 114b. Each base station 114a, 114b may be any type of device configured to facilitate access to one or more communication networks (e.g., CN 106 / 115, Internet 110, and / or other networks 112) by wirelessly interfacing with at least one of the WTRUs 102a, 102b, 102c, 102d. For example, the base stations 114a, 114b may be base transceiver stations (BTSs), Node-Bs, eNode-Bs, Home Node-Bs, Home eNode-Bs, gNBs, NR Node-Bs, site controllers, access points (APs), wireless routers, and the like. While each base station 114a, 114b is depicted as a single component, it should be appreciated that the base stations 114a, 114b may include any number of interconnected base stations and / or network components.

[0056] Base station 114a may be part of RAN 104 / 113, which may also include other base stations and / or network components (not shown), such as base station controllers (BSCs), radio network controllers (RNCs), relay nodes, and the like. Base station 114a and / or base station 114b may be configured to transmit and / or receive wireless signals on one or more carrier frequencies, referred to as cells (not shown). These frequencies may be in licensed spectrum, unlicensed spectrum, or a combination of both. A cell may provide wireless service coverage for a specific geographic area that may be relatively fixed or potentially change over time. A cell may be further divided into cell sectors. For example, the cell associated with base station 114a may be divided into three sectors. Thus, in one embodiment, base station 114a may include three transceivers, one for each sector of the cell. In one embodiment, base station 114a may employ multiple-input, multiple-output (MIMO) technology and may use multiple transceivers for each sector of the cell. For example, by employing beamforming, signals may be transmitted and / or received in a desired spatial direction.

[0057] The base stations 114a, 114b may communicate with one or more of the WTRUs 102a, 102b, 102c, 102d over an air interface 116, which may be any suitable wireless communication link (e.g., radio frequency (RF), microwave, centimeter wave, millimeter wave, infrared (IR), ultraviolet (UV), visible light, etc.). The air interface 116 may be established using any suitable radio access technology (RAT).

[0058] More specifically, as described above, the communication system 100 may be a multiple access system and may utilize one or more channel access schemes, such as CDMA, TDMA, FDMA, OFDMA, and SC-FDMA. For example, the base station 114a in the RAN 104 / 113 and the WTRUs 102a, 102b, 102c may implement a radio technology such as Universal Mobile Telecommunications System (UMTS) Terrestrial Radio Access (UTRA), which may utilize Wideband CDMA (WCDMA) to establish the air interface 115 / 116 / 117. WCDMA may include communication protocols such as High Speed ​​Packet Access (HSPA) and / or Evolved HSPA (HSPA+). HSPA may include High Speed ​​Downlink (DL) Packet Access (HSDPA) and / or High Speed ​​UL Packet Access (HSUPA).

[0059] In one embodiment, the base station 114a and the WTRUs 102a, 102b, 102c may implement a radio technology such as Evolved UMTS Terrestrial Radio Access (E-UTRA), which may use Long Term Evolution (LTE) and / or LTE-Advanced (LTE-A) and / or LTE-Advanced Pro (LTE-APro) to establish the air interface 116.

[0060] In one embodiment, the base station 114a and the WTRUs 102a, 102b, 102c may implement a radio technology such as NR radio access, which may establish the air interface 116 using new radio (NR).

[0061] In one embodiment, the base station 114a and the WTRUs 102a, 102b, 102c may implement multiple radio access technologies. For example, the base station 114a and the WTRUs 102a, 102b, 102c may jointly implement LTE radio access and NR radio access (e.g., using dual connectivity (DC) principles). Thus, the air interface used by the WTRUs 102a, 102b, 102c may be characterized by multiple types of radio access technologies and / or transmissions sent to / from multiple types of base stations (e.g., eNBs and gNBs).

[0062] In other embodiments, the base station 114a and the WTRUs 102a, 102b, 102c may implement radio technologies such as IEEE 802.11 (i.e., Wireless Fidelity (WiFi)), IEEE 802.16 (i.e., Worldwide Interoperability for Microwave Access (WiMAX)), CDMA2000, CDMA2000 1X, CDMA2000 EV-DO, Interim Standard 2000 (IS-2000), Interim Standard 95 (IS-95), Interim Standard 856 (IS-856), Global System for Mobile communications (GSM), Enhanced Data Rates for GSM Evolution (EDGE), and GSM EDGE (GERAN), among others.

[0063] Figure 1A The base station 114b in the may be a wireless router, a Home NodeB, a Home eNodeB, or an access point, and may utilize any appropriate RAT to facilitate wireless connectivity in a local area, such as a business location, a residence, a vehicle, a campus, an industrial facility, an air corridor (e.g., for use by drones), a road, and the like. In one embodiment, the base station 114b and the WTRUs 102c, 102d may establish a wireless local area network (WLAN) by implementing a radio technology such as IEEE 802.11. In one embodiment, the base station 114b and the WTRUs 102c, 102d may establish a wireless personal area network (WPAN) by implementing a radio technology such as IEEE 802.15. In yet another embodiment, the base station 114b and the WTRUs 102c, 102d may establish a picocell or a femtocell by utilizing a cellular-based RAT (e.g., WCDMA, CDMA2000, GSM, LTE, LTE-A, LTE-APro, NR, and the like). As Figure 1A As shown, base station 114b may be directly connected to Internet 110. Thus, base station 114b does not necessarily need to access Internet 110 via CN 106 / 115.

[0064] The RAN 104 / 113 may be in communication with the CN 106 / 115, which may be any type of network configured to provide voice, data, applications, and / or Voice over Internet Protocol (VoIP) services to one or more WTRUs 102a, 102b, 102c, 102d. The data may have different quality of service (QoS) requirements, such as different throughput requirements, latency requirements, fault tolerance requirements, reliability requirements, data throughput requirements, mobility requirements, etc. The CN 106 / 115 may provide call control, billing services, mobile location-based services, prepaid calling, Internet connectivity, video distribution, etc., and / or may perform advanced security functions such as user authentication. Although in Figure 1AAlthough not shown, it will be appreciated that the RAN 104 / 113 and / or the CN 106 / 115 may be in direct or indirect communication with other RANs that employ the same RAT or a different RAT as the RAN 104 / 113. For example, in addition to being connected to the RAN 104 / 113 employing NR radio technology, the CN 106 / 115 may also be in communication with another RAN (not shown) employing GSM, UMTS, CDMA 2000, WiMAX, E-UTRA, or WiFi radio technology.

[0065] The CN 106 / 115 may also serve as a gateway for the WTRUs 102a, 102b, 102c, 102d to access the PSTN 108, the Internet 110, and / or other networks 112. The PSTN 108 may include a circuit-switched telephone network that provides plain old telephone service (POTS). The Internet 110 may include a global system of interconnected computer networks and devices that use common communication protocols, such as the Transmission Control Protocol (TCP), User Datagram Protocol (UDP), and / or Internet Protocol (IP) from the TCP / IP suite of internet protocols. The networks 112 may include wired and / or wireless communication networks owned and / or operated by other service providers. For example, the networks 112 may include another CN connected to one or more RANs, which may use the same RAT as the RAN 104 / 113 or a different RAT.

[0066] Some or all of the WTRUs 102a, 102b, 102c, 102d in the communication system 100 may include multi-mode capabilities (e.g., the WTRUs 102a, 102b, 102c, 102d may include multiple transceivers for communicating with different wireless networks over different wireless links). Figure 1A The WTRU 102c shown may be configured to communicate with the base station 114a, which may employ a cellular-based radio technology, and with the base station 114b, which may employ an IEEE 802 radio technology.

[0067] Figure 1B is a system diagram illustrating an example WTRU 102. Figure 1B As shown, the WTRU 102 may include a processor 118, a transceiver 120, a transmit / receive element 122, a speaker / microphone 124, a keypad 126, a display / touchpad 128, non-removable memory 130, removable memory 132, a power supply 134, a global positioning system (GPS) chipset 136, and / or other peripherals 138. It will be appreciated that the WTRU 102 may include any sub-combination of the foregoing components while remaining consistent with an embodiment.

[0068] The processor 118 may be a general purpose processor, a special purpose processor, a conventional processor, a digital signal processor (DSP), a plurality of microprocessors, one or more microprocessors associated with a DSP core, a controller, a microcontroller, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) circuit, any other type of integrated circuit (IC), a state machine, and the like. The processor 118 may perform signal coding, data processing, power control, input / output processing, and / or any other functionality that enables the WTRU 102 to operate in a wireless environment. The processor 118 may be coupled to the transceiver 120, which may be coupled to the transmit / receive element 122. Although Figure 1B The processor 118 and the transceiver 120 are depicted as separate components, however, it should be understood that the processor 118 and the transceiver 120 may be integrated into a single electronic component or chip.

[0069] The transmit / receive element 122 may be configured to transmit or receive signals to or from a base station (e.g., base station 114a) via the air interface 116. For example, in one embodiment, the transmit / receive element 122 may be an antenna configured to transmit and / or receive RF signals. As another example, in another embodiment, the transmit / receive element 122 may be an emitter / detector configured to transmit and / or receive IR, UV, or visible light signals. In yet another embodiment, the transmit / receive element 122 may be configured to transmit and receive RF and light signals. It should be appreciated that the transmit / receive element 122 may be configured to transmit and / or receive any combination of wireless signals.

[0070] Although Figure 1B 102 as a single component, the WTRU 102 may include any number of transmit / receive components 122. More specifically, the WTRU 102 may employ MIMO technology. Thus, in one embodiment, the WTRU 102 may include two or more transmit / receive components 122 (e.g., multiple antennas) for transmitting and receiving radio signals over the air interface 116.

[0071] The transceiver 120 may be configured to modulate signals to be transmitted by the transmit / receive element 122 and to demodulate signals received by the transmit / receive element 122. As described above, the WTRU 102 may have multi-mode capabilities. Thus, the transceiver 120 may include multiple transceivers that allow the WTRU 102 to communicate via multiple RATs, such as NR and IEEE 802.11.

[0072] The processor 118 of the WTRU 102 may be coupled to a speaker / microphone 124, a keypad 126, and / or a display / touchpad 128 (e.g., a liquid crystal display (LCD) display unit or an organic light emitting diode (OLED) display unit) and may receive user input data from these components. The processor 118 may also output user data to the speaker / microphone 124, the keypad 126, and / or the display / touchpad 128. In addition, the processor 118 may access information from, and store data in, any suitable memory, such as non-removable memory 130 and / or removable memory 132. The non-removable memory 130 may include random access memory (RAM), read-only memory (ROM), a hard disk, or any other type of memory storage device. The removable memory 132 may include a subscriber identity module (SIM) card, a memory stick, a secure digital (SD) memory card, and the like. In other embodiments, the processor 118 may access information from, and store data in, memory that is not physically located on the WTRU 102, such as on a server or a home computer (not shown).

[0073] The processor 118 may receive power from the power source 134 and may be configured to distribute and / or control power to the other components in the WTRU 102. The power source 134 may be any suitable device for powering the WTRU 102. For example, the power source 134 may include one or more dry cell batteries (e.g., nickel-cadmium (Ni-Cd), nickel-zinc (Ni-Zn), nickel-metal hydride (NiMH), lithium-ion (Li-ion), etc.), solar cells, fuel cells, and the like.

[0074] The processor 118 may also be coupled to the GPS chipset 136, which may be configured to provide location information (e.g., longitude and latitude) regarding the current location of the WTRU 102. In addition to or in lieu of the information from the GPS chipset 136, the WTRU 102 may receive location information from a base station (e.g., base stations 114a, 114b) via the air interface 116 and / or determine its location based on the timing of signals received from two or more nearby base stations. It will be appreciated that the WTRU 102 may acquire location information using any suitable positioning method while remaining consistent with the embodiments.

[0075] The processor 118 may also be coupled to other peripherals 138, which may include one or more software and / or hardware modules that provide additional features, functionality, and / or wired or wireless connectivity. For example, the peripherals 138 may include an accelerometer, an electronic compass, a satellite transceiver, a digital camera (for photos and / or video), a universal serial bus (USB) port, a vibration device, a television transceiver, a hands-free headset, module, a frequency modulation (FM) radio unit, a digital music player, a media player, a video game console module, an Internet browser, a virtual reality and / or augmented reality (VR / AR) device, and an activity tracker, etc. The peripheral device 138 may include one or more sensors, which may be one or more of the following: a gyroscope, an accelerometer, a Hall effect sensor, a magnetometer, an orientation sensor, a proximity sensor, a temperature sensor, a time sensor, a geo-location sensor, an altimeter, a light sensor, a touch sensor, a magnetometer, a barometer, a gesture sensor, a biometric sensor, and / or a humidity sensor.

[0076] The WTRU 102 may include a full-duplex radio in which the reception and transmission of some or all signals (e.g., associated with subframes used for UL (e.g., for transmission) and downlink (e.g., for reception)) may be concurrent and / or simultaneous for the radio. The full-duplex radio may include an interference management unit that reduces and / or substantially eliminates self-interference by means of hardware (e.g., chokes) or by signal processing by a processor (e.g., a separate processor (not shown) or by the processor 118). In one embodiment, the WTRU 102 may include a half-duplex radio in which the transmission and reception of some or all signals (e.g., associated with specific subframes used for UL (e.g., for transmission) and downlink (e.g., for reception)) may be concurrent and / or simultaneous for the radio.

[0077] Figure 1C 1 is a system diagram illustrating the RAN 104 and the CN 106 according to one embodiment. As described above, the RAN 104 may employ an E-UTRA radio technology to communicate with the WTRUs 102a, 102b, 102c over the air interface 116. The RAN 104 may also be in communication with the CN 106.

[0078] The RAN 104 may include eNode-Bs 160a, 160b, 160c, however, it will be appreciated that the RAN 104 may include any number of eNode-Bs while remaining consistent with an embodiment. Each of the eNode-Bs 160a, 160b, 160c may include one or more transceivers for communicating with the WTRUs 102a, 102b, 102c over the air interface 116. In one embodiment, the eNode-Bs 160a, 160b, 160c may implement MIMO technology. Thus, for example, the eNode-B 160a may use multiple antennas to transmit wireless signals to, and / or receive wireless signals from, the WTRU 102a.

[0079] Each eNodeB 160a, 160b, 160c may be associated with a particular cell (not shown) and may be configured to handle radio resource management decisions, handover decisions, user scheduling in UL and / or DL, etc. Figure 1C As shown, the eNode-Bs 160a, 160b, and 160c may communicate with each other via an X2 interface.

[0080] Figure 1C The illustrated CN 106 may include a mobility management entity (MME) 162, a serving gateway (SGW) 164, and a packet data network (PDN) gateway (or PGW) 166. While each of the aforementioned components is depicted as being part of the CN 106, it should be understood that any of these components may be owned and / or operated by an entity other than the CN operator.

[0081] The MME 162 may be connected to each of the eNode-Bs 160a, 160b, 160c in the RAN 104 via an S1 interface and may serve as a control node. For example, the MME 162 may be responsible for authenticating users of the WTRUs 102a, 102b, 102c, bearer activation / deactivation, and selecting a particular serving gateway during an initial attach of the WTRUs 102a, 102b, 102c. The MME 162 may also provide a control plane function for switching between the RAN 104 and other RANs (not shown) employing other radio technologies, such as GSM and / or WCDMA.

[0082] The SGW 164 may be connected to each of the eNode-Bs 160a, 160b, 160c in the RAN 104 via an S1 interface. The SGW 164 may generally route and forward user data packets to and from the WTRUs 102a, 102b, 102c. The SGW 164 may also perform other functions, such as anchoring the user plane during inter-eNB handovers, triggering paging when downlink data is available for the WTRUs 102a, 102b, 102c, and managing and storing the context of the WTRUs 102a, 102b, 102c.

[0083] The SGW 164 may be connected to the PGW 166, which may provide the WTRUs 102a, 102b, 102c with access to packet-switched networks, such as the Internet 110, to facilitate communications between the WTRUs 102a, 102b, 102c and IP-enabled devices.

[0084] The CN 106 may facilitate communications with other networks. For example, the CN 106 may provide the WTRUs 102a, 102b, 102c with access to circuit-switched networks, such as the PSTN 108, to facilitate communications between the WTRUs 102a, 102b, 102c and traditional land-line communications devices. For example, the CN 106 may include or communicate with an IP gateway, such as an IP Multimedia Subsystem (IMS) server, which may serve as an interface between the CN 106 and the PSTN 108. The CN 106 may also provide the WTRUs 102a, 102b, 102c with access to other networks 112, which may include other wired and / or wireless networks owned and / or operated by other service providers.

[0085] Although Figures 1A-1D While the WTRU is described as a wireless terminal, it is appreciated that in certain exemplary embodiments, such a terminal may utilize a (eg, temporary or permanent) wired communication interface with a communication network.

[0086] In a typical embodiment, the other network 112 may be a WLAN.

[0087] A WLAN using an infrastructure basic service set (BSS) model may have an access point (AP) for the BSS and one or more stations (STAs) associated with the AP. The AP may access or interface with a distributed system (DS) or other type of wired / wireless network that routes traffic into and / or out of the BSS. Traffic originating from outside the BSS and destined for a STA may be routed through the AP and delivered to the STA. Traffic originating from a STA and destined for a destination outside the BSS may be sent to the AP for delivery to the destination. Traffic between STAs within the BSS may be routed through the AP, for example, where a source STA may send traffic to the AP, and the AP may deliver the traffic to the destination STA. Traffic between STAs within the BSS may be considered and / or referred to as point-to-point traffic. This point-to-point traffic may be routed between (e.g., directly between) the source and destination STAs using a direct link setup (DLS). In certain exemplary embodiments, the DLS may utilize 802.11e DLS or 802.11z tunneled DLS (TDLS). A WLAN using an independent BSS (IBSS) mode does not have an AP, and STAs (eg, all STAs) within or using the IBSS can communicate directly with each other. The IBSS communication mode may sometimes be referred to as an "ad hoc" communication mode.

[0088] When using 802.11ac infrastructure mode or a similar mode of operation, the AP may transmit beacons on a fixed channel (e.g., a primary channel). The primary channel may have a fixed width (e.g., a 20 MHz bandwidth) or a width that is dynamically set via signaling. The primary channel may be the operating channel of the BSS and may be used by STAs to establish a connection with the AP. In certain typical embodiments, carrier sense multiple access with collision avoidance (CSMA / CA) (e.g., in an 802.11 system) may be implemented. For CSMA / CA, STAs (e.g., each STA), including the AP, may sense the primary channel. If a particular STA senses / detects and / or determines that the primary channel is busy, the particular STA may back off. In a given BSS, one STA (e.g., only one station) may transmit at any given time.

[0089] High throughput (HT) STAs may communicate using a 40 MHz wide channel (eg, by combining a 20 MHz wide primary channel with adjacent or non-adjacent 20 MHz wide channels to form a 40 MHz wide channel).

[0090] Very High Throughput (VHT) STAs can support channels with widths of 20 MHz, 40 MHz, 80 MHz, and / or 160 MHz. 40 MHz and / or 80 MHz channels can be formed by combining contiguous 20 MHz channels. A 160 MHz channel can be formed by combining eight contiguous 20 MHz channels or by combining two discontinuous 80 MHz channels (this combination may be referred to as an 80+80 configuration). For the 80+80 configuration, after channel coding, the data can be passed through a segment parser that separates the data into two streams. Inverse Fast Fourier Transform (IFFT) processing and time domain processing can be performed separately on each stream. The streams can be mapped onto two 80 MHz channels, and the data can be transmitted by the transmitting STA. At the receiver of the receiving STA, the above operations for the 80+80 configuration can be reversed, and the combined data can be sent to the medium access control (MAC).

[0091] 802.11af and 802.11ah support sub-1 GHz operating modes. Compared to 802.11n and 802.11ac, the channel operating bandwidth and carriers used in 802.11af and 802.11ah are reduced. 802.11af supports 5 MHz, 10 MHz, and 20 MHz bandwidths in the TV White Space (TVWS) spectrum, and 802.11ah supports 1 MHz, 2 MHz, 4 MHz, 8 MHz, and 16 MHz bandwidths using non-TVWS spectrum. According to typical embodiments, 802.11ah may support meter type control / machine type communication (e.g., MTC devices in macro coverage areas). MTC may have certain capabilities, such as limited capabilities including support for (e.g., only support for) certain and / or limited bandwidths. The MTC device may include a battery, and the battery life of the battery is above a threshold (e.g., maintaining a very long battery life).

[0092] For WLAN systems that support multiple channels and channel bandwidths (e.g., 802.11n, 802.11ac, 802.11af, and 802.11ah), the WLAN system includes a channel that can be designated as the primary channel. The bandwidth of the primary channel can be equal to the maximum common operating bandwidth supported by all STAs in the BSS. The bandwidth of the primary channel can be set and / or limited by a STA, where the STA is derived from all STAs operating in the BSS that supports the minimum bandwidth operating mode. In the example of 802.11ah, even if the AP and other STAs in the BSS support 2 MHz, 4 MHz, 8 MHz, 16 MHz, and / or other channel bandwidth operating modes, for STAs that support (e.g., only) 1 MHz mode (e.g., MTC-type devices), the primary channel width can be 1 MHz. Carrier sensing and / or network allocation vector (NAV) settings can depend on the status of the primary channel. If the primary channel is busy (e.g., because a STA (that only supports 1 MHz operating mode) is transmitting to the AP), the entire available frequency band can be considered busy, even if most of the frequency band remains idle and available for use.

[0093] In the United States, the available frequency band for 802.11ah is 902MHz to 928MHz. In South Korea, the available frequency band is 917.5MHz to 923.5MHz. In Japan, the available frequency band is 916.5MHz to 927.5MHz. Depending on the country code, the total bandwidth available for 802.11ah ranges from 6MHz to 26MHz.

[0094] Figure 1D 1 is a system diagram illustrating the RAN 113 and the CN 115 according to one embodiment. As described above, the RAN 113 may communicate with the WTRUs 102a, 102b, 102c using NR radio technology over the air interface 116. In addition, the RAN 113 may also communicate with the CN 115.

[0095] The RAN 113 may include gNBs 180a, 180b, and 180c, though it will be appreciated that the RAN 113 may include any number of gNBs while remaining consistent with an embodiment. Each gNB 180a, 180b, and 180c may include one or more transceivers for communicating with the WTRUs 102a, 102b, and 102c over the air interface 116. In one embodiment, the gNBs 180a, 180b, and 180c may implement MIMO technology. For example, the gNBs 180a and 180b may employ beamforming to transmit and / or receive signals to and / or from the gNBs 180a, 180b, and 180c. Thus, for example, the gNB 180a may use multiple antennas to transmit wireless signals to and / or receive wireless signals from the WTRU 102a. In one embodiment, the gNBs 180a, 180b, and 180c may implement carrier aggregation. For example, gNB 180a may transmit multiple component carriers to WTRU 102a (not shown). A subset of these component carriers may be in unlicensed spectrum, while the remaining component carriers may be in licensed spectrum. In one embodiment, gNBs 180a, 180b, and 180c may implement coordinated multi-point (CoMP) technology. For example, WTRU 102a may receive coordinated transmissions from gNB 180a and gNB 180b (and / or gNB 180c).

[0096] The WTRUs 102a, 102b, 102c may communicate with the gNBs 180a, 180b, 180c using transmissions associated with the scalable parameter configurations. For example, the OFDM symbol spacing and / or OFDM subcarrier spacing may be different for different transmissions, different cells, and / or different portions of the radio transmission spectrum. The WTRUs 102a, 102b, 102c may communicate with the gNBs 180a, 180b, 180c using subframes or transmission time intervals (TTIs) of different or scalable lengths (e.g., containing different numbers of OFDM symbols and / or lasting different absolute time lengths).

[0097] The gNBs 180a, 180b, 180c may be configured to communicate with the WTRUs 102a, 102b, 102c in a standalone configuration and / or a non-standalone configuration. In a standalone configuration, the WTRUs 102a, 102b, 102c may communicate with the gNBs 180a, 180b, 180c without accessing other RANs (e.g., the eNode-Bs 160a, 160b, 160c). In a standalone configuration, the WTRUs 102a, 102b, 102c may use one or more of the gNBs 180a, 180b, 180c as mobility anchors. In a standalone configuration, the WTRUs 102a, 102b, 102c may communicate with the gNBs 180a, 180b, 180c using signals in an unlicensed band. In a non-standalone configuration, the WTRUs 102a, 102b, 102c may communicate / connect with the gNBs 180a, 180b, 180c while communicating / connecting with another RAN (e.g., the eNode-Bs 160a, 160b, 160c). For example, the WTRUs 102a, 102b, 102c may communicate with one or more gNBs 180a, 180b, 180c and one or more eNode-Bs 160a, 160b, 160c substantially simultaneously by implementing the DC principle. In a non-standalone configuration, the eNode-Bs 160a, 160b, 160c may serve as mobility anchors for the WTRUs 102a, 102b, 102c, and the gNBs 180a, 180b, 180c may provide additional coverage and / or throughput to serve the WTRUs 102a, 102b, 102c.

[0098] Each gNB 180a, 180b, 180c may be associated with a specific cell (not shown) and may be configured to handle radio resource management decisions, handover decisions, user scheduling in UL and / or DL, support network slicing, implement dual connectivity, implement interworking between NR and E-UTRA, route user plane data to user plane functions (UPFs) 184a, 184b, and route control plane information to access and mobility management functions (AMFs) 182a, 182b, etc. Figure 1D As shown, gNBs 180a, 180b, and 180c can communicate with each other via the Xn interface.

[0099] Figure 1DThe CN 115 shown may include at least one AMF 182a, 182b, at least one UPF 184a, 184b, at least one Session Management Function (SMF) 183a, 183b, and may include Data Networks (DNs) 185a, 185b. Although each of the aforementioned components is depicted as part of the CN 115, it should be understood that any of these components may be owned and / or operated by entities other than the CN operator.

[0100] The AMF 182a, 182b may be connected to one or more gNBs 180a, 180b, 180c in the RAN 113 via the N2 interface and may act as a control node. For example, the AMF 182a, 182b may be responsible for authenticating users of the WTRUs 102a, 102b, 102c, supporting network slicing (e.g., handling different PDU sessions with different requirements), selecting a specific SMF 183a, 183b, managing registration areas, terminating NAS signaling, and mobility management, among other things. The AMF 182a, 1823b may use network slicing processing to customize the CN support provided to the WTRUs 102a, 102b, 102c based on the type of service used by the WTRUs 102a, 102b, 102c. As an example, different network slices may be established for different use cases, such as services relying on ultra-reliable low-latency (URLLC) access, services relying on enhanced massive mobile broadband (eMBB) access, and / or services for machine-type communication (MTC) access, etc. The AMF 162 may provide a control plane function for switching between the RAN 113 and other RANs (not shown) that use other radio technologies, such as non-3GPP access technologies such as LTE, LTE-A, LTE-A Pro, and / or WiFi.

[0101] The SMFs 183a and 183b can connect to the AMFs 182a and 182b in the CN 115 via the N11 interface. The SMFs 183a and 183b can also connect to the UPFs 184a and 184b in the CN 115 via the N4 interface. The SMFs 183a and 183b can select and control the UPFs 184a and 184b and can configure traffic routing through the UPFs 184a and 184b. The SMFs 183a and 183b can perform other functions, such as managing and allocating UE IP addresses, managing PDU sessions, controlling policy enforcement and QoS, providing downlink data notifications, and the like. The PDU session type can be IP-based, non-IP-based, Ethernet-based, and the like.

[0102] The UPF 184a, 184b may be connected to one or more gNBs 180a, 180b, 180c in the RAN 113 via the N3 interface. This may provide the WTRUs 102a, 102b, 102c with access to packet-switched networks, such as the Internet 110, to facilitate communications between the WTRUs 102a, 102b, 102c and IP-enabled devices. The UPF 184, 184b may perform other functions, such as routing and forwarding packets, enforcing user plane policies, supporting multi-homed PDU sessions, handling user plane QoS, buffering downlink packets, and providing mobility anchoring handling, among others.

[0103] The CN 115 may facilitate communications with other networks. For example, the CN 115 may include or may communicate with an IP gateway (e.g., an IP Multimedia Subsystem (IMS) server) that acts as an interface between the CN 115 and the PSTN 108. Furthermore, the CN 115 may provide the WTRUs 102a, 102b, 102c with access to other networks 112, which may include other wired and / or wireless networks owned and / or operated by other service providers. In one embodiment, the WTRUs 102a, 102b, 102c may be connected to the local data network (DN) 185a, 185b through the UPFs 184a, 184b via the N3 interface to the UPFs 184a, 184b and the N6 interface between the UPFs 184a, 184b and the DNs 185a, 185b.

[0104] In view of Figures 1A-1D and about Figures 1A-1D

[0045] As described herein, one or more or all of the functions described herein with respect to one or more of the following may be performed by one or more emulated devices (not shown): WTRUs 102a-d, base stations 114a-b, eNodeBs 160a-c, MMEs 162, SGWs 164, PGWs 166, gNBs 180a-c, AMFs 182a-b, UPFs 184a-b, SMFs 183a-b, DNs 185a-b, and / or any other device or devices described herein. These emulated devices may be one or more devices configured to emulate one or more or all of the functions described herein. For example, these emulated devices may be used to test other devices and / or emulate network and / or WTRU functions.

[0105] The simulation device can be designed to perform one or more tests on other devices in a laboratory environment and / or an operator network environment. For example, the one or more simulation devices can perform one or more or all functions while being implemented and / or deployed in whole or in part as part of a wired and / or wireless communication network to test other devices within the communication network. The one or more simulation devices can perform one or more or all functions while being temporarily implemented / deployed as part of a wired and / or wireless communication network. The simulation device can be directly coupled to other devices to perform the tests, and / or can use over-the-air wireless communications to perform the tests.

[0106] One or more emulation devices can perform one or more functions, including all functions, while not being implemented / deployed as part of a wired and / or wireless communication network. For example, the emulation device can be used in a test lab and / or a test scenario of a wired and / or wireless communication network that has not been deployed (e.g., tested) to perform tests on one or more components. The one or more emulation devices can be test devices. The emulation device can transmit and / or receive data using direct RF coupling and / or wireless communication with the aid of RF circuitry (which can, for example, include one or more antennas).

[0107] One or more of the features disclosed herein may be implemented using Figures 1A-1D The present invention is implemented in one or more of the devices, methods and / or systems described herein.

[0108] Capacity-achieving codes other than turbo codes and / or low-density parity-check (LDPC) codes may include polar codes. Polar codes may be linear block codes having characteristics including one or more of the following: low encoding and / or decoding complexity, a low error floor (e.g., a very low error floor), or an explicit construction scheme.

[0109] The polar code (N, K) may be based on the information block length K and the coding block length N. The value N may be set to a power of 2, for example, N=2 n , n is an integer. The polar code generator matrix can be expressed as Among them B N is the bit-reversal permutation matrix, represents the nth Kronecker power, and In the exemplary implementation of the polar code, for simplicity, the bit reversal permutation matrix B N It can be ignored on the encoder side and a bit-reversal operation can be performed on the decoder side. Figure 2 An example of a polar encoder with N=8. Figure 2 Shown The codeword of the polar code can be represented by given.

[0110] Regarding decoding of polarity coded bits, Successive Cancellation (SC) decoding can be used. Advanced decoding schemes can also be used based on SC decoding, such as Successive Cancellation List (SCL) decoding or CRC Assisted SCL (CA-SCL) decoding.

[0111] CRC-assisted (CA) polar codes can be polar codes that utilize a CRC-assisted Successive Cancellation List (SCL) decoder. In CRC-assisted decoding, CRC bits can be used to select a final codeword from a list of candidate codewords. This final codeword can be selected at the decoding end. The CRC bits can be designed and used for error correction purposes, rather than, for example, error detection purposes. The CRC bits can be used for local error detection.

[0112] The polar code may be constructed according to the encoding and decoding. The design of the polar code may depend on the K information bits to the polar encoder. The K information bits may be placed on K bit channels, for example, the K best bit channels. The remaining NK input bits that are not mapped to the information bits may be referred to as frozen bits. The frozen bits may have a fixed value, for example, the frozen bits may be set to a value of 0. The set of positions of the frozen bits may be referred to as a frozen set The decision about the best bit channel can vary and depend on the channel conditions. In determining the frozen channel set, the bit channels can be ranked based on their reliability. Reliable bit channels can be classified as good bit channels, while bit channels with poor reliability can be classified as bad bit channels.

[0113] The reliability of the bit channel can be calculated. For example, the reliability of the bit channel can be calculated using one or more of the following: Bhattacharyya jitter, Monte-Carlo estimation, full transition probability matrix estimation, or Gaussian approximation. These schemes can have different computational complexities and can be applied to different channel conditions. A parameter design signal-to-noise ratio (SNR) can be selected. For example, a design SNR can be selected before performing the reliability calculation.

[0114] The ranking of the bit channels can be calculated. The ranking of the bit channels can be calculated without using the design SNR parameters. For example, the ranking sequence can be generated from a formula or expanded from a small sequence. Once the ranking of the bit channels is determined, the information bits can be mapped to the bit channels with high reliability. The frozen bits can be mapped to the bit channels with lower reliability, such as Figure 3shown.

[0115] Figure 4 An exemplary parity check (PC) polarity encoding is shown. The difference between PC polarity codes and non-PC polarity codes can be that a subset of frozen subchannels is selected as PC frozen subchannels. A PC function can be established for error correction on the subchannels. In one example (e.g., at each parity subchannel location), each decoded bit involved in the PC function on the PC frozen subchannel can help prune the list decoding tree. In one example, paths that satisfy the PC function can be left; the remaining paths are eliminated on the fly. For example, a forward-only PC function can be established to be consistent with a decoder based on continuous elimination. Figure 4 An example of mapping information bits to the input of a PC polar code is shown.

[0116] The introduction of PC polar codes allows the removal of the CRC bits of the CA polar codes. The PC polar codes can be used for error correction purposes during CRC-assisted consecutive cancellation list (SCL) decoding. This reduces the overhead of the polar codes and can result in higher coding gain.

[0117] Polar codes may be used as channel codes for uplink (UL) and / or downlink (DL) control information. The CRC bits may be used for control messages to reduce the false alarm rate. The polar codes for the physical channel may support one of: CRC+basic polarity code, or J-bit error detection CRC+concatenated polarity code. The CRC+basic polarity code (e.g., CA polarity) may be used in conjunction with a longer CRC (e.g., (J+J')-bit CRC and / or a distributed CRC (e.g., J-bit CRC). The concatenated polarity code may be one or more of: J'-bit CRC+basic polarity, J'-bit distributed CRC+basic polarity, PC polarity, or hash sequence PC polarity. A coding scheme that can achieve the advantages of both mechanisms may be implemented.

[0118] Polar coding designs for control and / or data information can be provided. Unlike tail-biting convolutional codes (TBCC), polar codes (which may be block codes) can have different block lengths. Rate matching can be designed for polar codes to improve performance. Rate matching selection can be performed using one or more of the following: a repetition mechanism, a puncturing mechanism, and / or a shortening mechanism. The rate matching mechanism can be selected based on one or more parameters described herein.

[0119] Polar code design may include code construction selection (eg, CRC-assisted (CA) polar coding or parity check (PC) polar coding) and / or code sequence selection. A flexible polar coding scheme capable of supporting multiple polar codes may be provided.

[0120] Polar coding for control channels may be provided. Figure 5 Example processing of control information (eg, downlink control information (DCI) or uplink control information (UCI)) using polar codes is shown. The control blocks within the polar coding subsystem may include a code selection control block and a rate matching control block.

[0121] The code selection control block may determine the type of polarity code to be used. The code selection control block may determine the associated CRC length. Example polarity code types may include the polarity code types described herein and / or other variants, such as advanced PC polarity codes with CA list selection. The determination of the polarity code type may be based on one or more of the following: WTRU category, WTRU capabilities, or configuration. In an example, the WTRU category may correspond to a polarity code. In an example, the polarity code type may be configured via a radio resource control (RRC) connection establishment message or an RRC connection reconfiguration message. In an example, the polarity code type may be predefined. The corresponding CRC length may be determined. For example, the CRC length may be determined based on the determined polarity code type. For example, if the list length is 8, a 16-bit CRC may be used for PC polarity codes; for CA polarity codes with a long CRC, a 19-bit CRC may be used, for example. The code selection control block may send CRC length information to the CRC attachment block. The CRC attachment block may pass the polarity code type to the channel coding block.

[0122] Figure 5 The rate matching control block of may perform one or more of the following: calculate the expected codeword length (eg, the length of the coded bits for transmission), i.e. bits; calculate the mother code length N (e.g., after calculating the expected codeword length); determine the rate matching scheme(s) to be used; or determine the detailed rate matching scheme(s). The rate matching control block may perform the calculation or make the determination based on one or more of the following: uplink control information (UCI) or downlink control information (DCI) block size K, CRC length J, or code rate R.

[0123] In one example, to calculate the mother code length N, the mother code length N may be assumed to be a power of 2 due to the polar code characteristics. The mother code length N may be greater than or less than the expected codeword length. For example, if the expected codeword length is slightly greater than 2 n bits, where n is an integer, the mother code length can be 2 n , instead of 2 n+1 The selection of the mother code length may be based on one or more formulas. In one example,

[0124] if

[0125] if For a certain constant fraction τ, it can be

[0126] In one example,

[0127] if

[0128] if

[0129] For a certain constant integer τ, it can be, for example, 10. Other exemplary formulas can be similar to the above formula, where the value τ can be a function of n. For example, if n≤5, then τ=0; otherwise And if n≤6, then τ=0; otherwise The mother code length formula may or may not depend on the code rate. For different code rates or code rate ranges, the formula and its parameter τ may be different.

[0130] The mother code length can be selected based on one or more lookup tables. Table 1 shows an example of a lookup table (LUT) for selecting the desired codeword length for a corresponding mother code length N. The first row of Table 1 indicates the desired codeword length range, while the second row indicates the corresponding mother code length. For example, if the desired codeword length is 50 bits, which is in the range of [33, 70], the mother code length can be selected as 64 bits. If the desired codeword length is 275 bits, which is in the range of [141, 280], the selected mother code length can be 256 bits. In the exemplary Table 1, the maximum mother code length can be fixed at 1024 bits.

[0131]

[0132] Table 1

[0133] Table 2 shows another example of the LUT, where the maximum mother code length may be 512 bits.

[0134]

[0135] Table 2

[0136] The mother code length can be determined based on the code rate. In one example, when the code rate is very high (e.g., > 1 / 2), the desired codeword length can be very small (or slightly larger) than the length of the information bits. The mother code length can be selected to be relatively large so that the use of this mother code length can contain more information than can be contained within it (e.g., when the code rate is 1 / 2).

[0137] For example, when the mother code length depends on the code rate, the exemplary Tables 1 and 2 may be applicable to certain code rates. For example, if the code rate is greater than a threshold (e.g., 1 / 2), the mother code length N may be a power of 2. This mother code length may be greater than the desired codeword length. If the code rate is less than the threshold, the mother code length N may be determined based on one or more lookup tables (e.g., Table 1 and / or Table 2). The mother code length selection may depend on the modulation order. For example, Tables 1 and 2 may be used for lower-order modulation (e.g., QPSK). A different set of tables may be defined for higher-order modulation (e.g., 64QAM).

[0138] Figure 37 、 Figure 38 、 Figure 39 as well as Figure 40 The results show that 10 is achieved for code rates 1 / 5, 1 / 3, 2 / 5 and 1 / 2 respectively. -3 These exemplary simulation results show that when the code rate may be less than or equal to 2 / 5 and the coding block length may be between 2 n to 2 n (1+1 / 8), a repeat scheme can be selected. For example, if In 2 n to 2 n (1+1 / 8) and the code rate is less than 2 / 5, then the mother code length N can be selected as 2 n , instead of 2 n+1 .

[0139] Additional performance simulations for the split-natural puncturing example, the split-natural shortening example, and the bit-reversal shortening example provide the results disclosed herein. In these simulations, QPSK modulation and an AWGN channel are assumed. In these simulations, polar codes with a PW sequence and a CA-SCL (L=8) decoding algorithm are used. A 19-bit CRC is appended to the source data. The CRC bits can be considered part of the information bits.

[0140] The rate matching control block may determine the rate matching scheme that may be used. The rate matching scheme may include one or more of the following: repetition, shortening, or puncturing. The selection of the rate matching scheme with respect to repetition may depend on the relationship between the mother code length and the expected codeword length. For example, if the mother code length is less than the expected codeword length, the repetition scheme may be selected. Otherwise, the shortening scheme or the puncturing scheme may be selected. The selection between the shortening scheme and the puncturing scheme may depend on at least one of the following: the code rate R, or the mother code rate R. At low code rates or low mother code rates, the puncturing scheme performs well and can be used. At high code rates or high mother code rates, the shortening scheme performs well and can be used. The function f(R m, R). If f(R m , R) < Thr, a puncturing scheme can be selected; otherwise, a shortening scheme can be selected.

[0141] Figure 41 and Figure 42 show the minimum SNR required to achieve the target BLER levels of 10 -2 and 10 -3 respectively for a code rate of 1 / 5. Figure 43 and Figure 44 show the minimum SNR required to achieve the target BLER levels of 10 -2 and 10 -3 respectively for a code rate of 1 / 3. Figure 45 and Figure 46 show the minimum SNR required to achieve the target BLER levels of 10 -2 and 10 -3 respectively for a code rate of 2 / 5. Figure 47 and Figure 48 show the minimum SNR required to achieve the target BLER levels of 10 -2 and 10 -3 respectively for a code rate of 1 / 2.

[0142] Based on these simulation results, the following scheme can be established: When the code rate is greater than 2 / 5, the shortening scheme can be selected. When the code rate is less than or equal to 2 / 5, the puncturing scheme can be selected. In one example, the code rate threshold for selecting the puncturing scheme or the shortening scheme can be 2 / 5.

[0143] Rate matching can be implemented by using concatenated polar codes (e.g., in addition to the repetition, shortening, and / or puncturing schemes). For example, for a desired codeword length of 288 bits, 224 bits can be punctured or shortened from a mother code length of 512 bits. One way can be to repeat 32 bits from a mother code length of 256 bits. Another way can be to split the 288 bits into 256 bits and 32 bits. One polar code can be used with the 256-bit mother code length, and another polar code can be used with the 32-bit mother code length. If the desired codeword length is close to the sum of some numbers that are powers of 2, this scheme can be used. The repetition, shortening, or puncturing scheme can be applied to each component of the concatenated polar codes.

[0144] Figure 6 shows an exemplary rate matching control process. In the process of determining the (multiple) detailed rate matching schemes, one or more of the following can be applied.

[0145] If the repetition scheme is selected as the rate matching scheme, then Figure 5The rate matching control block can select a detailed repetition scheme. The repetition scheme may include one or more of the following: repetition from the top of the circular buffer (e.g., natural repetition), repetition from the bottom of the circular buffer, repetition from the top of the circular buffer with bit reversal, repetition from the bottom of the circular buffer with bit reversal, random picking, uniform / distributed repetition, repetition from the configured starting point in a continuous manner, or repetition from the configured starting point in an interleaved manner. Assume that e0, ..., e N-1 is the polarity coded bit, and N+L is the number of bits transmitted. For repetition from the top of the ring buffer, the transmitted bits can be represented as: e0,…,e N-1 ,e0,…,e L-1 For repetition from the bottom of the ring buffer, the transmitted bits can be expressed as: N-1 ,…,e0,e N-1 ,…,e N-L For repetition from the top of the ring buffer with bit reversal, the transmitted bits can be expressed as: BR(0) ,…,e BR(N-1) ,e BR(0) ,…,e BR(L-1) For repetition from the bottom of the ring buffer with bit reversal, the transmitted bits can be expressed as: BR(N-1) ,…,e BR(0) ,e BR(N-1) ,…,e BR(N-L) The choice of repetition scheme may depend on one or more of the following: the number of repeated bits, the mother code length, or the code rate. Based on the determined repetition scheme, a repetition vector may be calculated. The repetition vector length may be equal to the desired codeword length. Subtract the mother code length N, where each value of the repetition vector can be an index with a value between 1 and N (or between 0 and N-1). Based on the expected codeword length and the mother code length, the rate matching block can determine the N output bits of the polar encoder that can be repeated. For example, for N=256, In the case of , the repetition vector can be (1,2,3,4), which may imply that the first 4 bits of the polar encoder output can be repeated. Figure 6 As shown, the repeat vector can be sent to Figure 5 rate matching box.

[0146] If a puncturing scheme is selected, the rate matching block may select a detailed puncturing scheme. The puncturing scheme may include one or more of the following: puncturing from the top of the circular buffer, puncturing from the bottom of the circular buffer, puncturing from the top of the circular buffer with bit reversal, puncturing from the bottom of the circular buffer with bit reversal, distributed puncturing (e.g., natural decomposition puncturing), puncturing in a continuous manner from a configured starting point, or puncturing in an interleaved manner from a configured starting point. Assume that e0, ..., eN-1 is the polarity coding bit, and L is the number of punctured bits. For puncturing from the top of the ring buffer, the punctured bits can be represented as: e0,…,e L-1 For puncturing from the bottom of the ring buffer, the punctured bits can be expressed as: e N-L ,…,e N-1 For puncturing from the top of the ring buffer with bit reversal, the punctured bits can be expressed as: BR(0) ,…,e BR(L-1) For puncturing from the bottom of the ring buffer with bit reversal, the punctured bits can be expressed as: BR(N-L) ,…,e BR(N-1) The distributed puncturing may start from 0, N / 4 and / or N / 2. The puncturing may be performed sequentially. The selection of the puncturing scheme may depend on one or more of the following: the number of punctured bits, the mother code length, the code rate, etc. Based on the selected puncturing scheme and the number of bits to be punctured, the puncturing vector may be calculated. Figure 6 As shown, the puncturing vector may be sent to a rate matching block.

[0147] When a shortening scheme is selected, the rate matching block may select a detailed shortening scheme. The shortening scheme may include one or more of the following: shortening from the bottom of the circular buffer, shortening from the bottom of the circular buffer with bit reversal (for example, it may be referred to as bit reversal shortening), or natural decomposition shortening. The selection of the shortening scheme may depend on one or more of the following: the number of punctured bits, the mother code length, the code rate, etc. Based on the selected shortening scheme and the number of bits to be shortened, a puncturing vector may be calculated, which may be sent to the rate matching block. A shortening vector corresponding to the puncturing vector may be calculated. For a polar encoder without a bit reversal operation, the shortening vector may be equal to the puncturing vector. For a polar encoder with a bit reversal operation, the shortening vector may be equal to the bit reversal of the puncturing vector. The shortening vector may be sent to the zero insertion subframe within the channel coding frame.

[0148] In one example, K bits of source information of downlink control information (DCI) or uplink control information (UCI) may be delivered via a CRC attachment box. The length J of the CRC bits may be determined by Figure 5 The code selection control box is determined by the code selection control box. This box can support possible CRC situations, such as single-length CRC, two separate CRCs, and ordinary CRC. Figure 13 ) and PC polarity encoding process (as shown Figure 17 The difference between the two codes (shown) may be the CRC length. For CA polarity codes, the CRC may be set to J+J'; for PC polarity codes, the CRC may be set to J.

[0149] The source bits (e.g., after a CRC is attached to the source bits) may be sent to Figure 5 The channel coding block can perform (multiple) polarity coding operations. Figure 5 As shown, the channel coding block may include one or more of the following sub-blocks: a zero insertion sub-block, a bit channel mapping sub-block, a sequence generation or selection sub-block, or a polar coding sub-block. The zero insertion sub-block may insert zeros into the (K+J) sequence (combined source bits and CRC bits). The position of the inserted zeros may depend on the shortening vector input from the rate matching control block. The sequence generation or selection sub-block may generate a ranked sequence (or select from a pre-generated ranked sequence) based on one or more of the following: a given mother code length N input from the rate matching control block, a code type input from the code selection control block, and / or other factors such as channel conditions (e.g., signal-to-noise ratio (SNR)). For example, for a CA polar code with a mother code length of 64 and an SNR of 5 dB, a ranked sequence may be selected or generated, or a ranked sequence may be selected from a list of pre-generated sequences. The bit mapping sub-block may map information and / or CRC bits to the appropriate bit channel for the polar code. This operation may depend on the code type and the input ranked sequence. For example, for PC polar codes, the bit mapping sub-box may determine, for example, an information set, a PC frozen set, and / or a frozen set, for example, based on a given ranked sequence. For CA polar codes, the bit mapping sub-box may determine, for example, the information set and the frozen set, for example, based on a given ranked sequence. The bit mapping sub-box may embed the WTRU ID and CRC bits using an operation such as an XOR operation. The WTRU ID may be embedded by XORing the WTRU ID with the PC frozen bits for the PC polar code. For example, the WTRU ID may be included in the frozen set. During the polar coding process, the frozen set may correspond to a number of constant bits (e.g., 0). In this case, the constant bit may be replaced with the WTRU ID. Inserting the WTRU ID into the frozen set may cause an unexpected UE to have a decoding error. The polar coding sub-box may perform a polar coding operation (e.g., a conventional polar coding operation), such as a generator matrix: or

[0150] like Figure 5 As shown, the polarity coded bits may be sent to a rate matching block. The rate matching block may perform puncturing or repetition operations. The selection of a puncturing vector or a repetition vector may be received from the rate matching block. Figure 7 An example of rate matching for polarity coded bits is shown. Figure 7 As shown, N=2 from the polar coding frame (not shown in the figure) nThe bits may be sent to an interleaver sub-frame within the rate matching frame. The interleaver sub-frame in the example may reorder the sub-blocks and the N polarity coded bits contained therein. The operation of the interleaver sub-frame may be associated with the rate matching scheme used. In one example, if puncturing from the top of the circular buffer and / or puncturing from the bottom of the circular buffer is used, the interleaver sub-frame may be transparent, i.e., no specific operation is required. In one example, if puncturing from the top with bit reversal and / or puncturing from the bottom of the circular buffer with bit reversal scheme is used, the interleaver sub-frame may perform a bit reversal operation on the N coded bits. In one example, if a distributed puncturing scheme is used, the interleaver sub-frame may perform an interleaving operation in the middle of the N coded bits. Similar operations may be used for one or more shortening schemes and / or repetition schemes.

[0151] The interleaved bits can be saved to a ring buffer or a virtual ring buffer. Figure 7 As shown, the operation of saving bits to the ring buffer can be performed by the bit collection sub-block. Figure 7 As shown, the bit selection sub-block may select bits from the circular buffer depending on a puncture vector or a repetition vector that may be generated by the rate matching control block. The puncture vector or the repetition vector may be interpreted to determine a pair of parameters associated with the circular buffer (e.g., a starting point, a duration).

[0152] In one example, when a puncturing scheme from the top of a circular buffer is applicable, the puncturing vector may be (0, ..., 0, 1, 1, ..., 1), and the first L bits are 0' and the last NL bits are 1', a pair of parameters may be determined (eg, L+1, NL). Figure 8 An exemplary bit selection is shown. Figure 8 As shown, the bits to be used may start at position L+1 of the circular buffer, and the bit sequence length may be NL. Similar operations can be applied to a scheme that punctures from the top of the circular buffer with bit reversal. In this scheme, the bits may be stored in the circular buffer after the bit reversal operation. Similar operations can be applied to a distributed puncturing scheme. In this scheme, the bits may be stored in the circular buffer after the interleaving or interleaving operation is performed on the N coded bits.

[0153] In one example, where a puncturing scheme from the bottom of a circular buffer can be applied, where the puncturing vector can be (1,…,1,0,…,0), and where the first L bits are 1' and the last NL bits are 0', a pair of parameters (e.g., 1, L) can be determined. Figure 9 An exemplary bit selection is shown. Figure 9 As shown, the bits to be used may start at the first position of the circular buffer, and the bit sequence length is L.

[0154] A similar operation can be applied to the scheme of "punching from the bottom of the ring buffer with bit reversal". In this scheme, the bits can be retained in the ring buffer after the bit reversal operation.

[0155] In one example, where a scheme of repeating from the top of a circular buffer may be applied, where the repeating vector may be (1,…,1,0,…,0), and where the first L bits are 1' and the last NL bits are 0', a pair of parameters (e.g., 1, N+L) may be determined. Figure 10 An exemplary bit selection is shown. Figure 10 As shown, the bits to be used may start at the first position of the circular buffer, and the bit sequence length is N+L.

[0156] In one example, where a scheme of repeating from the bottom of a circular buffer can be applied, where the repeating vector can be (0,…,0,1,…,1), and where the first NL bits are 0' and the last L bits are 1', a pair of parameters (e.g., NL, N+L) can be determined. Figure 11 An exemplary bit selection is shown. Figure 11 As shown, the bits to be used may start at the first position of the circular buffer, and the bit sequence length is N+L.

[0157] The starting point and / or the ending point may be located on the first or last coded bit. In some examples, neither the starting point nor the ending point may be located on the first or last coded bit. In the case of a hybrid scheme using a top-puncturing scheme and a bottom-puncturing scheme, the starting point and the ending point may be middle bits of the coded bits. In one example, where 1-bit shortening and top-puncturing can be used, the puncturing vector may be (0, ..., 0, 1, ..., 1, 0), where the first L bits are 0' and the following N-L-1 bits are 1' and the last bit is 0. A pair of parameters (e.g., L+1, N-1) may be determined. Figure 12 An exemplary bit selection is shown.

[0158] Advanced PC polarity codes with CA list selection can be provided. For example, polarity codes can be provided as a hybrid of PC polarity codes with CRC auxiliary list selection capability. Figure 13 and 14 Example encoding and decoding of CA polar codes, respectively, in a long CRC scenario (eg, as described herein) are shown. Figure 13 An exemplary encoding of a CA polar code with a long CRC is shown. Figure 14 An exemplary decoding for a CA polar code with a long CRC is shown.

[0159] like Figure 13As shown, on the encoding side, long CRC bits (J+J') can be appended to the information bits. A 16-bit level J can be used as the CRC length, for example, as specified for LTE control channels. Other values ​​of J are also possible, for example, as specified for other communication systems. The value J' can depend on the list size L within the cyclic redundancy check (CRC) assisted successive cancellation list (CA-SCL) decoder. In one example, J'=log2L. A basic polar code can be used to encode the K+(J+J') bits, and rate matching can be applied.

[0160] like Figure 14 As shown, on the decoder side, the demodulated symbols can be sent to the CA-SCL decoder. The SCL decoder block can output a list of L candidate sequences to the CRC auxiliary (CA) list selection block. The CA list selection block can feedback the sequence selected based on the CRC check result and / or the priority of the candidate sequences. If the L candidate sequences fail the CRC check (e.g., all L candidate sequences fail the CRC check), a detection error can be declared.

[0161] The (J+J') bits may be used in the CRC auxiliary list selection process (eg, error correction process). Error detection checks may be performed after the error correction because the selected sequence may have passed the CRC check.

[0162] Figure 15 and 16 Example encoding and decoding scenarios for CA polar codes with two separate CRCs (eg, as described herein), respectively, are shown. Figure 15 An exemplary encoding of a CA polar code with two separate CRCs is shown. Figure 16 An exemplary decoding of a CA polar code with two separate CRCs is shown.

[0163] like Figure 15 As shown, on the encoding side, JCRC bits can be appended to the K information bits. These CRC bits can be used for error detection. Additional J'CRC bits can be appended to the information bits with the CRC for error detection. These J'CRC bits can be used for error correction. Figure 15 As shown, the resulting (K+J+J') bits can be encoded by a PC polar encoder. Rate matching can be applied to the polar coded bits.

[0164] like Figure 16As shown, on the decoder side, the demodulated symbols may be sent to a CA-SCL decoder, wherein the SCL decoder block may provide a list of L candidate sequences to a CA list selection block. The CA list selection block may feed back the selected sequence to the SCL decoder. The CA list selection block may select a sequence based on the J'-bit CRC check result and / or the priority of the candidate sequence. In the event that the L candidate sequences fail the CRC check (e.g., all of the L candidate sequences fail the CRC check), a detection error may be declared, such as Figure 16 The decoded sequence or error declaration can be passed to a CRC check box. This CRC check box can use a J-bit CRC for error detection. If the CRC check passes, the sequence can be sent to the output terminal. Otherwise, an error is detected and / or a decoding failure can be declared.

[0165] Figure 17 and 18 Exemplary encoding and decoding for a PC polar code with a CRC (eg, as described herein) are shown, respectively. Figure 17 An exemplary encoding using a PC polar encoder is shown. Figure 18 An exemplary decoding for PC polar code is shown.

[0166] like Figure 17 As shown, on the encoding side, JCRC bits can be appended to the K information bits. These CRC bits can be used for error detection. The (K+J) bits can be encoded using PC polarity codes. The PC polarity coded bits can be rate matched. In the PC polarity codes, multiple frozen bits can be selected as PC frozen bits. The PC frozen bits can be used for error correction, for example, during the candidate sequence selection process.

[0167] like Figure 18 As shown, on the decoder side, the demodulated symbols can be sent to a PC-SCL decoder, where the PC-SCL decoder block can output a single sequence. The sequence can be passed to a CRC check. If the CRC check passes, the sequence can be sent to the output. Otherwise, an error can be detected and / or decoding failure can be declared.

[0168] PC polarity codes are disclosed herein as a combination of PC polarity codes and CRC auxiliary list selection capability. Such encoding is similar to, for example, reference Figure 17 An exemplary PC polar encoding scenario is shown.

[0169] Figure 19 An exemplary decoder for PC polar code with CRC auxiliary list selection is shown. Figure 19As shown, at the decoder side, the demodulated symbols may be sent to a cascaded PC-SCL decoder. The cascaded PC-SCL decoder block may include a modified PC-SCL decoder sub-block and a CRC auxiliary list selection sub-block. The modified PC-SCL decoder may generate a list of L candidate sequences (e.g., rather than a single sequence (e.g., Figure 18 Each of the L candidate sequences can be passed to an internal PC checksum within the decoder. The modified PC-SCL decoder can output L candidate sequences, and the modified PC-SCL decoder acts as an SCL decoder, which is different from, for example, a PC SCL decoder that can output a single codeword. The L candidate sequences can be associated with one or more ranks. The candidate sequences can pass a CRC checksum, for example, based on the J CRC bits. If a high-ranked sequence passes the CRC checksum, then that sequence can be identified as the decoded sequence. If no sequence passes the CRC checksum, then a detection / decoding failure can be declared.

[0170] The selection of the polarity code type may depend on one or more of the following: WTRU capabilities, WTRU category, or WTRU configuration. For example, for a WTRU with high capabilities, advanced PC polarity codes may be utilized. For a WTRU with low capabilities, basic polarity codes may be utilized. The selection of the polarity code may be determined based on the WTRU category. For example, WTRU categories 1, 2, and 3 may correspond to basic polarity codes, while WTRU categories 4, 5, and 6 may correspond to advanced PC polarity codes. The performance of CA polarity codes and PC polarity codes may depend on the list size utilized within the SCL decoding. In the case of larger list sizes, PC polarity codes may outperform CA polarity codes, while in the case of smaller list sizes, CA polarity codes may outperform PC polarity codes. The selection of the polarity code to be utilized may depend on the list size that the WTRU can support. The list size may be a portion of the WTRU capabilities.

[0171] Puncture vector generation for shortening and / or puncturing can be provided. Puncture and / or shortening schemes can be used to exclude some bits from the output coded bits. This may not affect the code construction. The shortening scheme can puncture the output coded bits and set the corresponding input bits to zero. These input bits can be included in the frozen bit set. These input bits can be different from other frozen bits that are set to a predefined value (e.g., a non-zero value). Since some input bits are pre-set to frozen bits due to shortening, the frozen bit set may need to be adjusted accordingly.

[0172] The corresponding input bits may depend on the bit reversal (BR) operation included in the polar encoding process. When the input bit index corresponding to the output bit is the BR of the output bit index. When the BR operation is not included in the polar coding process When the input bit and the output bit have the same index, the input bit may correspond to the output bit.

[0173] The difference between puncturing and shortening lies in the way of performing decoding. When calculating the log-likelihood ratio (LLR) value or probability of each output bit according to the received signal, the LLR value or probability of each punctured (shortened) output bit can be defined. For the puncturing scheme, the LLR value can be set to log(1)=0. For example, it can indicate that the probability of the punctured bit being 0 or 1 is the same. For the shortening scheme, the LLR value can be set to log(0)=-∞, which can imply that the punctured bit is equal to 0 (for example, it is always equal to 0)

[0174] The puncturing scheme and the shortening scheme can generate a puncturing vector to be used within a rate matching box as shown in Figure 5 The puncturing scheme and / or the shortening scheme can be provided so that a common puncturing vector can be generated for puncturing and / or shortening.

[0175] In one example, a mother code with length N = 2 n has M bits to be punctured or shortened. Let P(i) be the position of the i-th punctured bit, 0 ≤ i < M. Let I s (i) be the input bit position corresponding to the punctured bit P(i). In the case of shortening, the I s (i) bits can be shortened and set to frozen bits.

[0176] In one example, I s (i) can be selected as:

[0177] I s (i) = N - 1 - i, if i < N / 4,

[0178] If i ≥ N / 4 and

[0179] If i ≥ N / 4 and where can be the largest integer less than x. mod(a,b) can be the remainder of a / b.

[0180] This puncturing / shortening can be extended to:

[0181] I s (i) = N - 1 - i, if i < N / 2 G ,

[0182] If i ≥ N / 2 G as well as

[0183] In one example, I s (i) may be selected as:

[0184] If mod(i,G)=0

[0185] If mod(i,G)=g≠0

[0186] In one example, sub-block based puncturing may be used. For a mother code length N, the N bits (e.g., N polarity coded bits) may be divided (e.g., equally divided) into b sub-blocks. The b sub-blocks may be divided in a sequential manner. The number of sub-blocks b may be assumed to be a power of 2. Each sub-block may have bits. s (i) The following options may be selected:

[0187]

[0188] Functions d1 and d2 may be predefined independently, or d1 may be a function of d2. Function d1() may be a mapping function that determines the position of the sub-block within the sub-block set. Function d2() may be a mapping function that determines the position of a bit within the sub-block.

[0189] In one example, d2() can be defined in a manner where d2[i]=i. d1 can depend on the reliability distribution of the bit channel of the polar code. d1[0] can correspond to the least reliable block of the bit channel. d1[1] can correspond to the second least reliable block of the bit channel, and so on. For example, for d=2, we can make d1[0]=0, d1[1]=1; for d=4, we can make d1[0]=0, d1[1]=1; d1[2]=2, d1[1]=3; for b=8, we can make d1[0]=0, d1[1]=1, d1[2]=2, d1[3]=4, d1[4]=3, d1[5]=5, d1[6]=6, d1[7]=7; (mode 1) or d1[0]=0, d1[1]=1, d1[2]=4, d1[3]=2, d1[4]=3, d1[5]=5, d1[6]=6, d1[7]=7. When b=8, mode 1 can be regarded as starting from the end index. Interleaver Mode+ Interleaved Mode+ Symmetric interleaver mode. The interleaver pattern is d1[0]=0, d1[1]=1, and mode 1 can be generated.

[0190] Mode 1 can be expressed in a table format as shown in Table 3. Other modes can be expressed in table form.

[0191]

[0192]

[0193] Table 3

[0194] For the case of b=16, we can make:

[0195] d1[0]=0,d1[1]=1,d1[2]=2,d1[3]=4,d1[4]=8,d1[5]=3,d1[6]=5,d1[7]=6,d1[8]=9,d1[9]=10,d1

[10] =12,d1

[11] =7,d1

[12] =11,d1

[13] =13,d1

[14] =14,d1

[15] =15; (Mode 2)

[0196] or

[0197] d1[0]=0, d1[1]=1, d1[2]=2, d1[3]=3, d1[4]=4, d1[5]=8, d1[6]=5, d1[7]=6, d1[8]= 9, d1[9]=10, d1

[10] =12, d1

[11] =7, d1

[12] =11, d1

[13] =13, d1

[14] =14, d1

[15] =15;

[0198] or

[0199] d1[0]=0, d1[1]=1, d1[2]=2, d1[3]=4, d1[4]=3, d1[5]=8, d1[6]=5, d1[7]=6, d1[8]= 9, d1[9]=10, d1

[10] =12, d1

[11] =7, d1

[12] =11, d1

[13] =13, d1

[14] =14, d1

[15] =15;

[0200] Mode 2 can be expressed in a tabular format as shown in Table 4.

[0201] i <![CDATA[d1(i)]]> i <![CDATA[d1(i)]]> i <![CDATA[d1(i)]]> i <![CDATA[d1(i)]]> 0 0 4 8 8 9 12 11 1 1 5 3 9 10 13 13 2 2 6 5 10 12 14 14 3 4 7 6 11 7 15 15

[0202] Table 4

[0203] For the case of b=32, we can make:

[0204] d1[0] = 0, d1[1] = 1, d1[2] = 2, d1[3] = 4, d1[4] = 8, d1[5] = 16, d1[6] = 3, d1[7] = 5, d1[8] = 6, d1[9] = 9, d1

[10] = 10, d1

[11] = 17, d1

[12] = 12, d1

[13] = 18, d1

[14] = 20, d1

[15] = 7, d1

[16] = 24, d1

[17] = 11, d1

[18] = 13, d1

[19] = 19, d1

[20] = 14, d1

[21] = 21, d1

[22] = 22, d1

[23] = 25, d1

[24] = 26, d1

[25] = 28, d1

[26] = 15, d1

[27] = 23, d1

[28] = 27, d1

[29] = 29, d1

[30] = 30, d1

[31] = 31.

[0205] The expression (1) can also be expressed as:

[0206]

[0207] where d′1[i] = b - 1 - d1[i], d′2[i] = B - 1 - d2[i], and / or where d′1[i] = d1[i], d′2[i] = d2[i]. In one example, d1() can be expressed as in pattern (1) or pattern (2) or within other patterns described herein. In one example, d2() can be expressed as d2(i) = i.

[0208] The value of d1[i] can be derived by classifying the value representing each block i. If i indicates a block with an input bit index from B×(i - 1) to B×(i - 1) + B - 1, then the representative value can be the average reliability value, or the minimum reliability value or the maximum reliability value of the said range. d1[i] can be the index of the sub - block with the i - th representative value.

[0209] Some d1[i′] and d1[i″] (i′≠i″) within the derived d1[i] are exchangeable, for example, to improve the properties of the Hamming distance and the error performance of shortening and puncturing. A common total puncturing vector for puncturing and / or shortening can be used, and the determination of shortening or puncturing can be based on a specific criterion. This criterion can be the code rate described herein.

[0210] The common total puncturing vector can be divided into a puncturing part and a shortening part, where this common puncturing vector can be shared between puncturing and shortening. In one example, shortening can be used for P(i), i < p0, while puncturing can be used for P(i), i ≥ p0. p0 can be fixed or can depend on the code rate (or mother code rate) or p. p can be the total number of puncturing and shortening, and p0 ≤ p. When shortening can be used, the corresponding input bit position I s(i) can be set to 0, where P(i) = BR(I s (i), n), or in the case where the BR operation is not applied to the polar encoder, p(i) = I s (i) Here, BR(x,n) may be bit-reversed for the integer x according to n bits; the unfrozen bits within the polar encoder may be rearranged according to the index of these zero-valued input bits; and these zero-valued input bits may be excluded during the unfrozen bit selection process.

[0211] Figure 20 An exemplary BLER comparison between the proposed sub-block based puncturing and shortening schemes is shown. In the shortening example with N=512, K=126, and P=182, CA-SCL decoding is applied with a list size of 8 and a CRC length of 16. This example is the second mode or the case of b=16. As can be seen from the results, the exemplary scheme has a BLER of 10 -3 The coding gain can be ~0.35dB at a BLER of .

[0212] When R(i) is the position of the i-th repeated bit, R(i) = P(N–1-(i%N)). i can be greater than N-1 for repetition. i can be less than N-1 for puncturing and / or shortening. The repetition pattern can be configured based on a common puncturing vector that can be used for puncturing and shortening. An interleaver (such as that described herein) can be configured based on R(i) or P(i), and the i-th bit position (index) after interleaving can be the R(i)-th bit position (index) before interleaving (e.g., where the index starts at zero).

[0213] The interleaver mode d1() or d′1() can be determined as indicated by Expression 1 or 2 and can be used for sub-block level interleaving. Referring to Expression 1 or 2, may be the index of the bit before applying subblock-based interleaving, which corresponds to the i-th bit after applying subblock-based interleaving. In this expression, i may be the index of the bit after interleaving. The number of bits in a subblock or the subblock size B may be determined as: Where N is the number of polarity coded bits (eg, mother code length), and b is the number of sub-blocks. It may be the index of the interleaved sub-block containing the i-th bit after interleaving. may be the index of the subblock before interleaving. mod(i, B) may be the index of the i-th bit within the interleaved subblock. d2() may be the interleaver mode within the subblock. In one example, the expression d2(x) = x may indicate that interleaving is not applied within the subblock. d2(mod(i, B)) may be the index of a bit within the subblock before interleaving, which may correspond to the i-th bit within the subblock after subblock-level interleaving is applied.

[0214] Figure 21 Shown with the use of Example of a sub-block interleaver for 8 sub-blocks indexed by [0, 1, 2, 4, 3, 5, 6, 7]. In this example, the polarity coded bits may be divided (e.g., equally and sequentially) into 8 sub-blocks (e.g., sub-block 0 to sub-block 7). These 8 sub-blocks may be interleaved based on interleaver mode 1. Based on mode 1, the sub-blocks may be rearranged in the order [0, 1, 2, 4, 3, 5, 6, 7]. The rearranged sub-blocks may be stored as a ring buffer.

[0215] Figure 22 Shown with the use of Example of a sub-block interleaver for 16 sub-blocks indexed. The polarity coded bits may be divided (e.g., equally divided) into 16 sub-blocks. The 16 sub-blocks may be interleaved based on an interleaver pattern (mode 2 described herein). Based on mode 2, the sub-blocks may be rearranged in the order [0, 1, 2, 4, 8, 3, 5, 6, 9, 10, 12, 7, 11, 13, 14, 15].

[0216] Interleaver pattern Mode 1 can be extended to 16 subblocks by doubling each subblock to 2 subblocks. For example, the middle 8 subblocks can be interleaved or staggered, while the top 4 subblocks and the bottom 4 subblocks can remain unchanged. The interleaver pattern is as follows:

[0217] d1[0]=0, d1[1]=1, d1[2]=2, d1[3]=3, d1[4]=4, d1[5]=8, d1[6]=5, d1[7]=9, d1[8]= 6, d1[9]=10, d1

[10] =7, d1

[11] =11, d1

[12] =12, d1

[13] =13, d1

[14] =14, d1

[15] =15.

[0218] By quadrupling each subblock, the interleaver pattern Mode 1 described herein can be extended to 32 subblocks. For example, the middle 16 subblocks can be interleaved, while the top 8 subblocks and the bottom 8 subblocks can remain unchanged. The interleaver pattern is as follows:

[0219] d1[0]=0, d1[1]=1, d1[2]=2, d1[3]=3, d1[4]=4, d1[5]=5, d1[6]=6, d1[7]=7, d1[8]=8, d1[ 9]=16, d1

[10] =9, d1

[11] =17, d1

[12] =10, d1

[13] =18, d1

[14] =11, d1

[15] =19, d1

[16] =12, d1

[17] =20, d1

[18] =13, d1

[19] =21, d1

[20] =14, d1

[21] =22, d1

[22] =15, d1

[23] =23, d1[24 ]=24, d1

[25] =25, d1

[26] =26, d1

[27] =27, d1

[28] =28, d1

[29] =29, d1

[30] =30, d1

[31] =31.

[0220] Figures 23A-23C Shown with the use of Example of a subblock interleaver for 32 subblocks indexed. In this example, the middle 16 subblocks can be interleaved, while the top 8 subblocks and the bottom 8 subblocks can be copied directly from interleaver pattern Mode 1 (e.g., as described herein). This provides interleaver pattern Mode 3 as shown below:

[0221] d1[0]=0, d1[1]=1, d1[2]=2, d1[3]=4, d1[4]=3, d1[5]=5, d1[6]=6, d1[7]=7, d1[8]=8, d1[ 9]=16, d1

[10] =9, d1

[11] =17, d1

[12] =10, d1

[13] =18, d1

[14] =11, d1

[15] =19, d1

[16] =12, d1

[17] =20,d1

[18] =13,d1

[19] =21,d1

[20] =14,d1

[21] =22,d1

[22] =15,d1

[23] =23,d1

[24] =24,d1

[25] =25,d1

[26] =26,d1

[27] =28,d1

[28] =27,d1

[29] =29,d1

[30] =30,d1

[31] =31. (Mode 3)

[0222] This mode 3 can be expressed in the table format shown in Table 5.

[0223] i <![CDATA[d1(i)]]> i <![CDATA[d1(i)]]> i <![CDATA[d1(i)]]> i <![CDATA[d1(i)]]> i <![CDATA[d1(i)]]> i <![CDATA[d1(i)]]> i <![CDATA[d1(i)]]> i <![CDATA[d1(i)]]> 0 0 4 3 8 8 12 10 16 12 20 14 24 24 28 27 1 1 5 5 9 16 13 18 17 20 21 22 25 25 29 29 2 2 6 6 10 9 14 11 18 13 22 15 26 26 30 30 3 4 7 7 11 17 15 19 19 21 23 23 27 28 31 31

[0224] Table 5

[0225] The use of an interleaver may be provided after rate matching. A group basis channel interleaver may be provided. The output coded bits generated by the polar encoder may be interleaved. For example, the coded bits may be interleaved after applying the rate matching function and / or before modulation. The exemplary interleaving operation may provide improved block error rate (BLER) performance, for example, when using high order modulation or in the presence of a fading channel.

[0226] The input information bits may correspond to the output coded bits. The input information bits may have associated reliability rankings. The rate-matched output coded bits may be ranked based on the reliability rankings associated with the respective corresponding input information bits.

[0227] c(i) may be the value of the i-th coding and rate matching bit, where i = 0, 1, ..., NM may indicate the bit index of the output coded bits (e.g., natural order, sequence index from the starting point). M may be a rate matching parameter, which may be the number of bits to be punctured or shortened. In one example, rate matching may be performed by repetition. In this example, M may be a negative number. When output bits are repeated, the index order of the output bits may be associated with the same index order associated with the original repeated bits.

[0228] cr(j) may be the value of the (N–M–1-j)th reliable output coded bit, where j = 0, 1, …, NM may indicate the reliability index of the output coded bit. The reliability ranking of the output coded bit may follow the reliability ranking of the corresponding input bit. When the corresponding input bit may be a frozen bit and / or a parity bit, the associated reliability ranking may be relatively low and / or the lowest reliability ranking. When the output bit is repeated, the associated reliability ranking may be the same reliability ranking as the reliability ranking associated with the original repeated bit.

[0229] In one example, Q=2 may be used. q -ary modulation. The number of input bits provided for this modulation may be q. These bits may be used to generate modulation symbols. The reliability of these q bits may vary. For example, if q = 4, the first two bits may be classified as having a higher reliability than the last two bits of LTE 16QAM. Two levels of reliability may be provided for bits modulated using 16QAM.

[0230] In an example using 64QAM (e.g., where q=6), bits can be classified into three reliability levels. The first two bits can be classified as the most reliable, the next two or more bits can be classified as having lower reliability than the first two bits, and the last two bits can be classified as having the least reliability. q -ary modulation can have q / 2 reliability levels. Multiple and a certain number of reliability levels can be used

[0231] In one example, c(i), i=0, ..., NM bits may be divided into q / 2 blocks. The M bits are divided equally. BL(k) may indicate the kth block. After division, each block may be interleaved. The interleaver may be a random interleaver, a block interleaver, a bit reversal interleaver, a natural decomposition interleaver, etc. The effect of the selected interleaver used in rate matching may be counted (see, for example, Figure 7 In the example of a random interleaver, the interleaving pattern may be generated based on a pseudo-random sequence, which may include, for example, a gold sequence as used in LTE technology. In the case of a block interleaver, the same or different interleaver depths may be applied to the block interleaver.

[0232] In one example, cr(j), j = 0, ..., NM bits may be divided into q / 2 blocks. For example, the bits may be equally divided. Each sub-block may be represented by BL(k). Each sub-block (e.g., after division) may be interleaved using one or more interleavers. Each BL(k) block (e.g., after interleaving) may be mapped to input bits to be provided for modulation and associated with a particular reliability level,

[0233] For example, interleaved bits from the q / 2 blocks described herein can be mapped to modulation symbols. In one example, bits provided for modulation with high reliability can be associated with rate-matched coded bits with high reliability (e.g., which can correspond to input bits with high reliability). In one example, bits provided for modulation with low reliability can be associated with rate-matched coded bits with low reliability (e.g., which can correspond to input bits with low reliability). The kth component bit of the modulation symbol can be associated with BL(k). Figure 24 An exemplary implementation of this example using 16AQM is shown, where shaded boxes may indicate more reliable bits and unshaded boxes may indicate less reliable bits.

[0234] In one example, relatively less reliable bits provided for modulation may be associated with relatively more reliable rate-matched coded bits (e.g., bits that may correspond to more reliable input bits). In one example, relatively more reliable bits provided for modulation may be associated with relatively less reliable input bits (e.g., bits corresponding to relatively less reliable input bits). The kth component bit of the modulation symbol may be associated with BL(q / 2−k / 2). Figure 25An exemplary implementation of this example using 16QAM modulation is shown, where shaded boxes may indicate more reliable bits and unshaded boxes may indicate less reliable bits. These representations may apply to one or more of the coded bits and component bits of the modulation symbol examples. In other examples, 64QAM modulation and / or 256QAM modulation may be used.

[0235] In one example, the coding and rate matching bits may be partitioned into q / 2 blocks. In one example, the coding and rate matching bits may be partitioned into q blocks. Figure 26 An example implementation of this using 16QAM modulation and 4 partitions is shown. Figure 26 As shown, shaded boxes may indicate more reliable bits, while unshaded boxes may indicate less reliable bits. Figure 27 An exemplary QPSK modulation with two partitions is shown. Figure 28 An example of an exemplary QPSK modulation with two partitions is shown. q The number of divisions of the -ary modulation may include a number of divisions such as, for example, (q-1) divisions or a basic number of divisions. Figure 29 An exemplary QPSK modulation with 5 partitions is shown. The coding and rate matching bits may or may not be partitioned equally. For example, the blocks may have different numbers of bits.

[0236] Figure 30 An exemplary channel interleaver for a physical channel is shown. By using a parallel block interleaver, the operation can be applied to the uplink and / or downlink. Assume that the output of the rate matching may include M bits u1, ..., u M These bits can be divided into a number of groups. The number of groups can be denoted as p. For simplicity, M is divisible by p. If M is not divisible by p, null bits or dummy bits can be inserted into the output of the rate matcher so that the total number of bits is divisible by p.

[0237] The bits may be grouped based on a sequential order. The first group may include u1, u2, ..., u M / p , the second group may include And the pth group may include The bits may be grouped based on an interleaved order. The first group may include u1, u p+1 ,…,u M-p+1 , the second group may include u2,u p+2 ,…,u M-p+2 , and the pth group may include u p ,u 2p ,…,u M The bits can be grouped based on a subgrouping operation. Subgroups v1, ..., v q, where the subgroups may include u1,…,u M The number of bits of the subgroup v1,..,v q can be viewed as bits u1,…,u within the operations described herein M

[0238] The grouped bits can be passed to their corresponding interleavers. These interleavers can be block interleavers with the same depth, or block interleavers with different depths, or any interleavers. In the example of block interleavers, assume that d1, d2, ..., d p is the depth of the p block interleaver, d i Some or all of may have different values. i Can be a prime number. d i Other values ​​of may be possible.

[0239] The interleaved bits from the p groups may be combined into a joint output. The grouped interleaved bits may be combined in a group sequential order. For example, the first group interleaved bits may be generated first, the second group interleaved bits may be generated second, and so on. The grouped interleaved bits may be combined in a group order having a specific pattern. For example, the second group interleaved bits may be generated first, the fifth group interleaved bits may be generated second, and so on. The grouped interleaved bits may be combined in an interleaved order. For example, the order may be: first bit from the first group, first bit from the second group, ..., first bit from the last group, second bit from the first group, second bit from the second group, ..., second bit from the last group, third bit from the first group, .... The grouped interleaved bits may be jointly combined in an interleaved order (e.g., by using a group order).

[0240] Figure 31 An example interleaving that can be performed between rate matching and modulation is shown. In one example, interleaving can be performed first within the rate matching block. Interleaving performed after the rate matching block can be considered interleaving performed as part of the rate matching block or function.

[0241] An exemplary interleaver design may depend on the modulation order. A column-wise interleaver or block interleaver that performs interleaving after a rate matching block or function to achieve high-order modulation and performance in fading channels may be such that the number of rows may be equal to the modulation order or equal to the modulation order minus one.

[0242] The block interleaver following the rate matching block may be described by the depth of the rate matching block. Figure 32An example of a block interleaver with a depth of 5 (e.g., the number of rows of the block interleaver) is shown. The depth of the block interleaver may depend on the modulation order. For example, for 64QAM modulation, a block interleaver with a depth of 7 may not be sufficient (e.g., may not achieve the desired performance). For 16QAM modulation, a block interleaver with a depth of 7 may be sufficient (e.g., may achieve the desired performance).

[0243] like Figure 33 、 Figure 34 and Figure 35 As shown, a block interleaver with a depth of 11 is sufficient for QPSK, 16QAM and / or 64QAM modulation orders and AWGN channels and / or fading channels. Figure 32 This may be followed by a block interleaver with a depth of 11, having 11 rows. A fixed-depth uniform block interleaver may be used for each supported modulation order. For example, for simplicity, a fixed-depth uniform block interleaver may be used for each supported modulation order. Each supported modulation and / or modulation order may include a modulation and / or modulation order for which gain can be achieved using a block interleaver. The block interleaver used may include a block interleaver with a depth of 11 as a bit channel interleaver after the rate matching block for modulations such as QPSK, 16QAM, 64QAM, 16QAM, and / or 64QAM. One example may use a block interleaver with a depth of 11 as a bit channel interleaver after the rate matching block for each supported modulation order, for example, for modulations higher than 64QAM. A triangular interleaver may be used after the rate matching block, for example, to achieve performance similar to that achieved by a block interleaver. A random interleaver may be used after the rate matching block to achieve performance similar to that achieved by a block interleaver and / or a triangular interleaver.

[0244] Block interleavers with different depths can be used. For example, different depths can be used based on the modulation order. For example, a block interleaver with a depth of 5, 7, and / or 11 can be applied to QPSK modulation, and / or a block interleaver with a depth of 7 and / or 11 can be applied to 16QAM modulation. A block interleaver with a depth of 5 and / or 11 can be applied to 64QAM modulation. A block interleaver with a depth of 11 can be applied to 16QAM modulation, and / or a block interleaver with a depth of 5 can be applied to 64QAM modulation.

[0245] The depth of the block interleaver can be selected and / or specified based on the code rate. For example, at a high code rate, a smaller depth can be used. At a low code rate, a larger depth can be used. In the example of a 1 / 2 code rate, one or more depths can be used to achieve similar block error rate performance. In one example, a depth of 3 can be used for modulation orders (e.g., all modulation orders). In one example, when the code rate is 1 / 6, a larger depth (e.g., 11) can be used to achieve better block error rate performance than a shorter depth (e.g., 3 or 5). In one example, as described herein, the depth of the block interleaver can be selected and / or specified based on the modulation order and / or code rate.

[0246] If a natural decomposition shortening or puncturing scheme is used as a rate matching scheme, the interleaver within the rate matching block or function can be designed so that the coded bits can be equally divided into 4 groups. The second and third groups of the 4 groups can be interleaved.

[0247] Figure 36 An exemplary performance gain using a determinant-column interleaver for 16QAM modulation after the rate matching block is shown. Performance simulations for the natural decomposition puncturing example, the natural decomposition shortening example, the bit reversal shortening example, and the natural repetition example provide the results described herein. In these simulations, QPSK modulation and a QWGN channel are assumed. In these simulations, polar codes with PW sequences and a CA-SCL (L=8) decoding algorithm are used. A 19-bit CRC is appended to the source data. These CRC bits can be considered part of the information bits.

[0248] A triangular channel interleaver may be used in uplink (UL) transmissions. A parallel rectangular interleaver may be used in downlink (DL) transmissions. A triangular channel interleaver may be provided.

[0249] In one example, u1,…,u M is the M output bits of the rate matcher that can be transmitted. The minimum integer P can be determined so that Assumptions and y1,…,y Q y i =u i ,1≤i≤M, and y i =NULL,M+1≤i≤Q, such as Figure 49 As shown, the bit sequence y1,…,y Q The output of the triangular interleaver can be a bit sequence read out column by column starting from the first column, for example, y1,y P+1 ,y 2P ,…. In this process, null bits can be skipped.

[0250] Various variations of the triangular interleaver can be provided. In one example, null bits can be inserted at the beginning of the bit sequence from the rate matching block. The minimum integer P can be determined such that Assumptions and y1,…,y Q y i =NULL,1≤i≤QM and y i =u i-(Q-M) ,Q-M+1≤i≤Q, the bit sequence y1,…,y Q The isosceles right triangles are written row by row starting from the upper left corner of the array. For example, column permutation can be applied. The output of the triangular interleaver can be a bit sequence read out column by column starting from the first column, for example, y1,y P+1 ,y 2P ,…. In this process, empty bits can be skipped. It can be avoided that the bit sequence u1,…,u M Insert a null bit at the beginning of so that the first output bit is u1.

[0251] In one example, if Figure 50 As shown, the lower right corner of the array can be applied. M Insert a null bit at the end of . The minimum integer P can be determined so that Assumptions and y1,…,y Q y i =u i ,1≤i≤M, and make y i =NULL,M+1≤i≤Q, then Figure 50 As shown, the bit sequence y1,…,y can be written row by row starting from the lower right corner of the array. Q Write an isosceles right triangle. For example, column permutation can be applied. The output of the triangular interleaver can be a bit sequence read out column by column starting from the first column, for example, y Q-P+1 ,y Q-P+2 ,y Q-2P+2 .... During this process, null bits may be skipped.

[0252] In one example, the bit sequence u1,…,u M Insert the lower right corner of the array and the empty bit at the beginning of the array. The minimum integer P can be determined so that Assumptions and y1,…,y Q y i =NULL,1≤i≤QM, and make y i =u i-(Q-M) ,Q-M+1≤i≤Q, then Figure 50As shown, the bit sequence y1,…,y can be written row by row starting from the lower right corner of the array. Q Write an isosceles right triangle. For example, column permutation can be applied. The output of the triangular interleaver can be a bit sequence read out column by column starting from the first column, for example, y Q-P+1 ,y Q-P+2 ,y Q-2P+2 ,…. In this process, null bits may be skipped. Column-wise permutations may be applied, for example, to further randomize the output of the triangular interleaver.

[0253] A parallel triangular interleaver may be applied as described herein. For example, the output bits from the rate matcher, number M, may be divided into B groups. Each group may have the same number of bits or a different number of bits. Dummy / empty bits (one or more) may be added so that each group has the same number of bits. The number of groups may depend on the modulation order. The M output bits of the rate matcher may be divided in different ways. A triangular interleaver may be applied to the groups. The outputs of the triangular interleavers for each group may be combined, for example, via a cascade or interleaving operation. For example, v may be made i,1 ,…,v i,Q is the output bit from the ith group. Assuming there are 4 groups, if the interleaving operation is applied, the final output of the channel interleaver can be given as v 1,1 ,v 2,1 ,v 3,1 ,v 4,1 ,v 1,2 ,v 2,2 ,v 3,2 ,v 4,2, v 1,3 ,…,v 1,Q ,v 2,Q ,v 3,Q ,v 4,Q . Figure 30 The shown example can be applied to a triangular interleaver.

[0254] Figure 51 An example of a polar coding system is shown in FIG. Figure 51 As shown, the exemplary polar coding system may include one or more of the following: a CRC attachment and coding construction block, a rate matching control block, a polar coding block, a rate matching block, a channel interleaving block, or a modulation block. The channel interleaving block may be referred to as a channel interleaver or a bit interleaver. In one example, the channel interleaving block may be part of the rate matching block. Figure 51As described above, the polar coded bits N from the polar coding block may be rate matched based on the rate matching scheme generated by the rate matching control block as described herein. The rate-matched bits M may be passed through the channel interleaving block to interleave the M bits as described herein. The bits after the channel interleaving block may be sent to the modulation block to generate modulation symbols as described herein.

[0255] Although features and elements are described above in particular combinations, those skilled in the art will appreciate that each feature or element can be used alone without the other features and elements described, or in any combination with the other features and elements. Although the features described above consider New Radio (NR), 3G, 4G, 5G, LTE, LTE-A, and / or other examples, it should be understood that the features described herein are not limited to these technologies and may also be applicable to other wireless systems.

[0256] The processes described herein may be implemented using a computer program, software, or firmware, which may be incorporated into a computer-readable medium for execution by a computer and / or a processor. Examples of computer-readable media include, but are not limited to, electronic signals (transmitted via wired and / or wireless connections) and / or computer-readable storage media. Examples of computer-readable storage media include, but are not limited to, read-only memory (ROM), random access memory (RAM), registers, buffer memory, semiconductor memory devices, magnetic media (such as, but not limited to, internal hard disks and removable disks), magneto-optical media, and / or optical media (such as CD-ROM disks and / or digital versatile disks (DVDs)). A processor associated with the software is used to implement a radio frequency transceiver for use in a WTRU, terminal, base station, RNC, and / or any host computer.

Claims

1. A method implemented by a wireless transmit / receive unit (WTRU), the method comprising: generating a plurality of uplink control information (UCI) bits to be sent in a codeword; Applying a polarity code to the UCI bits to generate polarity-encoded UCI bits, wherein a mother code length associated with the polarity code is determined based on a codeword length used for transmission of the UCI; performing rate matching on the polarity-encoded UCI bits, wherein performing the rate matching comprises performing one of the following operations: If the code rate of the codeword is less than a threshold and the mother code length is greater than the codeword length, performing a puncturing scheme; or If the code rate of the codeword is greater than the threshold and the mother code length is greater than the codeword length, performing a shortening scheme; and Rate matched, polar coded UCI bits are transmitted.

2. The method according to claim 1, wherein The mother code length is determined based on the code rate.

3. The method according to claim 1, wherein The codeword also includes a plurality of cyclic redundancy check (CRC) bits.

4. The method according to claim 1, wherein The code rate corresponds to the number of UCI bits and cyclic redundancy check (CRC) bits in the codeword divided by the number of coded bits in the codeword.

5. The method according to claim 1, wherein The polar code includes a concatenated polar code.

6. A wireless transmit / receive unit (WTRU), transceiver; as well as A processor configured to: generating a plurality of uplink control information (UCI) bits to be sent in a codeword; A polarity code is applied to the UCI bits to generate polarity-encoded UCI bits, wherein A mother code length associated with the polar code is determined based on a codeword length used for transmission of the UCI; performing rate matching on the polarity-coded UCI bits, wherein the rate matching is performed using one of: If the code rate of the codeword is less than a threshold and the mother code length is greater than the codeword length, performing a puncturing scheme; and If the code rate of the codeword is greater than the threshold and the mother code length is greater than the codeword length, executing a shortening scheme; as well as Rate matched, polar coded UCI bits are transmitted.

7. The WTRU of claim 6, wherein the mother code length is determined based on the code rate.

8. The WTRU of claim 6, wherein the codeword further comprises a plurality of cyclic redundancy check (CRC) bits.

9. The WTRU of claim 6, wherein the code rate corresponds to the number of UCI bits and cyclic redundancy check (CRC) bits in the codeword divided by the number of coded bits in the codeword.

10. The WTRU of claim 6, wherein the polar code comprises a concatenated polar code.

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