Systems and methods for removing tungsten-containing films

Abstract

Exemplary etching methods may include: flowing a halogen-containing precursor into a remote plasma region of a semiconductor processing chamber while simultaneously exciting plasma to generate a plasma effluent. The method may include: contacting a substrate housed in the processing region with the plasma effluent. The substrate may define an exposed area of ​​tungsten oxide. Contact may generate tungsten fluoride oxyfluoride material. The method may include: flowing an etchant precursor into the processing region. The method may include: contacting the tungsten fluoride oxyfluoride material with the etchant precursor. The method may include: removing the tungsten fluoride oxyfluoride material.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit and priority of U.S. Nonprovisional Application No. 17 / 100,141, filed November 20, 2020, entitled “SYSTEMS AND METHODS FORTUNGSTEN-CONTAINING FILM REMOVAL,” the contents of which are incorporated herein by reference in their entirety for all purposes. Technical Field

[0003] This technology relates to semiconductor processing and equipment. More specifically, this technology relates to the selective etching of tungsten-containing structures. Background Technology

[0004] Integrated circuits are made possible by processes that create complex patterned material layers on a substrate surface. Creating patterned material on a substrate requires controlled methods to remove exposed material. Chemical etching is used for various purposes, including transferring patterns from photoresist to underlying layers, thinning layers, or reducing the lateral dimensions of features already present on a surface. Often, it is desirable to have etching processes that etch one material faster than another, facilitating, for example, pattern transfer processes. This etching process is referred to as selective etching for the first material. Due to the diversity of materials, circuits, and processes, selective etching processes for a wide variety of materials have been developed.

[0005] Depending on the materials used in the process, etching can be referred to as wet or dry. For example, wet etching can preferentially remove some oxide dielectrics compared to other dielectrics and materials. However, wet etching can be difficult to penetrate some confined trenches and may sometimes deform the remaining material. Dry etching, generated in localized plasma within the substrate processing area, can penetrate more confined trenches and exhibit less deformation of the fine remaining structure. However, localized plasma can damage the substrate by generating an electric arc during discharge.

[0006] Therefore, there is a need for improved systems and methods to produce high-quality equipment and structures. This technology addresses these and other needs. Summary of the Invention

[0007] Exemplary etching methods may include: flowing a halogen-containing precursor into a remote plasma region of a semiconductor processing chamber while simultaneously exciting plasma to generate a plasma effluent. The method may include: contacting a substrate housed in the processing region with the plasma effluent. The substrate may define an exposed area of ​​tungsten oxide. Contact may generate tungsten fluoride oxyfluoride material. The method may include: flowing an etchant precursor into the processing region. The method may include: contacting the tungsten fluoride oxyfluoride material with the etchant precursor. The method may include: removing the tungsten fluoride oxyfluoride material.

[0008] In some embodiments, the halogen-containing precursor may be or includes fluorine. The etchant precursor may be or includes a chlorine-containing precursor. The halogen-containing precursor may be or includes nitrogen trifluoride. The method may include: using the halogen-containing precursor to flow hydrogen. The hydrogen flow rate may be at least twice the flow rate of the halogen-containing precursor. During the flow of the etchant precursor, the semiconductor processing chamber may be maintained as plasma-free. The etching method may be performed at a temperature greater than or about 150°C. When the halogen-containing precursor is flowed, the pressure in the semiconductor processing chamber may be maintained below or about 15 Torr. When the etchant precursor is flowed, the pressure in the semiconductor processing chamber may be maintained above or about 15 Torr. The substrate may include an exposed area of ​​silicon oxide. Trenches may be formed through the silicon oxide to define an exposed area of ​​tungsten oxide.

[0009] Some embodiments of this technology may cover etching methods. The method may include: forming a plasma containing a first halogen precursor to generate a plasma effluent in a remote plasma region of a semiconductor processing chamber. The method may include: flowing the plasma effluent into a processing region of the semiconductor processing chamber. The method may include: contacting a substrate housed in the processing region with the plasma effluent. The substrate may include an exposed region of tungsten oxide covering a tungsten region at the bottom of a trench defined in the substrate. The plasma effluent may halogenate the tungsten oxide. The method may include: flowing a second halogen precursor into the processing region of the semiconductor processing chamber. The method may include: removing the halogenated tungsten oxide.

[0010] In some embodiments, the first halogen-containing precursor may be or include fluorine. The second halogen-containing precursor may be or include boron trichloride. The method may include stopping plasma formation before allowing the second halogen-containing precursor to flow. The first halogen-containing precursor may be or include nitrogen trifluoride. The method may include using the first halogen-containing precursor to flow hydrogen. The flow rate of hydrogen may be at least twice the flow rate of the first halogen-containing precursor. While allowing the first halogen-containing precursor to flow, the pressure in the semiconductor processing chamber may be maintained at less than or about 15 Torr. While allowing the second halogen-containing precursor to flow, the pressure in the semiconductor processing chamber may be maintained at more than or about 15 Torr.

[0011] Some embodiments of this technology may cover etching methods. Methods may include: forming a plasma containing a fluorine precursor to generate a plasma effluent in a remote plasma region of a semiconductor processing chamber. Methods may include: flowing the plasma effluent into a processing region of the semiconductor processing chamber. Methods may include: contacting a substrate housed in the processing region with the plasma effluent. The substrate may include an exposed area of ​​tungsten oxide covering a tungsten region. The plasma effluent may fluorinate the tungsten oxide. Methods may include: flowing a chlorine-containing precursor into a processing region of the semiconductor processing chamber. Methods may include: contacting a substrate with the chlorine-containing precursor. Methods may include: removing tungsten oxide.

[0012] In some embodiments, the method may include: using a fluorine-containing precursor to flow hydrogen. The flow rate of hydrogen may be at least twice the flow rate of the fluorine-containing precursor. When the fluorine-containing precursor is flowed, the pressure in the semiconductor processing chamber may be maintained at less than or about 10 Torr. When a chlorine-containing precursor is flowed, the pressure in the semiconductor processing chamber may be maintained at more than or about 20 Torr.

[0013] This technology offers numerous advantages over conventional systems and techniques. For example, the process allows for dry etching that protects features of the substrate. Furthermore, the process can selectively remove the tungsten-containing film relative to other exposed materials on the substrate. These and other embodiments, along with their many advantages and features, will be described in more detail below, together with the accompanying drawings. Attached Figure Description

[0014] A further understanding of the nature and advantages of the disclosed technology can be achieved by referring to the remainder of the specification and the accompanying drawings.

[0015] Figure 1 A top view of one embodiment of an exemplary processing system according to some embodiments of the present technology is shown.

[0016] Figure 2A A schematic cross-sectional view of an exemplary processing chamber according to some embodiments of the present technology is shown.

[0017] Figure 2B Some embodiments according to the present technology are shown. Figure 2A Detailed views of the processing chamber section as described in the diagram.

[0018] Figure 3 A bottom view of an exemplary shower head according to some embodiments of the present technology is shown.

[0019] Figure 4 Exemplary operations of methods according to some embodiments of the present technology are shown.

[0020] Figures 5A-5B A schematic cross-sectional view of an etched material according to some embodiments of the present technology is shown.

[0021] Several accompanying drawings are included as illustrations. It should be understood that the drawings are for illustrative purposes and are not to be considered to scale unless specifically stated otherwise. Furthermore, as illustrations, the drawings are provided to aid understanding and may not include all aspects or information compared to realistic representations, and may include additional or exaggerated material for illustrative purposes.

[0022] In the accompanying drawings, similar components and / or features may have the same reference numerals. Additionally, various components of the same type may be distinguished by letters following the reference numerals, which differentiate similar components. If only the preceding reference numerals are used in the description, regardless of the letters, the description applies to any similar components having the same preceding reference numerals. Detailed Implementation

[0023] As 3D NAND gate structures grow within cells to be formed, the aspect ratios of memory vias, contact windows, and other structures sometimes increase significantly. During 3D NAND gate processing, the stacking of placeholder layers and dielectric materials can form inter-electrode dielectric layers or polysilicon interlayer dielectric (IPD) layers. These placeholder layers can be subjected to various operations to accommodate the structure before completely removing the material and replacing it with metal. IPD layers are often formed over conductor layers, such as polysilicon. When forming memory vias, the vias can extend through alternating layers of all materials before entering the polysilicon or other material substrate. Subsequent processing can form stepped structures for contacts and can also laterally excavate placeholder material.

[0024] Reactive ion etching (“RIE”) operations can be performed to create high aspect ratio memory vias. RIE processes often involve a combination of alternating layers of chemical and physical removal, which can form a carbon polymer layer on the sidewalls during etching and protect the layer from further etching. After the memory structure is formed, additional RIE processes can be performed to form contact windows through the dielectric material layer, or additional RIE processes can be performed to create, for example, multi-level contacts. The process can etch down through the dielectric to expose contact landings or contact pads, which may be metallic. During subsequent ashing processes, the carbon polymer layer may be removed, or during subsequent mask removal, the exposed metal may be at least partially oxidized along the contact surface. Since this contact may be the electrical contact for the memory structure, the oxidized interface can increase the impedance at the landing, which may adversely affect device performance.

[0025] Conventional techniques have often overlooked these oxide regions because additional removal can introduce further damage. For example, additional RIE etching to remove oxides can damage the underlying metal on the contact platform due to ion bombardment from the RIE process. Additional etching can also etch the dielectric material that forms the contact opening and can further affect the aspect ratio by increasing the critical size of the opening. This technique overcomes these limitations by performing a selective etching process to remove the metal oxide material. The etching process can be selective for the dielectric material that forms the opening and also for the underlying metal. By utilizing the etching process to perform chemical removal of the oxide material, metal sputtering can also be limited or prevented.

[0026] While the remaining disclosure will conventionally identify specific materials and semiconductor structures utilizing the disclosed techniques, it will be readily understood that the systems, methods, and materials are equally applicable to some other structures that may benefit from the present technology. Therefore, the technology should not be considered limited to 3D NAND gate processing or materials alone. Furthermore, although exemplary chambers are described to provide the basis for the present technology, it should be understood that the technology can be applied to substantially any semiconductor processing chamber that allows for the described operations.

[0027] Figure 1 This figure shows a top view of one embodiment of a processing system 100 with deposition, etching, baking, and curing chambers according to an embodiment. In the figure, a pair of front-opening wafer transfer cassettes 102 supply substrates of various sizes, which are received by a robotic arm 104 and placed in a low-pressure holding area 106 before being placed into one of the substrate processing chambers 108a-f, located in serial areas 109a-c. A second robotic arm 110 is used to transfer substrate wafers from the holding area 106 to the substrate processing chambers 108a-f and to transfer substrate wafers back. Each substrate processing chamber 108a-f can be equipped to perform a number of substrate processing operations, including dry etching processes as described herein, as well as cyclic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, degassing, orientation, and other substrate processing.

[0028] The substrate processing chambers 108a-f may include one or more system components for depositing, annealing, curing, and / or etching dielectric films on a substrate wafer. In one configuration, two pairs of processing chambers, such as 108c-d and 108e-f, may be used to deposit dielectric material on the substrate, and a third pair of processing chambers, such as 108a-b, may be used to etch the deposited dielectric. In another configuration, all three pairs of chambers, such as 108a-f, may be configured to etch dielectric films on the substrate. Any one or more of the described processes may be performed in chambers separate from the manufacturing systems shown in the different embodiments. It will be appreciated that system 100 is contemplated for additional configurations of chambers for the deposition, etching, annealing, and curing of dielectric films.

[0029] Figure 2A A cross-sectional view of an exemplary processing chamber system 200 having partitioned plasma generation regions within a processing chamber is shown. During film etching, a process gas, such as titanium nitride, tantalum nitride, tungsten, silicon, polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, etc., can flow through a gas inlet assembly 205 into a first plasma region 215. A remote plasma system 201 may be optionally included in the system and can process the first gas that then travels through the gas inlet assembly 205. The inlet assembly 205 may include two or more separate gas supply channels, wherein a second channel (not shown) may bypass the RPS 201, if included.

[0030] According to an embodiment, a cooling plate 203, a panel 217, an ion suppressor 223, a spray head 225, and a base 265 or a substrate support having a substrate 255 disposed thereon are shown, and each of these may be included. The base 265 may have heat exchange channels through which heat exchange fluid flows to control the temperature of the substrate, and it may be operated during processing operations to heat and / or cool the substrate or wafer. The wafer support pad of the base 265, which may include aluminum, ceramic, or a combination thereof, may also be resistively heated using an embedded resistance heater assembly to achieve relatively high temperatures, such as from up to or about 100°C to above or about 1100°C.

[0031] Panel 217 may be pyramidal, conical, or other similar structures with a narrow top extending to a wide bottom. Panel 217 may also be flat as shown and include multiple through channels for distributing the process gas. Depending on the use of RPS 201, plasma-generating gas and / or plasma excitation material may pass through multiple openings in panel 217. Figure 2B (as shown in the figure) to deliver more evenly to the first plasma region 215.

[0032] An exemplary configuration may include a gas inlet assembly 205 leading to a gas supply region 258 separated from the first plasma region 215 by the panel 217, such that gas / material flows through perforations in the panel 217 into the first plasma region 215. Selectable structural and operational features may prevent significant backflow of plasma from the first plasma region 215 into the supply region 258, the gas inlet assembly 205, and the fluid supply system 210. The conductive top of the panel 217 or chamber and the spray head 225 are shown with an insulating ring 220 located between features, which allows an AC potential to be applied to the panel 217 relative to the spray head 225 and / or the ion suppressor 223. The insulating ring 220 may be located between the panel 217 and the spray head 225 and / or the ion suppressor 223, allowing capacitively coupled plasma to form in the first plasma region. A baffle (not shown) may be additionally located in the first plasma region 215 or otherwise coupled to the gas inlet assembly 205 to affect the flow of fluid through the gas inlet assembly 205 into the region.

[0033] The ion suppressor 223 may comprise a plate or other geometry whose distributed structure defines a plurality of holes configured to suppress the migration of ionic charged material out of the first plasma region 215 while allowing uncharged neutral or free radical material to pass through the ion suppressor 223 into an activated gas delivery region between the suppressor and the spray head. In embodiments, the ion suppressor 223 may comprise a perforated plate with various hole configurations. These uncharged materials may include highly reactive materials transported through the holes using a less reactive carrier gas. As noted above, migration of ionic material through the holes can be reduced and, in some instances, completely suppressed. Controlling the amount of ionic material passing through the ion suppressor 223 can advantageously provide increased control over the gas mixture in contact with the underlying wafer substrate, which in turn can increase control over the deposition and / or etching characteristics of the gas mixture. For example, adjusting the ion concentration of the gas mixture can significantly alter its etch selectivity, such as the SiNx:SiOx etch ratio, the Si:SiOx etch ratio, and so on. In alternative embodiments where deposition is performed, the balance between conformal and flowable deposition can also be altered for the dielectric material.

[0034] Multiple orifices in the ion suppressor 223 can be configured to control the passage of activated gases (i.e., ionic, free radical, and / or neutral substances) through the ion suppressor 223. For example, the aspect ratio of the orifices, or the diameter-to-length ratio of the orifices, and / or the geometry of the orifices can be controlled to reduce the flow of ionic charged substances in the activated gases through the ion suppressor 223. The orifices in the ion suppressor 223 may include a tapered portion facing the plasma excitation region 215 and a cylindrical portion facing the spray head 225. The cylindrical portion can be shaped and sized to control the flow of ionic substances to the spray head 225. An adjustable electrical bias can also be applied to the ion suppressor 223 as an additional means of controlling the flow of ionic substances through the suppressor.

[0035] Ion suppressor 223 can be used to reduce or eliminate the amount of ionic charged matter traveling from the plasma generation region to the substrate. Uncharged neutral and free radical matter can still react with the substrate through openings in the ion suppressor. It should be noted that complete elimination of ionic charged matter in the reaction region surrounding the substrate may not be performed in the embodiments. In some instances, ionic matter is intended to reach the substrate to perform etching and / or deposition processes. In these instances, the ion suppressor helps control the concentration of ionic matter in the reaction region to a level conducive to processing.

[0036] The combination of the spray head 225 and the ion suppressor 223 allows plasma to exist in the first plasma region 215 to avoid directly exciting the gas in the substrate processing region 233, while still allowing excited material to travel from the chamber plasma region 215 to the substrate processing region 233. In this way, the chamber can be constructed to prevent plasma from contacting the substrate 255 being etched. This advantageously protects various complex structures and patterned films on the substrate, which could be damaged, misaligned, or warped if directly exposed to the generated plasma. Additionally, when plasma is allowed to contact the substrate or approach the substrate level, the etching rate of oxide materials may increase. Therefore, if the exposed area of ​​the material is oxide, this material can be further protected by keeping the plasma away from the substrate.

[0037] The processing system may further include a power supply 240 electrically coupled to the processing chamber to provide power to the panel 217, ion suppressor 223, spray head 225, and / or base 265 to generate plasma in the first plasma region 215 or processing region 233. Depending on the process being performed, the power supply may be configured to deliver an adjustable amount of power to the chamber. This configuration allows the use of adjustable plasma in the process being performed. Unlike remote plasma units that often exhibit on or off functionality, adjustable plasma can be configured to deliver a specific amount of power to plasma region 215. This, in turn, allows for the development of specific plasma characteristics, enabling precursors to be decomposed in a particular manner to enhance the etch profile produced by these precursors.

[0038] Plasma can be ignited in the chamber plasma region 215 above the spray head 225 or in the substrate processing region 233 below the spray head 225. Plasma can be present in the chamber plasma region 215 to generate free radical precursors from the inflow of, for example, fluorine-containing precursors or other precursors. During deposition, an AC voltage, typically in the radio frequency (“RF”) range, can be applied between the conductive top of a processing chamber, such as panel 217, and the spray head 225 and / or ion suppressor 223 to ignite plasma in the chamber plasma region 215. The RF power supply can generate a high RF frequency of 13.56 MHz, but other frequencies, either alone or in combination with the 13.56 MHz frequency, can also be generated.

[0039] Figure 2B A detailed view 253 shows characteristics affecting the distribution of the processed gas through panel 217. (See also...) Figure 2A and Figure 2B As shown, panel 217, cooling plate 203, and gas inlet assembly 205 intersect to define a gas supply region 258 from which process gas can be supplied. Gas can fill gas supply region 258 and flow through aperture 259 in panel 217 to first plasma region 215. Aperture 259 can be configured to guide flow in a substantially unidirectional manner, allowing process gas to flow into processing region 233, but partially or completely preventing backflow into gas supply region 258 after passing through panel 217.

[0040] Gas distribution assemblies such as those used for spray heads 225 in the processing chamber area 200 can be referred to as dual-channel spray heads and Figure 3 The embodiments described herein are further described in detail. The dual-channel spray head can provide an etching process that allows the etchant to be separated from the processing area 233, in order to provide confined interaction with or with the chamber components before being delivered to the processing area.

[0041] The spray head 225 may include an upper plate 214 and a lower plate 216. These plates may be coupled to each other to define a volume 218 between them. This coupling of the plates may provide a first fluid passage 219 through the upper and lower plates, and a second fluid passage 221 through the lower plate 216. The formed passage may be configured to allow fluid to enter the volume 218 only through the lower plate 216 via the second fluid passage 221, and the first fluid passage 219 may be fluidly isolated from the volume 218 between the plates and the second fluid passage 221. Fluid access to the volume 218 is possible through the sides of the spray head 225.

[0042] Figure 3 This is a bottom view of a spray head 325 used with a processing chamber 325 according to an embodiment. The spray head 325 may correspond to... Figure 2A The spray head 225 is shown in the figure. The through-hole 365, showing a view of the first fluid channel 219, can have various shapes and configurations to control and influence the flow of the precursor through the spray head 225. The small holes 375, showing a view of the second fluid channel 221, can be distributed substantially uniformly across the surface of the spray head, even between the through-holes 365, and compared to other configurations, the small holes can help provide a more uniform mixing of the precursor as it leaves the spray head.

[0043] The chambers discussed earlier can be used in exemplary methods that include etching methods. (Go to...) Figure 4 This illustrates exemplary operations in method 400 according to an embodiment of the present technology. Before starting the method, method 400 may include one or more operations, including front-end processing, deposition, etching, polishing, cleaning, or any other operations that may be performed prior to said operations. The method may include some optional operations that may or may not be specifically related to some embodiments of the method according to the present technology. For example, many operations are described to provide a broader range of processes performed, but are not critical to the technology or may be performed by alternative methods discussed further below. Method 400 may be described in... Figures 5A-5B The operations illustrated in the figures are described in conjunction with the operation of method 400. It should be understood that the figures only illustrate partial schematic diagrams, and the substrate may contain any number of additional materials and features having the various features and aspects illustrated in the figures.

[0044] Method 400 may or may not involve optional operations to develop a semiconductor structure into a specific manufacturing operation. It should be understood that any number of such operations are possible. Figure 5AMethod 400 is performed on a semiconductor structure or substrate 505 illustrated in the figure, including an exemplary structure on which oxide removal operations can be performed. The exemplary semiconductor structure may include trenches, vias, or other recessed features that may include one or more exposed materials. For example, the exemplary substrate may contain silicon or some other semiconductor substrate material and an interlayer dielectric material through which recesses, trenches, vias, or isolation structures may be formed. The material exposed at any point during the etching process may be or include metallic materials, one or more dielectric materials, contact materials, transistor materials, or any other material that may be used in the semiconductor processing.

[0045] For example, Figure 5A The illustrated contact area of ​​the 3D NAND gate structure is offset laterally from the memory cell area. The substrate 505 may illustrate a dielectric material covering one or more other structures on the substrate, and it is to be understood that any number of materials may be formed beneath the illustrated structure. In some embodiments, the dielectric material may be or include silicon oxide, or any other oxide or nitride that can be patterned therethrough. Contact openings 510 may be defined by the substrate 505, and in some embodiments, contact openings 510 may have been formed by reactive ion etching or other patterning processes. Although only a single opening 510 is shown, it is to be understood that any number of openings may be formed, such as creating contact step structures or other contact patterns through the dielectric. Openings may be formed to the level of an extension of a metal or conductive material 515, which may be an extension of a memory word line forming a step structure from which cell electrical contacts can be formed. The conductive material 515 may be any number of metals or conductive materials, and may be tungsten, cobalt, copper, or any other material used for conductive coupling. As previously explained, due to one or more prior operations, a certain amount of oxide 520 may be formed as a platform covering the conductive material 515. If left on the conductive material, subsequent contact metal deposition may create increased resistance between the contact metal and the word line extension, which could affect device performance.

[0046] It should be understood that the described structures are not limiting and similarly encompass any of a variety of other semiconductor structures including tungsten-containing materials or other metallic materials. Other exemplary structures may include two-dimensional and three-dimensional structures common in semiconductor manufacturing, and in which the removal of tungsten-containing materials, such as tungsten oxide, relative to one or more other materials will be possible, as this technique can selectively remove the tungsten-containing material relative to other exposed materials (such as silicon-containing materials) and any other materials discussed elsewhere. Furthermore, while high aspect ratio structures may benefit from this technique, it is equally applicable to lower aspect ratio and any other structures.

[0047] For example, layers of material according to this technology can be characterized by any aspect ratio or height-to-width ratio of the structure. Although in some embodiments the material can be characterized by a larger aspect ratio, this larger aspect ratio may not allow for adequate etching using conventional techniques or methods. For example, in some embodiments, the aspect ratio of any layer of the exemplary structure can be greater than or about 10:1, greater than or about 20:1, greater than or about 30:1, greater than or about 40:1, greater than or about 50:1, or greater. Furthermore, the layers can be characterized by reduced widths or thicknesses of less than or about 100 nm, less than or about 80 nm, less than or about 60 nm, less than or about 50 nm, less than or about 40 nm, less than or about 30 nm, less than or about 20 nm, less than or about 10 nm, less than or about 5 nm, less than or about 1 nm, or even smaller, including any fraction of any described number, such as 20.5 nm, 1.5 nm, etc. This combination of high aspect ratio and minimum thickness can frustrate many conventional etching operations or require substantially longer etching times to remove layers across a limited width along vertical or horizontal distances. Additionally, as previously explained, conventional techniques may damage or remove other exposed layers.

[0048] In one embodiment, method 400 may be performed to remove exposed tungsten-containing material, although in embodiments of the art any number of oxides or tungsten-containing materials may be removed from any number of structures. The method may include specific operations for the removal of tungsten oxide. While the remainder of the disclosure will generally discuss tungsten oxide, it is to be understood that other metal oxides may be similarly processed by some embodiments of the art. In some embodiments, the method may include a multi-operation etching process that controls the etching of tungsten relative to other exposed materials (such as dielectric materials, e.g., silicon oxide) and the underlying contact material (such as tungsten used in the structure or some other conductive material).

[0049] Method 400 may include, in operation 405, flowing a halogen-containing precursor, including a first halogen-containing precursor, into a semiconductor processing chamber housing the described substrate or some other substrate. The halogen-containing precursor may flow through a remote plasma region of the processing chamber (such as region 215 described above), and plasma may be formed by the halogen-containing precursor to generate a plasma effluent. While substrate-level plasma may be generated, in some embodiments, the plasma may be a remote plasma, which may protect exposed substrate material from ion bombardment that may occur due to substrate-level plasma. In operation 410, the plasma effluent of the halogen-containing precursor may be delivered to a substrate processing region, and in operation 415, the effluent may contact a semiconductor substrate including exposed tungsten-containing material in the substrate processing region. Contact with a fluorinated material, such as tungsten fluoride oxyfluoride or tungsten oxide halide material, such as by converting exposed tungsten oxide on the substrate. In some embodiments, after fluorination, the plasma may be extinguished, and the chamber may be cleaned.

[0050] Following the fluorination operation, in operation 420, an etchant precursor may flow into the processing area. In some embodiments, the etchant precursor may be a second halogen-containing precursor and may include the same or different halogen as the first halogen-containing precursor. The etchant precursor may interact with tungsten oxide or other oxide materials to produce tungsten and / or oxygen byproducts that are volatile under processing conditions and can be released from the substrate. Therefore, in operation 425, the etchant precursor may contact the fluorinated material, which may etch or remove the tungsten oxide material from the underlying metal. Figure 5B As described, the removal of oxide material can expose the contact surface of the contact material at the bottom of the formed hole or trench.

[0051] In some embodiments, the second precursor may not be plasma-enhanced, and in some embodiments, the semiconductor processing chamber may be maintained plasma-free during operation and delivery using the second halogen precursor. Plasma-free removal can be performed by utilizing a special precursor and performing etching under specific processing conditions, and the removal can also be dry etching. Therefore, techniques according to aspects of this technology can be performed to remove tungsten oxide from narrow features, high aspect ratio features, and thin dimensions that would not otherwise be suitable for wet etching or reactive ion etching.

[0052] In some embodiments, during each of the two-step operations, the precursor may include a halogen-containing precursor and may include one or more of fluorine or chlorine. Some exemplary precursors that may be used as the first precursor may include halides, including hydrogen fluoride, nitrogen trifluoride, or any organofluorine compound. Various combinations may also be used to flow the precursors together. In some embodiments, in the first operation, nitrogen trifluoride or some other fluorine-containing precursor may be delivered to a remote plasma region using hydrogen and the nitrogen trifluoride or some other fluorine-containing precursor may be plasma-enhanced to produce a fluorinated surface of tungsten oxide. The etchant precursor used as the second halogen precursor may be or include a chlorine-containing precursor, such as boron trichloride, or any other chlorine material. Under the processing conditions of this technology, boron trichloride may promote the formation of volatile byproducts of fluorinated tungsten oxide that can be removed. For example, some byproducts may include tungsten oxychloride or tungsten pentachloride, which may be volatile at the processing temperature, facilitating material removal from the substrate.

[0053] Processing conditions can influence and promote etching according to this technology. Because the etching reaction can be based on the thermal decomposition of the halogen for a second reaction between the second halogen precursor and the fluorinated oxide material, the temperature can depend at least in part on the particular halogen or precursor to initiate decomposition. For example, etching can begin or increase when the temperature increases to above or about 100°C or above or about 150°C, which can indicate the decomposition of the precursor and / or activation of the reaction with fluorinated tungsten oxide. Further increases in temperature can further promote decomposition and, consequently, the reaction with fluorinated tungsten oxide.

[0054] Therefore, in some embodiments of this technology, etching methods can be performed at substrate, base, and / or chamber temperatures above or about 100°C, and at temperatures above or about 150°C, above or about 200°C, above or about 250°C, above or about 300°C, above or about 350°C, above or about 400°C, above or about 450°C, or higher. Temperatures can also be maintained within these ranges, within a smaller range encompassed by these ranges, or at any temperature between any of these ranges. In some embodiments, the method can be performed on a substrate that may have some of the resulting characteristics, which can generate a thermal budget. Therefore, in some embodiments, the method can be performed at temperatures below or about 800°C, and at temperatures below or about 750°C, below or about 700°C, below or about 650°C, below or about 600°C, below or about 550°C, below or about 500°C, or lower.

[0055] The pressure within the chamber can also affect the performed operation and the temperature at which halogens decompose from the transition metal. To facilitate fluorination based on plasma-enhanced precursors, the processing pressure can be lower than the pressure in the second removal operation. Maintaining a lower pressure in the first operation, such as during the use of a first halogen precursor, can promote increased interactions at the substrate surface. Lower pressure in the first part of the method can increase the mean free path between atoms, which can increase energy and interactions at the film surface. By utilizing higher pressure in the second part of the method, such as during the use of a second halogen precursor, the etching rate can be increased. Therefore, in some embodiments, during the first part of etching (such as during operations 405-415), the pressure can be maintained below about 20 Torr, and the pressure can be maintained below or about 15 Torr, below or about 10 Torr, below or about 9 Torr, below or about 8 Torr, below or about 7 Torr, below or about 6 Torr, below or about 5 Torr, below or about 4 Torr, below or about 3 Torr, below or about 2 Torr, below or about 1 Torr, below or about 0.5 Torr, or lower. During the second part of the method (such as during operations 420-425), the pressure may then be increased, wherein the pressure may be maintained at a pressure greater than or about 1 Torr, and may be maintained at a pressure greater than or about 5 Torr, greater than or about 10 Torr, greater than or about 15 Torr, greater than or about 20 Torr, greater than or about 25 Torr, greater than or about 30 Torr, greater than or about 35 Torr, greater than or about 40 Torr, greater than or about 45 Torr, greater than or about 50 Torr, greater than or about 75 Torr, greater than or about 100 Torr, or higher, which may extend upwards to atmospheric pressure, although in some embodiments vacuum conditions may facilitate operation. The pressure may also be maintained within these ranges, within a smaller range encompassed by these ranges, or between any of these ranges.

[0056] As previously noted, in some embodiments, hydrogen may be delivered using nitrogen trifluoride or a first halogen precursor. By including hydrogen, the etching rate of the material from fluorine can be reduced or suppressed during fluorination. To protect the dielectric material that can form holes or trenches through it, and to protect the metal beneath the oxide material, hydrogen may be delivered at a flow rate greater than that of the first halogen precursor. For example, in some embodiments where the first halogen precursor may be nitrogen trifluoride, the hydrogen to nitrogen trifluoride flow rate ratio may be greater than or about 1.5:1, and may be greater than or about 2.0:1, greater than or about 2.5:1, greater than or about 3.0:1, greater than or about 3.5:1, greater than or about 4.0:1, greater than or about 4.5:1, greater than or about 5.0:1, greater than or about 10.0:1, or higher. Hydrogen radicals can help passivate other exposed material, while fluorine interacts with the oxide material at the bottom of the trench or feature.

[0057] Further control is added to the etching process. In some embodiments, the halogen-containing precursor can be pulsed, and the halogen-containing precursor can be delivered continuously or in a series of pulses throughout the etching process. The pulses can be uniform or vary over time. Pulsed delivery is characterized by a first time period during which the halogen-containing precursor flows, and a second time period during which the halogen-containing precursor is paused or stopped. The time periods used for any pulsed operation can be similar or different from each other, with any one time period being longer. In embodiments, the time period of precursor flow or continuous flow can be performed for a duration greater than or approximately 1 second, and can be greater than or approximately 2 seconds, greater than or approximately 3 seconds, greater than or approximately 4 seconds, greater than or approximately 5 seconds, greater than or approximately 6 seconds, greater than or approximately 7 seconds, greater than or approximately 8 seconds, greater than or approximately 9 seconds, greater than or approximately 10 seconds, greater than or approximately 11 seconds, greater than or approximately 12 seconds, greater than or approximately 13 seconds, greater than or approximately 14 seconds, greater than or approximately 15 seconds, greater than or approximately 20 seconds, greater than or approximately 30 seconds, greater than or approximately 45 seconds, greater than or approximately 60 seconds, or longer. The time can also be any smaller range encompassed by any of these ranges. In some embodiments, the etching rate can be increased because the transport of the precursor occurs over a longer period of time.

[0058] By performing operations according to embodiments of the present technology, tungsten oxide or other oxide materials can be selectively etched relative to other materials including other oxides. For example, the present technology can selectively etch tungsten oxide relative to metal-exposed areas, dielectrics including silicon-containing materials (silicon-containing materials include silicon oxide), or other materials. Embodiments of the present technology can etch tungsten oxide or other metal oxides relative to any of silicon oxide, silicon nitride, tungsten, or other materials at a rate of at least about 100:1, and can etch tungsten oxide relative to any of silicon oxide, silicon nitride, tungsten, or other previously specified materials at a selectivity greater than or about 200:1, greater than or about 300:1, greater than or about 400:1, greater than or about 500:1, greater than or about 1,000:1, or higher. For example, etching performed according to some embodiments of the present technology can etch tungsten oxide while substantially or substantially maintaining silicon oxide, silicon nitride, tungsten, or other materials.

[0059] The previously discussed methods allow for the removal of tungsten oxide or other oxide materials relative to some other exposed materials. Improved tungsten oxide etching can be performed by utilizing the previously described multi-precursor etchant treatment, which increases both selectivity and etching access in fine-pitch features compared to conventional techniques.

[0060] In the preceding description, numerous details have been set forth for illustrative purposes to provide an understanding of various embodiments of the present technology. However, it will be apparent to those skilled in the art that some of these details may not be necessary, or may require additional details, to practice certain embodiments.

[0061] Several embodiments have been disclosed, and those skilled in the art will recognize that various modifications, alternative constructions, and equivalents can be used without departing from the spirit of the embodiments. Furthermore, some well-known processes and elements have not been described to avoid unnecessarily obscuring the technology. Therefore, the above description should not be considered as limiting the scope of the technology. Additionally, methods or processes may be described as sequential or step-by-step, but it is to be understood that operations may be performed simultaneously or in a different order than shown.

[0062] When a numerical range is provided, unless otherwise clearly indicated herein, it is to be understood that each intermediate value between the upper and lower limits of the range is also specifically disclosed, down to the minimum fraction of the unit to the lower limit. This encompasses a narrower range between any described or undescribed intermediate values ​​within the described range, as well as any other described or intermediate values ​​within that range. The upper and lower limits of those smaller ranges may be independently included in or excluded from the range, and each range wherein neither the upper nor lower limit is excluded from, nor includes, is also covered by this technique, subject to any specific exclusions within the described range. Where the described range includes one or both of the upper and lower limits, ranges excluding either or both of the included upper and lower limits are also included.

[0063] As used herein and in the appended claims, the singular forms “a (or an)” and “the” include plural references unless otherwise clearly indicated herein. Thus, for example, a reference to “a precursor” includes a plurality of such precursors, and a reference to “the layer” includes a layer or multiple layers, as well as equivalents known to those skilled in the art, and so on.

[0064] Furthermore, when the terms “comprise(s) or comprising,” “contain(s) or containing,” and “include(s) or including” are used in this specification and the appended claims, they are intended to indicate the presence of the described features, integers, components, or operations, but do not preclude the presence or addition of one or more other features, integers, components, operations, actions, or groups.

Claims

1. An etching method, comprising: The halogen-containing precursor is flowed into a remote plasma region of the semiconductor processing chamber, and the plasma is excited to generate plasma effluent. A substrate contained in a processing area is brought into contact with the plasma effluent, wherein the substrate defines an exposed area of ​​tungsten oxide, and wherein the contact produces tungsten fluoride oxyfluoride material; Increase the pressure in the semiconductor processing chamber; The etchant precursor is allowed to flow into the processing area; Contact the tungsten fluoride oxyfluoride material with the etchant precursor; and Remove the fluorinated tungsten material.

2. The etching method of claim 1, wherein the halogen-containing precursor comprises fluorine, and wherein the etchant precursor comprises a chlorine-containing precursor.

3. The etching method of claim 2, wherein the halogen-containing precursor comprises nitrogen trifluoride, and the method further comprises: Hydrogen flow is achieved using the halogen-containing precursor.

4. The etching method of claim 3, wherein the flow rate of hydrogen is at least twice the flow rate of the halogen-containing precursor.

5. The etching method of claim 1, wherein the semiconductor processing chamber is maintained as plasma-free during the flow of the etchant precursor.

6. The etching method of claim 1, wherein the etching method is performed at a temperature greater than or equal to 150°C.

7. The etching method of claim 1, wherein the pressure in the semiconductor processing chamber is maintained at less than or equal to 15 Torr while the halogen-containing precursor is flowing.

8. The etching method of claim 7, wherein the pressure in the semiconductor processing chamber is maintained at or above 15 Torr while the etchant precursor is flowing.

9. The etching method of claim 1, wherein the substrate may further include an exposed area of ​​silicon oxide.

10. The etching method of claim 9, wherein trenches are formed through the silicon oxide to define the exposed area of ​​the tungsten oxide.

11. An etching method, comprising: The plasma that forms the first halogen-containing precursor generates plasma effluent in a remote plasma region of the semiconductor processing chamber; The plasma effluent is then directed to the processing area of ​​the semiconductor processing chamber, which is under a first pressure. A substrate housed in the processing area is brought into contact with the plasma effluent, wherein the substrate includes an exposed area of ​​tungsten oxide that covers a tungsten region at the bottom of a trench defined in the substrate, and wherein the plasma effluent halogenates the tungsten oxide. The second halogen-containing precursor is allowed to flow into the processing region of the semiconductor processing chamber at a second pressure, wherein the second pressure is greater than the first pressure; as well as Remove halogenated tungsten oxide.

12. The etching method of claim 11, wherein the first halogen-containing precursor comprises fluorine, and wherein the second halogen-containing precursor comprises boron trichloride.

13. The etching method of claim 11, further comprising stopping plasma formation before allowing the second halogen-containing precursor to flow.

14. The etching method of claim 11, wherein the first halogen-containing precursor comprises nitrogen trifluoride, the method further comprising: Hydrogen flows using the first halogen-containing precursor.

15. The etching method of claim 14, wherein the flow rate of hydrogen is at least twice the flow rate of the first halogen-containing precursor.

16. The etching method of claim 11, wherein the pressure in the semiconductor processing chamber is maintained at less than or equal to 15 Torr while the first halogen-containing precursor is flowing.

17. The etching method of claim 16, wherein the pressure in the semiconductor processing chamber is maintained at or above 15 Torr while the second halogen-containing precursor is flowing.

18. An etching method, comprising: Plasma containing fluorine precursors is formed to generate plasma effluent in a remote plasma region of the semiconductor processing chamber; The plasma effluent is then directed to the processing area of ​​the semiconductor processing chamber. A substrate contained in the processing area is brought into contact with the plasma effluent, wherein the substrate includes an exposed area of ​​tungsten oxide covering a tungsten region, and wherein the plasma effluent fluorinates the tungsten oxide; Increase the pressure in the semiconductor processing chamber; The chlorine-containing precursor is allowed to flow into the processing area of ​​the semiconductor processing chamber; Contact the substrate with the chlorine-containing precursor; and Remove the tungsten oxide.

19. The etching method of claim 18, further comprising: Hydrogen is flowed using the fluorinated precursor, wherein the flow rate of the hydrogen is at least twice the flow rate of the fluorinated precursor.

20. The etching method of claim 18, wherein the pressure in the semiconductor processing chamber is maintained at less than or equal to 10 Torr while the fluorine-containing precursor is flowing, and wherein the pressure in the semiconductor processing chamber is maintained at more than or equal to 20 Torr while the chlorine-containing precursor is flowing.

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