Semiconductor devices and power equipment

Abstract

A concentrated semiconductor device capable of reducing hole current on the surface side is provided. The semiconductor device (100) according to this disclosure includes a buffer layer (14) of a first conductivity type, a surface region (10a) on the surface side of the buffer layer (14), and a back side region (10b) on the back side side of the buffer layer (14). A collector layer (11) of a second conductivity type formed in the back side region (10b) has a first collector layer (P1) and a second collector layer (P2) having an impurity concentration lower than that of the first collector layer (P1) that are alternately formed. The surface region (10a) includes a first surface region (1a) located above the first collector layer (P1) and a second surface region (1b) located above the second collector layer (P2). In the first surface region (1a), a hole discharge promoting structure (110) is formed that promotes the discharge of holes from the upper part of the first collector layer (P1) compared to the case where the structure of the first surface region (1a) is the same as the structure of the second surface region (1b).

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a power equipment, and more particularly to an insulated gate bipolar transistor (IGBT) and a power conversion device using the IGBT. Background Technology

[0002] In recent years, IGBTs have been widely used in household appliances such as air conditioners and refrigerators, which promote energy saving and miniaturization, as well as in railway inverters and motor control for industrial robots. In particular, in order to reduce losses in power equipment for high-frequency applications (such as power conversion devices), it is necessary to reduce the turn-off losses of IGBTs.

[0003] To reduce the turn-off loss of IGBTs, it is preferable to reduce the concentration of the p-collector layer on the back side to decrease the amount of holes injected from the back side. However, if the concentration of the p-collector layer is too low, it will impair the ohmic performance of the back electrode, resulting in a significant increase in turn-off loss.

[0004] Therefore, for example, Patent Document 1 discloses that p is formed on the back side of the IGBT. + p-type collector layer and p-type - p type - IGBT with collector layer.

[0005] Furthermore, Patent Document 2 discloses forming p on the back side of the IGBT. + p-type collector layer and p-type - p type - An IGBT with a collector layer and no n-type source layer in the region where a p-type collector layer is provided.

[0006] The back side is formed with a p-collector layer and a p-concentration lower than that of the p-collector layer, as disclosed in Patent Documents 1 and 2. - IGBTs with collector layers can suppress hole injection to achieve low hole injection, thus reducing turn-off losses without compromising ohmic performance.

[0007] Patent Document 1: Japanese Patent No. 4566470

[0008] Patent Document 2: Japanese Patent Application Publication No. 2018-49866 Summary of the Invention

[0009] The problem the invention aims to solve

[0010] However, the inventors of this disclosure have discovered the following phenomenon: In the IGBTs with collector layers disclosed in the prior art, due to the flow from the p collector layer and p... -The difference in hole injection amount between the collector layer and the emitter layer results in a greater accumulation of holes on the surface side of the p-collector layer during turn-off. This leads to a concentration of hole current with a higher density, and the discharge of holes from this concentration point to the emitter electrode is delayed, thus increasing turn-off losses. In particular, the inventors of this disclosure have discovered that a p-collector layer and a p-collector layer... - The larger the spacing of the collector layer pattern, the more significant this phenomenon becomes. For example, in the 1200V withstand voltage category, this phenomenon is more likely to occur when the spacing is above 20μm, and the effect is more significant when it is above 50μm.

[0011] On the other hand, in making p - Increasing the concentration of the collector layer to reduce the amount of electricity generated from the p-collector layer and p-collector layer. - The difference in hole injection amount in the collector layer leads to an increase in turn-off loss.

[0012] To simultaneously achieve low hole injection and low turn-off losses, it is necessary to improve the concentration of hole current on the surface side where holes are discharged. Previous technologies have encountered the problem of being unable to reduce the concentration of hole current to achieve a uniform hole current density distribution.

[0013] This disclosure was made to solve the problems described above, and to obtain a p-collector layer with a lower concentration of p-collector layer on the back side. - Semiconductor devices and power equipment using the same semiconductor device are constructed to improve the concentration of hole current on the surface side above the p-collector layer.

[0014] Solution for solving the problem

[0015] The semiconductor device disclosed herein includes: a buffer layer of a first conductivity type; a surface region on a side closer to the surface of the buffer layer; and a back surface region on a side closer to the back surface of the buffer layer. The surface region has: a drift layer of a first conductivity type formed on the buffer layer; a base layer of a second conductivity type formed on the drift layer; a source layer of a first conductivity type and a contact layer of a second conductivity type formed on the base layer and adjacent to each other; a plurality of trench gates formed in a manner that penetrates the source layer, the contact layer, and the base layer and extends to the drift layer, and are spaced apart from each other; an emitter contact layer formed on the source layer and the contact layer; and an emitter electrode formed on the emitter contact layer. The back surface region has: a second conductivity type and a back surface region. An electrical type collector layer is formed beneath a buffer layer; and a collector electrode is formed beneath the collector layer. The collector layer has alternating first collector layers and second collector layers with impurity concentrations lower than those of the first collector layers. The surface region includes a first surface region above the first collector layer and a second surface region above the second collector layer. The second surface region has a different structure from the first surface region. In the first surface region, a hole discharge promoting structure is formed, which promotes the discharge of holes from the upper part of the first collector layer compared to the case where the structure of the first surface region is the same as that of the second surface region.

[0016] The power equipment involved in this disclosure has the semiconductor device involved in this disclosure.

[0017] The effects of the invention

[0018] According to the semiconductor device disclosed herein, a first collector layer serving as a p-collector layer and a p-collector layer having an impurity concentration lower than that of the first collector layer are formed. - The second collector layer of the collector layer, constituting a second conductivity type collector layer, has a corresponding hole discharge promotion structure. Therefore, compared to the case where the structure of the first surface region is the same as that of the second surface region, hole discharge above the first collector layer is promoted. As a result, the delay in hole discharge caused by the concentration of hole current above the first collector layer can be reduced, and the turn-off loss in the concentrated hole current area can be reduced.

[0019] The power equipment disclosed herein incorporates the semiconductor device disclosed herein, thereby enabling improved loss reduction. Attached Figure Description

[0020] Figure 1 This is a cross-sectional perspective view showing the structure of the semiconductor device involved in Embodiment 1.

[0021] Figure 2This is a cross-sectional view showing the structure of the semiconductor device involved in Embodiment 1.

[0022] Figure 3 This is a plan view illustrating an example of the layout of the collector layer and hole discharge promotion structure of the semiconductor device according to Embodiment 1.

[0023] Figure 4 This is a plan view illustrating an example of the layout of the collector layer and hole discharge promotion structure of the semiconductor device according to Embodiment 1.

[0024] Figure 5 This is a plan view illustrating an example of the layout of the collector layer and hole discharge promotion structure of the semiconductor device according to Embodiment 1.

[0025] Figure 6 This is a cross-sectional view showing the structure of the semiconductor device involved in a variation of Embodiment 1.

[0026] Figure 7 This is a cross-sectional view showing the structure of the semiconductor device involved in a variation of Embodiment 1.

[0027] Figure 8 This is a cross-sectional view showing the structure of the semiconductor device involved in Embodiment 2.

[0028] Figure 9 This is a cross-sectional view showing the structure of the semiconductor device involved in the modified example of Embodiment 2.

[0029] Figure 10 This is a cross-sectional view showing the structure of the semiconductor device involved in Embodiment 3.

[0030] Figure 11 This is a cross-sectional view showing the structure of the semiconductor device involved in Embodiment 4.

[0031] Figure 12 This is a block diagram that schematically represents the structure of a power conversion system using the power conversion device described in Embodiment 5.

[0032] (Explanation of reference numerals in the attached diagram)

[0033] 1a: First surface region; 1b: Second surface region; 10a: Surface region; 10b: Back surface region; 11, 11a, 11b, 11c: Collector layer; 12: Drift layer; 14: Buffer layer; 18: Source layer; 20: Contact layer; 22: Base layer; 22b: Deep base layer; 24: Carrier accumulation layer; 24a: First carrier accumulation layer; 24b: Second carrier accumulation layer; 26: Insulating film; 28: Conductor; 42: Interlayer insulating film; 44: Emitter contact layer; 46: Emitter electrode; 50: Gate electrode; 51a: First collector region; 51b: Second collector region; 90: Trench gate; 95: Bottom layer; 99: Sidewall layer; 100, 101, 102, 200, 201, 300, 400: Semiconductor device; 110, 110a, 110b, 110c, 111, 112, 210, 211, 310, 410: Hole ejection facilitator structure; 1000: Power supply; 2000: Power conversion device; 2001: Main conversion circuit; 2002: Drive circuit; 2003: Control circuit; 3000: Load Detailed Implementation

[0034] The embodiments of this disclosure will now be described with reference to the figures. Furthermore, in the following embodiments, the same reference numerals are used for the same structural elements.

[0035] Implementation method 1.

[0036] In the following description, regarding the conductivity type of impurities, n-type is defined as "first conductivity type" and p-type is defined as "second conductivity type", but these conductivity types can be interchanged.

[0037] Figure 1 This is a cross-sectional perspective view showing a portion of the semiconductor device 100 according to Embodiment 1. Figure 2 This is a cross-sectional view showing a portion of the semiconductor device 100 according to Embodiment 1. The semiconductor device 100 is an IGBT.

[0038] like Figure 1 and Figure 2 As shown, the semiconductor device 100 has a buffer layer 14 of a first conductivity type, a surface region 10a on the surface side of the buffer layer 14, and a back surface region 10b on the back surface side of the buffer layer.

[0039] Surface region 10a has: a drift layer 12 of a first conductivity type formed on buffer layer 14; a base layer 22 of a second conductivity type formed on drift layer 12; a source layer 18 of a first conductivity type and a contact layer 20 of a second conductivity type formed on base layer 22 and adjacent to each other; a plurality of trench gates 90 formed in such a way that they penetrate source layer 18, contact layer 20 and base layer 22 and reach drift layer 12, and extend spaced apart from each other; an emitter contact layer 44 formed on source layer 18 and contact layer 20; and an emitter electrode 46 formed on emitter contact layer 44.

[0040] The back surface region 10b has a collector layer 11 of a second conductivity type formed under the buffer layer 14 and a collector electrode 40 formed under the collector layer 11.

[0041] The collector layer 11 has a first collector layer P1 formed alternately and a second collector layer P2 having an impurity concentration lower than that of the first collector layer P1.

[0042] In embodiment 1, the buffer layer 14 of the first conductivity type is an n-type buffer layer. The drift layer 12 of the first conductivity type is an n-type buffer layer. - The drift layer is of the second conductivity type. The base layer 22 is a P-type base layer. The source layer 18 is an n-type source layer. + The source layer is of the p-type conductivity. The second conductivity type contact layer 20 is p-type. + Type of contact layer.

[0043] In the collector layer 11 of the second conductivity type formed beneath the buffer layer 14, the first collector layer P1 is a p-type p-collector layer, and the second collector layer P2 is a p-type p-collector layer. - p type - Collector layer.

[0044] n + Impurities of type n are present at a higher concentration compared to type n; impurities of type n are present at a higher concentration than those of type n. - Compared to other types, it contains a high concentration.

[0045] p + Impurities of type 1 are present at a higher concentration compared to type 2, while those of type 2 are present at a higher concentration. - Compared to other types, it contains a high concentration.

[0046] exist Figure 1 In the diagram, the x-direction is the extension direction of the trench gate 90. The z-direction, orthogonal to the x-direction, is the arrangement direction of the trench gate 90, which is orthogonal to the extension direction of the trench gate 90. The y-direction, orthogonal to both the x-direction and the z-direction, is the stacking direction of the semiconductor device 100.

[0047] Figure 2This is a cross-sectional view of the semiconductor device 100 in the yz direction, which is perpendicular to the x direction, which is the extension direction of the trench gate 90.

[0048] Additionally, in the following explanation, Figure 1 The positive y-direction is defined as the upward direction and the surface side direction, while the negative direction is defined as the downward direction and the back side direction, for explanation purposes.

[0049] In addition, such as Figure 1 and Figure 2 As shown, in the semiconductor device 100, the trench gate 90 is formed by forming a strip-shaped trench that penetrates the source layer 18 and the base layer 22 and reaches the drift layer 12, and then filling it with a conductor 28 after forming an insulating film 26 on the wall surface of the trench.

[0050] In addition, such as Figure 1 As shown, the semiconductor device 100 has an interlayer insulating film 42 formed on the contact layer 20 and the source layer 18.

[0051] The emitter contact layer 44 is formed in the opening disposed in the interlayer insulating film 42 and is in contact with the contact layer 20 and the source layer 18.

[0052] The emitter electrode 46, which is in contact with the emitter contact layer 44, is formed on the interlayer insulating film 42.

[0053] In addition, Figure 1 In the diagram, the interlayer insulating film 42, the emitter contact layer 44, and the emitter electrode 46 extend in the negative x-direction to the dashed line 46a with the same structure. However, for the purpose of illustrating the structure of the trench gate 90, the contact layer 20, and the source layer 18, the portion indicated by the dashed line 46a is omitted. That is, the emitter contact layer 44 contacts the emitter electrode 46 above it and contacts the contact layer 20 and the source layer 18 below it.

[0054] As described above, in the semiconductor device 100 having a collector layer 11 having a first collector layer P1 and a second collector layer P2, holes accumulate more in the surface region 10a above the first collector layer P1 compared to the second collector layer P2, thus causing hole current to tend to concentrate. Consequently, due to the concentration of hole current above the first collector layer P1, hole discharge to the emitter electrode on the surface side is delayed, resulting in increased turn-off losses.

[0055] like Figure 2As shown, surface region 10a has a first surface region 1a located above the first collector layer P1 and a second surface region 1b located above the second collector layer P2. In order to improve the concentration of hole current in the first surface region 1a, the second surface region 1b has a different structure from the first surface region 1a with respect to surface region 10a.

[0056] In Embodiment 1, a hole discharge promoting structure 110 is formed, which promotes the discharge of holes from the upper part of the first collector layer P1 compared to the case where the structure of the first surface region 1a is the same as the structure of the second surface region 1b.

[0057] The hole discharge promoting structure in this disclosure refers to a structure that accelerates the discharge of holes above the first collector layer P1, thereby reducing the delay in hole discharge caused by the high density of hole current above the first collector layer P1, compared to the case where the structure of the first surface region 1a is the same as the structure of the second surface region 1b.

[0058] The hole discharge promoting structure 110 is constructed as follows: a first carrier accumulation layer 24a of a first conductivity type with a higher impurity concentration than the drift layer 12 is formed between the drift layer 12 and the base layer 22 in the second surface region 1b. In contrast, a first carrier accumulation layer 24a with a higher impurity concentration than the drift layer 12 is not formed between the drift layer 12 and the base layer 22 in the first surface region 1a.

[0059] The trench gate 90 in the first surface region 1a penetrates the source layer 18, the contact layer 20, and the base layer 22, and reaches the drift layer 12. The trench gate 90 in the second surface region 1b penetrates the source layer 18, the contact layer 20, the base layer 22, and the first carrier accumulation layer 24a, and reaches the drift layer 12.

[0060] Typically, the carrier accumulation layer acts as a barrier to holes, thus accumulating holes. The hole discharge promotion structure 110 in the semiconductor device 100 according to Embodiment 1 is a structure that utilizes the hole barrier effect of the first carrier accumulation layer 24a.

[0061] The first carrier accumulation layer 24a is a structure that suppresses the discharge of holes in the second surface region 1b. In contrast, in the first surface region 1a, the first carrier accumulation layer 24a is not provided between the drift layer 12 and the base layer 22, thus becoming a structure that does not suppress the discharge of holes. That is, the hole discharge promoting structure 110 formed in the first surface region 1a is a structure that promotes the discharge of holes above the first collector layer P1 and improves the delay of hole discharge compared to the case where the structure of the first surface region 1a is the same as the structure of the second surface region 1b.

[0062] Therefore, the concentration of hole current in the first surface region 1a can be improved, and the turn-off loss caused by the delay in hole discharge in the concentrated part of hole current can be reduced.

[0063] The impurity concentration of the first collector layer P1 only needs to be higher than that of the second collector layer P2, for example, 1×10 16 cm -3 Above and 1×10 18 cm -3 The impurity concentration of the second collector layer P2 only needs to be lower than that of the first collector layer P1, for example, 1×10⁻⁶. 15 cm -3 Above and 5×10 17 cm -3 the following.

[0064] In the collector layer 11, the spacing L0 of the pattern containing the first collector layer P1 and the second collector layer P2, obtained by adding the width L1 of the first collector layer P1 and the width L2 of the second collector layer P2, is, for example, 5 μm or more. Furthermore, a problem with this disclosure is that the concentration of hole current above the first collector layer P1 is more likely to occur on the surface side of the first collector layer P1 if the spacing L0 is larger; therefore, a spacing L0 of 20 μm or more is desirable.

[0065] Regarding the ratio of the width L1 of the first collector layer P1 to the width L2 of the second collector layer P2, i.e., L1:L2, a larger L2 relative to L1 is better at suppressing hole injection and reducing turn-off losses. Therefore, a larger L2 relative to L1 is desirable. For example, if L1:L2 is 0.4:0.6 or higher, a ratio of 0.1:0.9 or higher is desirable.

[0066] Next, use Figure 3 , Figure 4 , Figure 5 The present invention describes collector layers 11a, 11b, and 11c as examples of the patterns of the first collector layer P1 and the second collector layer P2 in the collector layers.

[0067] Figure 3 , Figure 4 , Figure 5 This is a plan view of a semiconductor device along the xz direction of the extension direction of the trench gate 90, showing an example layout of the collector layer and the hole discharge promotion structure corresponding to the collector layer in the semiconductor device involved in this disclosure.

[0068] exist Figure 3 , Figure 4 , Figure 5 In the middle, the x-direction is Figure 1The extension direction of the trench gate 90 is shown. The z-direction is the arrangement direction of the trench gate 90, which is orthogonal to the extension direction of the trench gate 90.

[0069] Figure 3 (a) is Figure 2 The plan view in the xz direction at the position of the dashed line AA shows the pattern of the layout of the first collector layer P1 and the second collector layer P2 in the collector layer 11a. Figure 3 (b) is Figure 2 The plan view in the xz direction at the position of the dashed line BB shows the pattern of the hole discharge promotion structure 110a disposed between the drift layer 12 and the base layer 22, corresponding to the layout of the collector layer 11a.

[0070] like Figure 3 As shown in (a), in the collector layer 11a, the first collector layer P1 and the second collector layer P2 are formed alternately in the z-direction. In this case, the spacing L0 of the pattern in the collector layer 11a in which the first collector layer P1 and the second collector layer P2 are arranged is... Figure 3 The length is obtained by adding the width L1 of the first collector layer P1 and the width L2 of the second collector layer P2 in the z direction.

[0071] Figure 3 The hole discharge promoting structure 110a shown in (b) has the following structure: a first carrier accumulation layer 24a is formed in the second surface region 1b above the second collector layer P2, whereas the first carrier accumulation layer 24a is not formed in the first surface region 1a above the first collector layer P1. That is, in Figure 3 In the plane at position BB shown in (b), the position corresponding to the second collector layer P2 is the first carrier accumulation layer 24a, and the position corresponding to the first collector layer P1 is the drift layer 12.

[0072] Figure 4 (a) is Figure 2 The plan view at the location of the dashed line AA shows the layout pattern of the first collector layer P1 and the second collector layer P2 in the collector layer 11b. Figure 4 (b) is Figure 2 The plan view in the xz direction at the position of the dashed line BB shows the pattern of the hole discharge promotion structure 110b disposed between the drift layer 12 and the base layer 22, corresponding to the layout of the collector layer 11b.

[0073] like Figure 4As shown in (a), the collector layer 11b is a pattern in which the first collector layer P1 and the second collector layer P2 are alternately formed in the x-direction. In this case, the spacing L0 of the pattern of the first collector layer P1 and the second collector layer P2 arranged in the collector layer 11b is [missing information]. Figure 4 The length is obtained by adding the width L1 of the first collector layer P1 and the width L2 of the second collector layer P2 in the x-direction shown.

[0074] Figure 4 The hole discharge promoting structure 110b shown in (b) has the following structure: a first carrier accumulation layer 24a is formed in the second surface region 1b above the second collector layer P2, whereas the first carrier accumulation layer 24a is not formed in the first surface region 1a above the first collector layer P1. That is, in Figure 4 In the plane at position BB shown in (b), the position corresponding to the second collector layer P2 is the first carrier accumulation layer 24a, and the position corresponding to the first collector layer P1 is the drift layer 12.

[0075] Figure 5 (a) is Figure 2 The plan view at the location of the dashed line AA shows the layout pattern of the first collector layer P1 and the second collector layer P2 in the collector layer 11c. Figure 5 (b) is Figure 2 The plan view in the xz direction at the position of the dashed line BB shows the hole discharge promotion structure 110c disposed between the drift layer 12 and the base layer 22, corresponding to the layout of the collector layer 11c.

[0076] like Figure 5 As shown in (a), the collector layer 11c has a first collector region 51a and a second collector region 51b that are alternately formed in the z direction. The first collector region 51a is a region in which the first collector layer P1 and the second collector layer P2 are alternately formed in the x direction. The second collector region 51b is a region in which only the second collector layer P2 is formed without the first collector layer P1.

[0077] In the collector layer 11c, the spacing L0 of the patterns of the first collector layer P1 and the second collector layer P2 is [missing information]. Figure 5 The length is obtained by adding the width L1 of the first collector layer P1 in the first collector region 51a in the z-direction to the width L2 of the second collector layer P2 in the second collector region 51b.

[0078] Figure 5 (b) and Figure 5 (a) corresponds to the first surface region 1a and the second surface region 1b in the plane where BB is located.

[0079] Figure 5 The hole discharge promotion structure 110c shown in (b) is as follows: a first carrier accumulation layer 24a is formed in the second surface region 1b above the second collector layer P2, whereas the first carrier accumulation layer 24a is not formed in the first surface region 1a above the first collector layer P1.

[0080] exist Figure 5 In the plane at position BB shown in (b), at the position corresponding to the first collector region 51a, the first surface region 1a and the second surface region 1b alternate in the x direction. The position corresponding to the second collector region 51b is the second surface region 1b.

[0081] That is, above the first collector region 51a, the drift layer 12 and the first carrier accumulation layer 24a are alternately formed in the x direction. Above the second collector region 51b, where only the second collector layer P2 is formed, only the first carrier accumulation layer 24a is formed.

[0082] Next, an example of a method for manufacturing the semiconductor device 100 according to Embodiment 1 will be described.

[0083] First, prepare a semiconductor substrate of the first conductivity type.

[0084] Next, an oxide film is formed on the upper surface of the semiconductor substrate as a mask, and a photoresist pattern is formed on the oxide film using photolithography. The oxide film is then etched using the photoresist pattern as a mask. Finally, the photoresist pattern is removed.

[0085] Next, a mask is used to inject phosphorus (P) ions to form a carrier accumulation layer of the first conductivity type.

[0086] Next, the mask is removed, a new mask is made, and boron (B) ions are injected.

[0087] Next, the injected phosphorus and boron are diffused through a drive. This forms a first carrier accumulation layer 24a of a first conductivity type and a base layer 22 of a second conductivity type.

[0088] The impurity concentration of the first carrier accumulation layer 24a only needs to be higher than that of the drift layer 12 and lower than that of the base layer 22. For example, it can be 1×10⁻⁶. 15 ~1×10 16 cm -3 The diffusion depth of the first carrier accumulation layer 24a is, for example, 1.0–3.0 μm. The surface concentration of the base layer 22 of the second conductivity type is, for example, 1 × 10⁻⁶. 17 ~1×10 18 cm -3The diffusion depth is, for example, 0.5–2.0 μm.

[0089] Next, arsenic (As) ions are implanted as impurities using a mask made of an oxide film, and the implanted arsenic diffuses through a push-well. Thus, a source layer 18 of the first conductivity type is formed on the base layer 22 of the second conductivity type. For example, the impurity concentration of the source layer 18 is, for example, 5 × 10⁻⁶. 18 ~5×10 19 cm -3 The diffusion depth is, for example, 0.5 μm.

[0090] Next, a trench gate 90 is formed. Regarding the trench gate 90, a mask consisting of an oxide film patterned in a manner connected to the gate electrode is used to form the trench by dry etching through the base layer 22 and the first carrier accumulation layer 24a. For example, the trench depth is 4.0–8.0 μm and the width is 0.5–2.0 μm.

[0091] Next, the oxide mask is removed to form an insulating film 26 that serves as the sidewall of the covering trench. Then, a conductive material 28, such as polysilicon, is filled into the trench covered by the insulating film 26.

[0092] Next, an interlayer insulating film 42, composed of an oxide film or the like, is formed to insulate the conductor 28 within the trench. The thickness of the interlayer insulating film 42 is, for example, 0.5 to 3.0 μm.

[0093] Next, an emitter contact layer 44 is formed using a mask made of an oxide film.

[0094] Next, an emitter electrode 46 is formed. The material of the emitter electrode 46 is, for example, aluminum or aluminum silicon. The film thickness of the emitter electrode 46 is, for example, 0.5 to 5.0 μm. In addition, a gate electrode 50 insulated from the emitter electrode 46 is formed.

[0095] Next, P ions and B ions are implanted on the lower surface of the semiconductor substrate to form a second collector layer P2 of the second conductivity type and a buffer layer 14 of the first conductivity type. Then, B ions are implanted on the lower surface of the semiconductor substrate 10 using a mask made of an oxide film to alternately form a first collector layer P1 of the second conductivity type with a higher concentration than the second collector layer P2. The first collector layer P1, the second collector layer P2, and the buffer layer 14 are formed by annealing.

[0096] Next, a collector electrode 40 is formed beneath the first collector layer P1 and the second collector layer P2. The material and film thickness of the collector electrode 40 can be set as needed.

[0097] Next, the narrative Figure 6The semiconductor device 101 and the modified example of Embodiment 1 shown herein Figure 7 The semiconductor device 102 involved in the modified embodiment 1 shown.

[0098] Figure 6 The structure of the semiconductor device 101 according to the modified example 1 of embodiment 1 is shown in the cross-sectional view of the semiconductor device 101 in the yz direction, which is perpendicular to the extension direction of the trench gate 90.

[0099] like Figure 6 As shown, in the surface region 10a of the semiconductor device 101 according to Variation 1 of Embodiment 1, the second surface region 1b located above the second collector layer P2 has a different structure than the first surface region 1a located above the first collector layer P1. In order to improve the concentration of hole current in the first surface region 1a, a hole discharge promoting structure 111 is formed.

[0100] A first carrier accumulation layer 24a of a first conductivity type with a higher impurity concentration than the drift layer 12 is formed between the drift layer 12 and the base layer 22 in the second surface region 1b. The hole discharge promotion structure 111 is constructed as follows: a second carrier accumulation layer 24b of a first conductivity type with a lower impurity concentration than the first carrier accumulation layer 24a and a higher impurity concentration than the drift layer 12 is formed between the drift layer 12 and the base layer 22 in the first surface region 1a.

[0101] Compared to the second carrier accumulation layer 24b in the first surface region 1a, the first carrier accumulation layer 24a in the second surface region 1b accumulates more holes to suppress hole discharge.

[0102] That is, the hole discharge promoting structure 111 formed on the first surface region 1a of the semiconductor device 101, like the hole discharge promoting structure 110, is a structure that promotes the discharge of holes above the first collector layer P1 to improve the delay of hole discharge compared to the case where the structure of the first surface region 1a is the same as the structure of the second surface region 1b.

[0103] Figure 7 The structure of the semiconductor device 102 according to the modified example 2 of embodiment 1 is shown in the cross-sectional view of the semiconductor device 102 in the yz direction, which is perpendicular to the extension direction of the trench gate 90.

[0104] like Figure 7As shown, in the surface region 10a of the semiconductor device 102 according to Variation 2 of Embodiment 1, the second surface region 1b located above the second collector layer P2 has a different structure than the first surface region 1a located above the first collector layer P1. To improve the concentration of hole current in the first surface region 1a, a hole discharge promoting structure 112 is formed. A first carrier accumulation layer 24a of a first conductivity type with a higher impurity concentration than the drift layer 12 is formed between the drift layer 12 and the base layer 22 in the second surface region 1b. The hole discharge promoting structure 112 is constructed such that a deep base layer 22b with a depth deeper than the base layer 22 on the drift layer 12 in the first surface region 1a is formed above the drift layer 12.

[0105] If the base layer of the first conductivity type is deep, the hole discharge effect is greater. Hole discharge is promoted by forming a deep base layer 22b in the first surface region 1a. On the other hand, the first carrier accumulation layer 24a in the second surface region 1b has the effect of accumulating holes to suppress hole discharge.

[0106] That is, the hole discharge promoting structure 112 formed on the first surface region 1a of the semiconductor device 102, like the hole discharge promoting structure 110, is a structure that promotes the discharge of holes above the first collector layer P1 to improve the delay of hole discharge compared to the case where the structure of the first surface region 1a is the same as the structure of the second surface region 1b.

[0107] According to the semiconductor device of Embodiment 1, the hole discharge promotion structure that improves the concentration of hole current in the first surface region 1a is configured as follows: a first carrier accumulation layer 24a with a higher impurity concentration than the drift layer 12 is formed between the drift layer 12 and the base layer 22 in the second surface region 1b. In contrast, the first carrier accumulation layer 24a is not formed between the drift layer 12 and the base layer 22 in the first surface region 1a. Therefore, compared with the case where the structure of the first surface region 1a is the same as the structure of the second surface region 1b, hole discharge above the first collector layer P1 is promoted. As a result, the delay in hole discharge caused by the concentration of hole current above the first collector layer P1 can be reduced, and the turn-off loss in the concentrated hole current area can be reduced.

[0108] Implementation method 2.

[0109] In Embodiment 2, the same reference numerals are used for structural elements that are the same as those in Embodiment 1 of this disclosure, and descriptions of the same or corresponding parts are omitted. Hereinafter, the semiconductor device 200 according to Embodiment 2 and the semiconductor device 201 according to a variation of Embodiment 2 will be described with reference to the figures.

[0110] Figure 8 The structure of the semiconductor device 200 according to Embodiment 2 is shown in a cross-sectional view of the semiconductor device 200 in the yz direction, which is perpendicular to the extension direction of the trench gate 90.

[0111] like Figure 8 As shown, in the surface region 10a of the semiconductor device 200, both the first surface region 1a and the second surface region 1b have a carrier accumulation layer 24 of a first conductivity type with an impurity concentration higher than that of the drift layer 12 between the drift layer 12 and the base layer 22.

[0112] In the semiconductor device 200 according to Embodiment 2, a hole discharge promoting structure 210 is formed in the first surface region 1a. The hole discharge promoting structure 210 is a structure that promotes the discharge of holes from the upper part of the first collector layer P1 compared to the case where the structure of the first surface region 1a is the same as the structure of the second surface region 1b.

[0113] The hole discharge promoting structure 210 is a structure in which the spacing between the trench gates 90 in the first surface region 1a, i.e., the first trench spacing L3, is formed to be greater than the spacing between the trench gates 90 in the second surface region 1b, i.e., the second trench spacing L4.

[0114] For example, the following ratio is used: when the second trench spacing L4 above the second collector layer P2 is 1, the first trench spacing L3 above the first collector layer P1 is 2 to 3.

[0115] By increasing the spacing between the trench gates, i.e., the trench pitch, the hole discharge path is enlarged, promoting hole discharge. The hole discharge promotion structure 210 is a structure that promotes hole discharge above the first collector layer P1 and improves the hole discharge delay compared to the case where the structure of the first surface region 1a is the same as the structure of the second surface region 1b.

[0116] Figure 9 The structure of the semiconductor device 201 involved in the modified example of Embodiment 2 is shown in a cross-sectional view of the semiconductor device 201 in the yz direction, which is perpendicular to the extension direction of the trench gate 90.

[0117] like Figure 9 As shown, in the surface region 10a of the semiconductor device 201, both the first collector layer P1 and the second collector layer P2 have a carrier accumulation layer 24 of a first conductivity type with a higher impurity concentration than the drift layer 12 between the drift layer 12 and the base layer 22.

[0118] The hole discharge promoting structure 211 of the semiconductor device 201 in the first surface region 1a of the modified embodiment 2 is formed such that the spacing between the trench gates 90 above the first collector layer P1, i.e., the first trench spacing, is formed to be greater than the spacing between the trench gates 90 above the second collector layer P2, i.e., the second trench spacing, and the first trench spacing is progressively narrowed in the direction from the first collector layer P1 to the second collector layer P2.

[0119] That is, the first trench spacing L5 and L6 on the first collector layer P1 side and the second trench spacing L7 on the second collector layer P2 side are in the relationship L5>L6>L7.

[0120] The first trench spacing is larger than the second trench spacing. Therefore, the hole discharge promotion structure 211 and the hole discharge promotion structure 210 are similarly designed to improve the delay of hole discharge by promoting the discharge of holes above the first collector layer P1 compared to the case where the structure of the first surface region 1a is the same as the structure of the second surface region 1b.

[0121] Furthermore, the hole current density tends to decrease in stages in the direction from the first collector layer P1 to the second collector layer P2. Therefore, by constructing a structure in which the first trench spacing gradually narrows in the direction from the first collector layer P1 to the second collector layer P2, the non-uniformity of the hole current density distribution can be improved.

[0122] According to the semiconductor device of Embodiment 2, by providing a hole discharge promotion structure 210 or a hole discharge promotion structure 211 on the first surface region 1a, similar to Embodiment 1, the delay in hole discharge caused by the concentration of hole current above the first collector layer P1 can be reduced, and the turn-off loss in the concentrated portion of hole current can be reduced.

[0123] Implementation method 3.

[0124] In Embodiment 3, the same reference numerals are used for structural elements that are the same as those in Embodiment 1 of this disclosure, and descriptions of the same or corresponding parts are omitted. Hereinafter, the semiconductor device 300 according to Embodiment 3 will be described with reference to the figures.

[0125] Figure 10 The structure of the semiconductor device 300 according to Embodiment 3 is shown in a cross-sectional view of the semiconductor device 300 in the yz direction, which is perpendicular to the extension direction of the trench gate 90.

[0126] like Figure 10As shown, in the surface region 10a of the semiconductor device 300 according to Embodiment 3, both the first surface region 1a and the second surface region 1b have a carrier accumulation layer 24 of a first conductivity type with an impurity concentration higher than that of the drift layer 12 formed between the drift layer 12 and the base layer 22.

[0127] In the semiconductor device 300 according to Embodiment 3, a hole discharge promoting structure 310 is formed in the first surface region 1a. The hole discharge promoting structure 310 is a structure that promotes the discharge of holes from the upper part of the first collector layer P1 compared to the case where the structure of the first surface region 1a is the same as the structure of the second surface region 1b.

[0128] The hole discharge promoting structure 310 is configured such that a second conductivity type bottom layer 95 is formed at the bottom of the trench gate 90 above the first collector layer P1, and a second conductivity type sidewall layer 99 is formed on the sidewall of the trench gate 90. In contrast, no second conductivity type bottom layer or second conductivity type sidewall layer is formed in the trench gate 90 in the second surface region 1b.

[0129] The bottom layer 95 is connected to the base layer 22 between the trench gates 90 via the sidewall layer 99, and is connected to the emitter electrode 46 via the base layer 22. Holes are also discharged to the emitter electrode 46 via the bottom layer 95 at the bottom of the trench gates 90 in the first surface region 1a. The hole discharge promotion structure 310 is a structure that increases the discharge path of holes above the first collector layer P1 to promote the discharge of holes above the first collector layer P1 and improve the hole discharge delay compared to the case where the structure of the first surface region 1a is the same as the structure of the second surface region 1b.

[0130] According to the semiconductor device of Embodiment 3, the hole discharge promotion structure 310 provided in the first surface region 1a can, similarly to Embodiment 1, reduce the delay in hole discharge caused by the concentration of hole current above the first collector layer P1 and reduce the turn-off loss in the concentrated portion of hole current.

[0131] Implementation method 4.

[0132] In Embodiment 4, the same reference numerals are used for structural elements that are the same as in Embodiment 1 of this disclosure, and descriptions of the same or corresponding parts are omitted. Hereinafter, the semiconductor device 400 according to Embodiment 4 will be described with reference to the figures.

[0133] Figure 11 The structure of the semiconductor device 400 according to Embodiment 4 is shown in a cross-sectional view of the semiconductor device 400 in the yz direction, which is perpendicular to the extension direction of the trench gate 90.

[0134] like Figure 11 As shown, in the surface region 10a of the semiconductor device 400 according to Embodiment 4, both the first surface region 1a and the second surface region 1b have a carrier accumulation layer 24 of a first conductivity type with an impurity concentration higher than that of the drift layer 12 formed between the drift layer 12 and the base layer 22.

[0135] In the semiconductor device 400 according to Embodiment 4, a hole discharge promoting structure 410 is formed in the first surface region 1a. The hole discharge promoting structure 410 is a structure that promotes the discharge of holes from the upper part of the first collector layer P1 compared to the case where the structure of the first surface region 1a is the same as the structure of the second surface region 1b.

[0136] The hole discharge promoting structure 410 is a structure in which the number of emitter contact layers 44 in the first surface region 1a is greater than the number of emitter contact layers 44 in the second surface region 1b.

[0137] Holes are discharged to the emitter electrode 46 via the emitter contact layer 44. Increasing the number of emitter contact layers 44 promotes hole discharge.

[0138] The hole discharge promotion structure 410 is configured such that, compared to the second surface region 1b, the number of emitter contact layers 44 that serve as the discharge path for holes in the first surface region 1a is increased, thereby promoting the discharge of holes above the first collector layer P1 and improving the delay in hole discharge compared to the case where the structure of the first surface region 1a is the same as that of the second surface region 1b.

[0139] Furthermore, the emitter contact layer 44 above the second collector layer P2 can also be not only as... Figure 11 As shown, the trench gates 90 are arranged in a staggered manner in the z-direction, i.e., the arrangement direction of the trench gates 90, and also in a staggered manner in the x-direction (not shown), which is perpendicular to the plane of the paper, i.e., the extension direction of the trench gates 90.

[0140] According to the semiconductor device of Embodiment 4, the hole discharge promotion structure 410 provided in the first surface region 1a can, similarly to Embodiment 1, reduce the delay in hole discharge caused by the concentration of hole current above the first collector layer P1 and reduce the turn-off loss in the concentrated portion of hole current.

[0141] Implementation method 5.

[0142] Embodiment 5 is an embodiment in which the semiconductor device described in any of Embodiments 1 to 4 is applied as a power conversion device for power equipment intended for high-frequency applications. This disclosure is not limited to any specific power conversion device; hereinafter, Embodiment 5 will be described in the case of applying this disclosure to a three-phase inverter. When the semiconductor device described in any of Embodiments 1 to 4 is applied to a power conversion device, the hole discharge promotion structure provided in the semiconductor device described in any of Embodiments 1 to 4 can reduce the delay in hole discharge caused by the uneven density distribution of hole current in the semiconductor device, and can reduce the turn-off loss in the concentrated portion of hole current.

[0143] Figure 12 This is a block diagram schematically illustrating the structure of a power conversion system employing the power conversion device 2000 according to Embodiment 5. The power conversion system includes a power source 1000, a power conversion device 2000, and a load 3000. The power source 1000 is a DC power source that supplies DC power to the power conversion device 2000. The power source 1000 can be composed of various power sources, such as a DC system, solar cells, a battery, or a rectifier circuit or AC / DC converter connected to an AC system. Alternatively, the power source 1000 can also be composed of a DC / DC converter that converts DC power output from a DC system into a specified power.

[0144] The power conversion device 2000 is a three-phase inverter connected between the power source 1000 and the load 3000. It converts the DC power supplied from the power source 1000 into AC power and supplies AC power to the load 3000. Figure 12 As shown, the power conversion device 2000 includes: a main conversion circuit 2001 that converts the input DC power into AC power and outputs it; a drive circuit 2002 that outputs drive signals for driving each switching element of the main conversion circuit 2001; and a control circuit 2003 that outputs control signals for controlling the drive circuit 2002 to the drive circuit 2002.

[0145] Load 3000 is a three-phase motor driven by AC power supplied from power conversion device 2000. Furthermore, load 3000 is not limited to a specific application; it is a motor mounted on various electrical equipment, such as those used in hybrid vehicles, electric vehicles, railway vehicles, elevators, or air conditioning equipment.

[0146] The details of the power conversion device 2000 are described below. The main conversion circuit 2001 includes switching elements and freewheeling diodes (not shown). The switching elements perform switching operations to convert DC power supplied from the power source 1000 into AC power and supply it to the load 3000. Various circuit structures exist for the main conversion circuit 2001. The main conversion circuit 2001 according to Embodiment 5 is a two-level three-phase full-bridge circuit, which can be composed of six switching elements and six freewheeling diodes connected in anti-parallel to each switching element. At least one of the switching elements and freewheeling diodes of the main conversion circuit 2001 uses a semiconductor device as described in any of Embodiments 1 to 4. The six switching elements are connected in series in pairs to form upper and lower arms, and each upper and lower arm constitutes a phase (U phase, V phase, W phase) of the full-bridge circuit. Furthermore, the output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 2001, are connected to the load 3000.

[0147] The drive circuit 2002 generates drive signals for driving the switching elements of the main converter circuit 2001 and supplies them to the control electrodes of the switching elements of the main converter circuit 2001. Specifically, according to the control signals from the control circuit 2003 (described later), drive signals that turn the switching elements on and drive signals that turn the switching elements off are output to the control electrodes of each switching element. When the switching element is kept on, the drive signal is a voltage signal greater than the threshold voltage of the switching element (on signal); when the switching element is kept off, the drive signal is a voltage signal less than the threshold voltage of the switching element (off signal).

[0148] The control circuit 2003 controls the switching elements of the main converter circuit 2001 to supply the desired power to the load 3000. Specifically, the on-time is calculated based on the power to be supplied to the load 3000, determining when each switching element of the main converter circuit 2001 should be in the on state. For example, the main converter circuit 2001 can be controlled using pulse width modulation (PWM) control, which modulates the on-time of the switching elements according to the voltage to be output. Then, a control signal is output to the drive circuit 2002 as a control command, in a manner that outputs an on signal to the switching element that should be in the on state and an off signal to the switching element that should be in the off state at each time point. The drive circuit 2002 outputs an on or off signal to the control electrode of each switching element according to the control signal as a drive signal.

[0149] In the power conversion device according to Embodiment 5, the freewheeling diode of the main conversion circuit 2001 can be any of the semiconductor devices involved in Embodiments 1 to 4. By applying any of the semiconductor devices involved in Embodiments 1 to 4 to the power conversion device, the turn-off losses of the semiconductor device can be reduced using the structures shown in Embodiments 1 to 4. This improves the loss reduction of the power conversion device.

[0150] Furthermore, in Embodiment 5, an example of applying this disclosure to a two-level three-phase inverter was described; however, this disclosure is not limited to this and can be applied to various power conversion devices. For example, the power conversion device can also be a multi-level device such as a three-level device. Additionally, when supplying power to a single-phase load, this disclosure can also be applied to a single-phase inverter. Furthermore, when supplying power to DC loads, etc., this disclosure can also be applied to DC / DC converters or AC / DC converters.

[0151] Furthermore, the power conversion device disclosed herein is not limited to devices used in situations where the load is an electric motor. For example, it can also be used in power supply devices for electrical discharge machining machines, laser processing machines, induction heating cookers, or contactless power supply systems, and can also be used as a power regulator for solar power generation systems, energy storage systems, etc.

[0152] Furthermore, the features of the semiconductor devices described in embodiments 1 to 4 above can be appropriately combined to further enhance the effects of this disclosure. It can be combined with other known technologies, and a portion of the structure can be omitted or modified without departing from the spirit of this disclosure.

Claims

1. A semiconductor device, characterized in that, have: Buffer layer of the first conductivity type; The surface region on the side closer to the surface of the buffer layer; and The back area, which is closer to the back side of the buffer layer, The surface region has: A drift layer of the first conductivity type is formed on the buffer layer; A base layer of the second conductivity type is formed on the drift layer; A source layer of a first conductivity type and a contact layer of a second conductivity type are formed on the base layer and are adjacent to each other; Multiple trench gates are formed in such a way that they penetrate the source layer, the contact layer, and the base layer and reach the drift layer, and are spaced apart from each other and extend. An emitter contact layer is formed on the source layer and the contact layer; and An emitter electrode is formed on the emitter contact layer. The rear region has: A collector layer of the second conductivity type is formed beneath the buffer layer; and The collector electrode is formed beneath the collector layer. The current collector layer has alternating first and second current collector layers, the second current collector layer having a lower impurity concentration than the first current collector layer. The surface region includes a first surface region located above the first collector layer and a second surface region located above the second collector layer. The second surface region has a different structure than the first surface region. A hole discharge promoting structure is formed in the first surface region. This hole discharge promoting structure promotes the discharge of holes above the first collector layer compared to the case where the structure of the first surface region is the same as that of the second surface region. The cavitation facilitation structure includes the following components: In contrast to the configuration in the second surface region where a first carrier accumulation layer with a higher impurity concentration than the drift layer is formed between the drift layer and the base layer, no first carrier accumulation layer is formed between the drift layer and the base layer in the first surface region. The trenches used to form the trench gate in the second surface region are formed by penetrating the first carrier accumulation layer.

2. The semiconductor device according to claim 1, characterized in that, The cavitation facilitation structure also includes the following structures: A second carrier accumulation layer of a first conductivity type is formed between the drift layer and the base layer in the first surface region. The impurity concentration is lower than that of the first carrier accumulation layer and higher than that of the drift layer.

3. The semiconductor device according to claim 1, characterized in that, The cavitation facilitation structure also includes the following structures: The base layer formed on the drift layer in the first surface region becomes a deeper base layer than the base layer formed on the drift layer in the second surface region.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, The cavitation facilitation structure also includes the following structures: The spacing between the trench gates in the first surface region, i.e., the first trench spacing, is formed to be greater than the spacing between the trench gates in the second surface region, i.e., the second trench spacing.

5. The semiconductor device according to claim 4, characterized in that, The first trench spacing is formed to narrow in stages in the direction from the first collector layer to the second collector layer.

6. The semiconductor device according to any one of claims 1 to 3, characterized in that, The hole discharge promoting structure further includes the following configuration: in contrast to the formation of a second conductivity type substrate at the bottom of the trench gate and a second conductivity type sidewall layer on the sidewall of the trench gate in the first surface region, neither the substrate nor the sidewall layer is formed in the second surface region. The bottom layer is connected to the base layer between the trench gates via the sidewall layer.

7. The semiconductor device according to any one of claims 1 to 3, characterized in that, The cavitation facilitation structure also includes the following structures: The number of emitter contacts in the first surface region is greater than the number of emitter contacts in the second surface region.

8. The semiconductor device according to any one of claims 1 to 3, characterized in that, The first collector layer and the second collector layer are alternately formed in the arrangement direction of the trench gate, which is orthogonal to the extension direction of the trench gate. The spacing between the patterns of the first collector layer and the second collector layer in the contact layer is the length obtained by adding the width of the first collector layer and the width of the second collector layer in a direction orthogonal to the extension direction of the trench gate.

9. The semiconductor device according to any one of claims 1 to 3, characterized in that, The first collector layer and the second collector layer are formed alternately in the extension direction of the trench gate. The spacing between the patterns of the first collector layer and the second collector layer in the contact layer is the length obtained by adding the width of the first collector layer and the width of the second collector layer in the extension direction of the trench gate.

10. The semiconductor device according to any one of claims 1 to 3, characterized in that, The collector layer has a first collector region and a second collector region alternately formed in an arrangement direction of the trench gates orthogonal to the extension direction of the trench gates. The first collector region is a region in which the first collector layer and the second collector layer are alternately formed in the extension direction of the trench gate. The second collector region is the region where only the second collector layer is formed, without the first collector layer. The spacing between the patterns in the contact layer that are configured with the first collector region and the second collector region is the length obtained by adding the width of the first collector layer in the first collector region and the width of the second collector layer in the second collector region in the arrangement direction of the trench gate.

11. The semiconductor device according to claim 8, characterized in that, The spacing is greater than 20 μm.

12. The semiconductor device according to claim 9, characterized in that, The spacing is greater than 20 μm.

13. The semiconductor device according to claim 10, characterized in that, The spacing is greater than 20 μm.

14. An electrical device having a semiconductor device as described in any one of claims 1 to 13.

15. The power equipment according to claim 14, wherein, The power equipment is a power conversion device. The power equipment includes: The main conversion circuit converts the input power into output power. The driving circuit outputs a driving signal to the semiconductor device to drive the semiconductor device. as well as The control circuit outputs control signals to the drive circuit.

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