Semiconductor device and method for manufacturing the same

Abstract

By preventing defects from forming at the interface between the contact region and the silicide layer, a highly reliable IGBT with suppressed current-on degradation is realized. As a means for achieving this goal, a semiconductor device is provided, comprising: a collector region formed on the lower surface of a semiconductor substrate and constituting the IGBT; and a collector electrode formed on the lower surface of the collector region via a silicide layer, the silicide layer comprising aluminum, a first metal that bonds more readily to silicon than aluminum, and a second metal that bonds more readily to carbon than aluminum.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular to an IGBT. Background Art

[0002] When forming an IGBT (Insulated Gate Bipolar Transistor), a silicide layer is sometimes formed on the back surface of the semiconductor substrate and then a collector electrode made of metal is formed below the silicide layer to reduce the connection resistance between the semiconductor substrate and the collector electrode.

[0003] Patent Document 1 (Japanese Patent Application Publication No. 2018-56584) describes forming a silicide layer between a p-type collector region and a collector electrode on the back side of a semiconductor substrate having an IGBT. Patent Document 1 describes using Ni, Co, or Ti as the material for the silicide layer and Al (aluminum) as the material for the collector electrode.

[0004] Furthermore, Patent Document 1 describes that in order to prevent degradation of carrier lifetime due to introduction of defects into the p-type collector region and the n-type buffer region, laser annealing is performed on the back surface of the substrate where the p-type collector region is formed.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Publication No. 2018-56584 Summary of the Invention

[0008] Problems to be solved by the invention

[0009] When forming an IGBT on an n-type SiC substrate, one approach is to sequentially grow a p-type layer, serving as the collector region, and an n-type layer, serving as the drift region, on the SiC substrate using epitaxial growth. The SiC substrate is then removed by grinding, and the collector electrode is connected to the bottom surface of the p-type layer via a silicide layer. However, during the formation of this silicide layer, defects may form on the bottom surface of the p-type layer. Such defects can cause electrical degradation of the semiconductor device.

[0010] The present invention aims to improve the reliability of a semiconductor device, particularly to prevent defects from occurring at the interface between a contact region and a silicide layer, thereby realizing a highly reliable IGBT capable of suppressing current-on degradation.

[0011] The foregoing and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0012] Means for solving problems

[0013] The outline of a representative embodiment among the embodiments disclosed in this application is briefly described as follows.

[0014] A semiconductor device according to one embodiment comprises: a semiconductor substrate; a collector region formed on a lower surface of the semiconductor substrate and having a first conductivity type; a first semiconductor region formed on the collector region in the semiconductor substrate and having a second conductivity type different from the first conductivity type; a second semiconductor region formed extending from the upper surface of the semiconductor substrate to a depth midway through the first semiconductor region and having the first conductivity type; and an emitter region formed extending from the upper surface of the second semiconductor region to a depth midway through the second semiconductor region and having a first conductivity type. The body region is separated and is of the second conductivity type; the gate electrode is formed on the semiconductor substrate through an insulating film so as to cover the second semiconductor region between the emitter region and the first semiconductor region; the silicide layer is formed in contact with the lower surface of the collector region; and the collector electrode is formed in contact with the lower surface of the silicide layer, the collector region, the emitter region and the gate electrode constitute an insulated gate bipolar transistor, and the silicide layer contains: aluminum, a first metal that is easier to combine with silicon than aluminum, and a second metal that is easier to combine with carbon than aluminum.

[0015] Effects of the Invention

[0016] The effects obtained by the representative inventions among the inventions disclosed in this application will be briefly described as follows.

[0017] According to the present invention, the reliability of a semiconductor device can be improved. In particular, defects can be prevented from occurring at the interface between the contact region and the silicide layer, thereby realizing a highly reliable IGBT that can suppress current-on degradation. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a cross-sectional view showing a semiconductor device according to an embodiment.

[0019] Figure 2 It is a cross-sectional view during the manufacturing process of the semiconductor device according to the embodiment.

[0020] Figure 3 Then Figure 2 A cross-sectional view of a semiconductor device during a manufacturing process.

[0021] Figure 4 Then Figure 3 A cross-sectional view of a semiconductor device during a manufacturing process.

[0022] Figure 5 Then Figure 4A cross-sectional view of a semiconductor device during a manufacturing process.

[0023] Figure 6 Then Figure 5 A cross-sectional view of a semiconductor device during a manufacturing process.

[0024] Figure 7 Then Figure 6 A cross-sectional view of a semiconductor device during a manufacturing process.

[0025] Figure 8 This is a graph showing the Si content in the silicide layer in the semiconductor device according to the embodiment.

[0026] Figure 9 This is a graph showing current-voltage characteristics due to energization in the semiconductor device according to the embodiment.

[0027] Figure 10 It is a cross-sectional view showing a semiconductor device according to a modification of the embodiment.

[0028] Figure 11 It is a cross-sectional view during the manufacturing process of a semiconductor device according to a comparative example.

[0029] Figure 12 Then Figure 11 A cross-sectional view of a semiconductor device during a manufacturing process.

[0030] Figure 13 Then Figure 12 A cross-sectional view of a semiconductor device during a manufacturing process.

[0031] Figure 14 This is a graph showing the current-voltage characteristics of a semiconductor device according to a comparative example when current is applied.

[0032] Figure 15 This is a graph showing the Si content in the silicide layer of the semiconductor device of the comparative example. DETAILED DESCRIPTION

[0033] The following describes the embodiments of the present invention in detail based on the accompanying drawings. In addition, in the full figures used to illustrate the embodiments, the same figure marks are marked on the components with the same functions, and their repeated descriptions are omitted. In addition, in the following embodiments, the description of the same or identical parts is not repeated in principle unless it is particularly necessary. In addition, in the drawings illustrating the embodiments, in order to make the structure easier to understand, sometimes even plan views or stereoscopic views are shaded. Furthermore, in the drawings illustrating the embodiments, in order to make the structure easier to understand, sometimes shading is omitted in the cross-sectional views.

[0034] also," - "as well as" +" is a reference symbol indicating the relative impurity concentration of n-type or p-type conductivity. For example, - ”, “n”, “n + ”, the impurity concentration of the n-type impurity becomes higher.

[0035] <Details of room for improvement>

[0036] The following uses Figures 11 to 14 To illustrate the details of the room for improvement. Figures 11 to 13 It is a cross-sectional view during the manufacturing process of a semiconductor device according to a comparative example. Figure 14 This is a graph showing the current-voltage characteristics of a semiconductor device according to a comparative example when current is applied.

[0037] This section describes how, when forming an IGBT (Insulated Gate Bipolar Transistor) on a semiconductor substrate, defects are generated due to the formation of a silicide layer between the collector region and the collector electrode on the lower surface of the semiconductor substrate, leading to current degradation. The semiconductor substrate referred to in this application includes not only a bulk substrate but also a laminated substrate comprising a bulk substrate and an epitaxial layer formed on the bulk substrate, as well as an epitaxial substrate consisting solely of the epitaxial layer without the bulk substrate at the bottom of the laminated substrate.

[0038] First, if Figure 11 As shown in the comparative example, n-type SiC (silicon carbide) was prepared. + Then, on the upper surface of the SiC substrate 13, p-type SiC (silicon carbide) substrate 13 is formed in sequence by epitaxial growth. + Type collector region 3, n-type buffer layer 4 and n - The collector region 3 contains, for example, Al (aluminum) as a dopant.

[0039] Next, if Figure 12 As shown in FIG, a p-type body layer 6 and an n-type layer are formed on the upper surface of the drift layer 5. + Type emitter region 7 and p + The main body layer contact region 8 is formed. Next, a gate electrode 10 is formed on the drift layer 5 via a gate insulating film 9, and an interlayer insulating film 11 is formed to cover the gate electrode 10. Next, a through-hole is formed through the interlayer insulating film 11, and then an emitter electrode 12 is formed on the interlayer insulating film 11. A portion of the emitter electrode 12 is embedded in the through-hole, electrically connecting to the emitter region 7 and the main body layer contact region 8. Thus, an IGBT including the gate electrode 10, the emitter region 7, and the collector region 3 is formed.

[0040] Next, the SiC substrate 13 is removed through a grinding process, exposing the collector region 3. When an n-channel IGBT is formed on a semiconductor substrate composed of SiC, the back side of the semiconductor substrate becomes the collector region 3, or p-type layer. High-quality SiC substrates contain only n-type layers. Therefore, in the manufacturing process, as described above, the stacked structure including the collector region 3, buffer layer 4, and drift layer 5 is formed entirely by epitaxial growth, and the SiC substrate 13, which serves as the bulk substrate, is removed by grinding.

[0041] Next, if Figure 13 As shown, after forming the silicide layer 20 on the lower surface of the collector region 3, the collector electrode 1 is formed in contact with the lower surface of the silicide layer 20. The collector electrode 1 is ohmically connected to the collector region 3 via the silicide layer 20. As described above, the IGBT of the comparative example is completed.

[0042] When forming the silicide layer 20, a metal layer containing, for example, Ti (titanium) and Al (aluminum) is deposited on the lower surface of the collector region 3, and then laser annealing is performed on the lower surface to react the metal layer with the semiconductor substrate, thereby forming the silicide layer 20. However, during this process, there is a possibility that defects will be formed at the interface between the back surface of the semiconductor substrate and the silicide layer 20.

[0043] IGBT is a bipolar device. Due to carrier recoupling, Figure 14 Such deterioration due to electrical conduction is a problem. Figure 14 This is a graph with the collector voltage on the horizontal axis and the collector current on the vertical axis. Figure 14 , it is shown that the current-voltage characteristics deteriorate over time when a stress current continues to flow through a semiconductor device of a comparative example including an IGBT. Figure 14 In the graph, the solid line shows the graph at the time of starting the current flow, the dotted line shows the graph after 50 hours have passed since the start of the current flow, and the one-dot chain line shows the graph after 100 hours have passed since the start of the current flow.

[0044] like Figure 14 As shown, in the IGBT of the comparative example, the current-voltage characteristics deteriorate significantly as the time of the current flowing therethrough passes. This is believed to be caused by defects formed at the interface between the back side of the semiconductor substrate and the silicide layer. As the metal layer (silicide metal) used in the formation of the silicide layer formed in contact with the p-type semiconductor substrate containing SiC, Ti / Al is considered. However, it is difficult to generate a compound of Ti or Al and Si (silicon), and Si dissolves, thereby forming a Si-rich silicide region with a high Si content. It is believed that due to this influence, the lattice spacing of SiC near the interface between the semiconductor substrate and the silicide layer is deformed, resulting in the above-mentioned defects.

[0045] In contrast, if a silicide layer is not formed on the back surface of the semiconductor substrate to prevent defect formation, the connection resistance between the collector region and the collector electrode increases, and the performance of the semiconductor device degrades. Therefore, it is necessary to suppress defect formation during the silicide process.

[0046] Thus, in an IGBT in which a silicide layer is formed on the back surface of a semiconductor substrate, there is room for improvement in preventing current-carrying degradation.

[0047] Therefore, in the embodiments of the present application, efforts are made to address the above-mentioned room for improvement. The technical concept of the embodiments in which these efforts are made will be described below.

[0048] (Implementation Method)

[0049] Hereinafter, a semiconductor device will be described using the drawings, taking an IGBT made of SiC as an example.

[0050] <Structure of Semiconductor Device>

[0051] use Figure 1 The structure of the IGBT, which is the semiconductor device of this embodiment, will be described. Figure 1 : is a cross-sectional view showing the semiconductor device according to this embodiment.

[0052] like Figure 1 As shown in FIG. 1 , the semiconductor device of this embodiment includes a semiconductor substrate (epitaxial substrate) made of silicon carbide (SiC). The semiconductor substrate includes p + Type collector region 3, n-type buffer layer 4 and n - The structure of the drift layer 5 of the collector region 3 is shown in FIG. 1 . The collector region 3 is a p-type semiconductor region containing, for example, Al (aluminum) as a dopant, and is formed on the lower surface of the semiconductor substrate. The buffer layer 4 and the drift layer 5 are n-type semiconductor regions containing, for example, N (nitrogen) or P (phosphorus) as a dopant. The buffer layer 4 and the drift layer 5 are formed on the collector region 3 in the semiconductor substrate. The semiconductor substrate mainly contains SiC. The semiconductor substrate including the collector region 3, the buffer layer 4, and the drift layer 5 has: a main surface (first main surface) which is the upper surface of the drift layer 5; and a back surface (second main surface) which is the lower surface of the collector region 3 and is located on the opposite side of the main surface.

[0053] A plurality of p-type body layers 6 are formed from the upper surface of the drift layer 5 (the upper surface of the semiconductor substrate) to the mid-depth of the drift layer 5. In addition, an n-type body layer 6 is formed from the upper surface of the body layer 6 to the mid-depth of the body layer 6. + Type emitter region (first emitter region) 7 and p +The emitter region 7 and the body layer contact region 8 are in contact with each other in a direction along the upper surface of the semiconductor substrate. The depths of the emitter region 7 and the body layer contact region 8 are approximately the same. In the direction along the upper surface of the semiconductor substrate, the body layer 6 is located between the emitter region 7 and the drift layer 5, and the emitter region 7 and the drift layer 5 are separated from each other. The body layer 6 and the body layer contact region 8 are, for example, p-type semiconductor regions containing Al (aluminum) as a dopant, and the emitter region 7 is, for example, an n-type semiconductor region containing N (nitrogen) or P (phosphorus) as a dopant.

[0054] A gate electrode 10 is formed on the semiconductor substrate via a gate insulating film 9 so as to cover the upper surface of the body layer 6 between the emitter region 7 and the drift layer 5. The gate electrode 10 is formed so as to extend across at least the drift layer 5, the body layer 6, and directly above each of the emitter region 7 arranged on the upper surface of the semiconductor substrate. In other words, the gate electrode 10 is formed on the semiconductor substrate via the gate insulating film 9 so as to cover the body layer 6 between the emitter region 7 and the drift layer 5.

[0055] The gate insulating film 9 is made of, for example, silicon oxide, and the gate electrode 10 is made of, for example, polycrystalline silicon. The stacked film including the gate insulating film 9 and the gate electrode 10 is covered by an interlayer insulating film 11 formed on the gate electrode 10. In other words, the side surfaces and top surface of the gate electrode 10 are covered by the interlayer insulating film 11. The gate insulating film 9 may be wider than the gate electrode 10.

[0056] A through hole (connection hole) is formed in the interlayer insulating film 11 at a position separated from the gate electrode 10, extending from the upper surface of the interlayer insulating film 11 to the lower surface. At the bottom of the through hole, the emitter region 7 and the body layer contact region 8 are exposed from the interlayer insulating film 11. An emitter electrode 12 is formed on the semiconductor substrate, including the through hole, so as to cover the interlayer insulating film 11. In other words, the emitter electrode 12 is embedded in the through hole and electrically connected to the emitter region 7 and the body layer contact region 8. Although not shown here, a silicide layer may be present between the emitter electrode 12 and the emitter region 7 and the body layer contact region 8 at the bottom of the through hole.

[0057] The lower surface of the collector region 3 is covered by the silicide layer 2, and the lower surface of the silicide layer 2 is covered by the collector electrode 1. The lower surface of the collector region 3 is in contact with the silicide layer 2, and the lower surface of the silicide layer 2 is in contact with the collector electrode 1. The collector electrode 1 is electrically connected to the collector region 3 via the silicide layer 2.

[0058] The silicide layer 2 contains Al (aluminum), Ti (titanium), and Ni (nickel). The inclusion of Al in the silicide layer 2 creates an ohmic connection between the collector region 3, which has Al as a dopant, and the silicide layer 2. Furthermore, the silicide layer 2 contains Ti, a metal that bonds more readily with carbon (carbon) than Al. That is, carbon and Ti bond more readily than carbon and Al. Consequently, Ti and C bond between the silicide layer 2 and the collector region 3 to form TiC (titanium carbide). TiC is contained in the silicide layer 2.

[0059] Furthermore, as one of the main features of this embodiment, the silicide layer 2 contains Ni, a metal that bonds more readily with Si than Al. That is, Si and Ni bond more readily than Si and Al. The silicide layer 2 may also contain Mo (molybdenum) or Co (cobalt), a metal that bonds more readily with Si than Al, instead of Ni. Ni and Si bond between the silicide layer 2 and the collector region 3 to form Ni2Si. Ni2Si is contained in the silicide layer 2. The Ni content in the silicide layer 2 is 10 at.% or more and less than 33 at.%. Furthermore, the combined Ni and Ti content in the silicide layer 2 is less than 50 at.%, and the Al content in the silicide layer 2 is greater than 50 at.%. Thus, by reducing the Ni content in the silicide layer 2 to less than 33 at.%, the Al content in the silicide layer 2 can be increased. This enables a low-resistance ohmic connection between the silicide layer 2, which contains a high amount of Al, and the collector region 3, which is doped with Al.

[0060] <Method for Manufacturing Semiconductor Device>

[0061] The following uses Figures 2 to 7 A method for manufacturing the semiconductor device according to this embodiment will be described. Figures 2 to 7 It is a cross-sectional view during the manufacturing process of the semiconductor device of this embodiment.

[0062] First, if Figure 2 As shown, prepare n containing SiC (silicon carbide) + The SiC substrate 13 has a main surface and a back surface opposite to the main surface. Next, p-type SiC substrate 13 is formed in sequence by epitaxial growth. + Type collector region 3, n-type buffer layer 4 and n - The collector region 3 includes, for example, Al as a dopant. The buffer layer 4 and the drift layer 5 include, for example, N or P as a dopant.

[0063] Next, if Figure 3 As shown in FIG, a p-type body layer 6 and an n-type layer 7 are formed on the upper surface of the drift layer 5 by, for example, ion implantation. +Type emitter region 7 and p + The main body layer 6, emitter region 7 and main body layer contact region 8 are formed by using Figure 1 As described.

[0064] Next, a gate electrode 10 is formed on the drift layer 5 via a gate insulating film 9. The gate insulating film 9 is formed, for example, by thermal oxidation or CVD (Chemical Vapor Deposition). A polysilicon film is deposited (formed) on the gate insulating film 9 by CVD or the like, and the polysilicon film is patterned using photolithography and etching to form the gate electrode 10 formed of the polysilicon film.

[0065] Next, an interlayer insulating film 11 is formed on the drift layer 5 and the gate electrode 10, for example, by CVD. The interlayer insulating film 11 includes, for example, silicon oxide. Next, a through-hole is formed through the interlayer insulating film 11 using photolithography and etching. As a result, at the bottom of the through-hole, the emitter region 7 and the body layer contact region 8 are exposed from the interlayer insulating film 11. Next, an emitter electrode 12 is formed on the drift layer 5 and the interlayer insulating film 11 within the through-hole, for example, by sputtering. A portion of the emitter electrode 12 is buried in the through-hole, and the emitter electrode 12 is electrically connected to the emitter region 7 and the body layer contact region 8. The emitter electrode 12 includes, for example, Al. Before forming the emitter electrode 12, a silicide layer can be formed to cover the upper surface of the emitter region 7 and the body layer contact region 8 exposed at the bottom of the through-hole. The silicide layer can be formed using a well-known silicidation technique.

[0066] Thus, an IGBT including the gate electrode 10 , the emitter region 7 , and the collector region 3 is formed.

[0067] Next, if Figure 4 As shown, the SiC substrate 13 is removed by grinding to expose the lower surface of the collector region 3. The resulting semiconductor substrate (epitaxial substrate) including the collector region 3, buffer layer 4, and drift layer 5 has a primary surface (first primary surface) serving as the upper surface of the drift layer 5, and a rear surface (second primary surface) located opposite this primary surface and serving as the lower surface of the collector region 3. Thus, a semiconductor substrate including the collector region 3, buffer layer 4, and drift layer 5 is prepared.

[0068] In addition, although it is described here that the SiC substrate 13 is removed after forming the device structure such as the gate electrode on the semiconductor substrate, if the epitaxial substrate on the SiC substrate 13 has sufficient strength, it is also possible to remove the SiC substrate 13 as shown in FIG. Figure 2 As shown, after the epitaxial layer is formed, the SiC substrate 13 is removed, and then the emitter region 7 and the gate electrode 10 are formed.

[0069] Next, the semiconductor substrate is turned upside down so that the back surface of the semiconductor substrate where the collector region 3 is formed faces upward.

[0070] Next, if Figure 5 As shown in FIG. 1 , a metal layer 2a containing Ni and a metal layer 2b containing Ti and Al are sequentially formed on the back side of the semiconductor substrate (the upper surface of the collector region 3). The metal layers 2a and 2b are formed, for example, by sputtering. Here, the collector region 3 is in contact with the metal layer 2a, and the collector region 3 and the metal layer 2b are separated by the metal layer 2a. The metal layer 2b covers the back side of the semiconductor substrate and the upper surface of the collector region 3 (as shown in FIG. 1 ). Figure 4 (As shown in the figure, the lower surface of the collector region 3 is shown without flipping the semiconductor substrate.) The thickness of metal layer 2a is smaller than that of metal layer 2b. Here, the thickness of metal layer 2a is, for example, 10 nm, and the thickness of metal layer 2b is, for example, 250 nm. Co or Mo can be used as the material for metal layer 2a. In other words, the material of metal layer 2a can be a metal that bonds more easily with Si than Al.

[0071] The metal layer 2b can be a layer containing a mixture of Ti and Al, or a stacked film of Ti film and Al film. Here, for example, the metal layer 2b containing the Al film and the Ti film is formed by stacking the Al film and the Ti film in sequence on the metal layer 2a containing Ni.

[0072] Next, laser annealing is performed by irradiating the back surface of the semiconductor substrate on which the metal layers 2a and 2b are stacked from the metal layer 2b side with laser light. This heat treatment based on laser irradiation allows local heating of only the vicinity of the back surface of the semiconductor substrate. This reduces damage to the device structures on the main surface side (e.g., gate insulating film 9 and emitter region 7).

[0073] like Figure 6 As shown, by the above-mentioned laser annealing, the metal layers 2a and 2b react with the SiC constituting the semiconductor substrate to form the silicide layer 2. That is, the silicide layer 2 is in contact with the upper surface of the collector region 3. The silicide layer 2 contains Si, Ni, Ti and Al. In the laser annealing, since the heating time is short, by making the film thickness of the metal layer 2a in contact with the collector region 3 less than 30nm, the metal layer 2b not in contact with the collector region 3 can reliably react with the collector region 3. However, if the film thickness of the metal layer 2a is less than 10nm, the effect of the present embodiment described later is small due to the small amount of Ni. Therefore, the desired range of the thickness of the metal layer 2a is greater than 10nm and less than 30nm. In addition, the thickness of the metal layer 2b is, for example, 200 to 300nm.

[0074] Because metal layer 2b contains Al, collector region 3, which has Al as a dopant, and silicide layer 2 are ohmically connected. Furthermore, silicide layer 2 contains Ti, a metal that bonds more readily with carbon (C) than Al. Consequently, Ti and C bond between silicide layer 2 and collector region 3 to form TiC (titanium carbide). TiC is contained in silicide layer 2.

[0075] Between the silicide layer 2 and the collector region 3, Ni and Si combine to form Ni2Si. Ni2Si is contained in the silicide layer 2. The Ni content in the silicide layer 2 is 10 at.% or more and less than 33 at.%. Furthermore, the combined Ni and Ti content in the silicide layer 2 is less than 50 at.%, and the Al content in the silicide layer 2 is greater than 50 at.%. Thus, by reducing the Ni content in the silicide layer 2 to less than 33 at.%, the Al content in the silicide layer 2 can be increased. This enables a low-resistance ohmic connection between the silicide layer 2, which contains a large amount of Al, and the collector region 3, which uses Al as a dopant.

[0076] Next, if Figure 7 As shown, a collector electrode 1 is formed in contact with the lower surface of the silicide layer 2. The collector electrode 1 can be formed, for example, by sputtering. The collector electrode comprises, for example, Al or Au (gold). The collector electrode 1 is ohmically connected to the collector region 3 via the silicide layer 2. Then, the semiconductor substrate is turned upside down to obtain Figure 7 The structure shown in FIG. Through the above, the IGBT of this embodiment is completed.

[0077] <Effects of this embodiment>

[0078] Next, the effects of this embodiment will be described.

[0079] If used Figures 11 to 14 As described in the comparative example shown, in the IGBT, there is room for improvement in preventing the current degradation caused by defects generated at the interface between the back surface of the semiconductor substrate and the silicide layer.

[0080] Here, in Figure 15 The graph shows the distribution of Si in the depth direction in the IGBT of the comparative example. Figure 15 This is a graph showing the relationship between the depth (distance) shown on the horizontal axis and the Si content shown on the vertical axis in a comparative example. Figure 15 Schematic diagram of a region 1A corresponding to a collector region and a region 1B corresponding to a silicide layer below the collector region are shown.

[0081] like Figure 15As shown, the Si content in the comparative example IGBT decreases temporarily within the silicide layer deeper than the collector layer, but increases again in regions deeper within the silicide layer. In other words, Si is distributed within the silicide layer. This Si distribution causes deformation (defects) in the SiC lattice spacing on the lower surface of the collector region.

[0082] Therefore, in this embodiment, unlike the comparative example, a metal (e.g., Ni) that is more easily bonded to Si than Al is added as the material constituting the silicide layer 2 in contact with the lower surface of the collector electrode. In other words, a metal that easily bonds to Si is used as the silicide metal for forming the silicide layer. Furthermore, Ni, which forms a compound with Si, is added to the interface between the semiconductor substrate comprising SiC and the silicide layer, and laser annealing is performed thereon.

[0083] Thus, achieving Figure 8 As shown, the distribution of Si in the silicide layer decreases monotonically in the depth direction. Figure 8 This is a graph showing the relationship between the depth (distance) shown on the horizontal axis and the Si content shown on the vertical axis in this embodiment. Figure 8 In, with Figure 15 Likewise, a region 1A corresponding to the collector region and a region 1B corresponding to the silicide layer below the collector region are shown.

[0084] That is, Figure 8 As shown, this achieves a distribution in which the amount of Si gradually decreases in the depth direction within the silicide layer, thereby suppressing Si bias. In other words, the Si content in the silicide layer gradually decreases as it moves from the interface between the silicide layer and the collector region to the lower surface of the silicide layer. This suppresses the occurrence of lattice spacing distortion at the interface between the semiconductor substrate and the silicide layer. Consequently, the formation of defects at this interface is suppressed.

[0085] exist Figure 9 The graph shows changes in current-voltage characteristics due to energization in the IGBT of this embodiment. Figure 9 The horizontal axis is the collector voltage and the vertical axis is the collector current. Figure 9 In the graph, the solid line shows the graph when the current starts to flow, the dotted line shows the graph after 760 hours from the start of the current flow, and the dotted line shows the graph after 1000 hours from the start of the current flow. Figure 9 There is almost no difference in the current-voltage characteristics in these three graphs. Figure 14 Compared with the comparative example described above, it can be seen that the IGBT of this embodiment can suppress the degradation caused by current flow. That is, in this embodiment, by suppressing the generation of crystal defects, a highly reliable IGBT with suppressed degradation caused by current flow can be realized.

[0086] In addition, in order to achieve ohmic connection with a p-type SiC semiconductor substrate in which Al is a dopant, a silicide layer containing a large amount of Al is required. However, since Al density is low, Figure 5 The thickness of the metal layer 2b shown is increased. In addition, in order to suppress the influence of laser annealing on the device structure, the heating time is short. Therefore, it is important to make the metal layer 2a and the semiconductor substrate react as easily as possible.

[0087] Therefore, in the manufacturing process of the semiconductor device of this embodiment, the metal layer 2a is formed in contact with the semiconductor substrate, and laser annealing with a short heating time is performed to achieve a reliable reaction between the metal constituting the metal layer 2a and Si constituting SiC.

[0088] <Modification>

[0089] Since this embodiment relates to the structure of the back side of the semiconductor substrate, the structure of the main surface side of the semiconductor substrate can be modified in various ways. That is, the silicide layer of this embodiment can be applied not only to planar IGBTs in which the gate electrode is formed on the flat upper surface of the semiconductor substrate, but also to trench IGBTs in which, for example, trench gate electrodes are provided on the upper surface of the semiconductor substrate.

[0090] exist Figure 10 A cross-sectional view of a trench IGBT according to this modification is shown. Figure 10 The IGBT shown has a trench 14 extending from the upper surface of the semiconductor substrate (epitaxial substrate) to the middle of the drift layer 5, and a gate electrode 10 is formed not only on the main surface of the semiconductor substrate but also in the trench 14 via a gate insulating film 9. Figure 1 The structure shown is different. That is, the gate electrode 10 is a trench gate electrode buried in the trench 14. In addition, here, the main layer 6 and the emitter region 7 thereon are connected in the trench 14. The other structures are the same as Figure 1 The same is true for the IGBT shown.

[0091] In the manufacturing process of semiconductor devices, Figure 2 After the steps described above, for example, after forming the body layer 6, the emitter region 7, and the body layer contact region 8, and before forming the gate insulating film 9, the trench 14 is formed. Figures 3 to 6 As described above, by forming the gate insulating film 9, the gate electrode 10, the silicide layer 2 and the collector electrode 1, etc., a Figure 10 The IGBT of this modified example shown can form the trench 14 by forming a resist pattern on a semiconductor substrate using a photolithography technique, for example, and performing dry etching using the resist pattern as an etch stop mask.

[0092] In this manner, also in a trench-type IGBT, by forming the silicide layer 2 of this embodiment, the same effects as described above can be obtained.

[0093] As mentioned above, the invention made by the inventors of the present invention has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention.

[0094] For example, the material, conductivity type, and manufacturing conditions of each part are not limited to those described in the aforementioned embodiment, and various modifications are possible, which is self-evident. Here, for the convenience of explanation, the conductivity type of the fixed semiconductor substrate and the semiconductor region is described, but it is not limited to the conductivity type described in the aforementioned embodiment.

[0095] Industrial applicability

[0096] The present invention can be widely applied to a semiconductor device including an IGBT having a silicide layer and a method for manufacturing the same.

[0097] Description of Reference Signs

[0098] 1 Collector electrode

[0099] 2 Silicide layer

[0100] 2a, 2b metal layers

[0101] 3 Collector region

[0102] 4 Buffer layer

[0103] 5 Drift layer

[0104] 6 Main layer

[0105] 7 Emitter region

[0106] 8 Main layer contact area

[0107] 9 Gate insulating film

[0108] 10 Gate electrode.

Claims

1. A semiconductor device, characterized in that: have: semiconductor substrates; a collector region formed on the lower surface of the semiconductor substrate and having a first conductivity type; a first semiconductor region formed on the collector region in the semiconductor substrate and having a second conductivity type different from the first conductivity type; a second semiconductor region extending from the upper surface of the semiconductor substrate to a depth midway between the first semiconductor region and being of the first conductivity type; an emitter region extending from the upper surface of the second semiconductor region to a depth midway through the second semiconductor region, separated from the first semiconductor region, and having the second conductivity type; a gate electrode formed on the semiconductor substrate via an insulating film so as to cover the second semiconductor region between the emitter region and the first semiconductor region; a silicide layer formed in contact with the lower surface of the collector region; and a collector electrode formed in contact with the lower surface of the silicide layer, The collector region, the emitter region, and the gate electrode constitute an insulated gate bipolar transistor, The silicide layer includes aluminum, a first metal that bonds more easily to silicon than aluminum, and a second metal that bonds more easily to carbon than aluminum.

2. The semiconductor device according to claim 1, wherein In the silicide layer, the content of the first metal is less than 33 at. %.

3. The semiconductor device according to claim 2, wherein In the silicide layer, the content of the first metal is 10 at. % or more.

4. The semiconductor device according to claim 1, wherein The first metal is nickel, cobalt or molybdenum.

5. The semiconductor device according to claim 1, wherein The silicon content in the silicide layer gradually decreases from the interface between the silicide layer and the collector region toward the lower surface of the silicide layer.

6. The semiconductor device according to claim 1, wherein The semiconductor substrate includes silicon carbide.

7. A method for manufacturing a semiconductor device, characterized in that: The process is as follows: (a) preparing a semiconductor substrate having a main surface and a rear surface opposite to the main surface, and having a collector region of a first conductivity type formed on the rear surface, and a first semiconductor region of a second conductivity type different from the first conductivity type formed on the collector region; (b) forming the second semiconductor region of the first conductivity type extending from the upper surface of the semiconductor substrate to a depth midway through the first semiconductor region; (c) forming the second conductivity type emitter region extending from the upper surface of the second semiconductor region to a depth midway within the second semiconductor region and separated from the first semiconductor region; (d) forming a gate electrode on the semiconductor substrate via an insulating film so as to cover the second semiconductor region between the emitter region and the first semiconductor region; (e) after the step (a), forming a silicide layer in contact with the lower surface of the collector region; and (f) After the step (e), forming a collector electrode in contact with the lower surface of the silicide layer, The collector region, the emitter region, and the gate electrode constitute an insulated gate bipolar transistor, The silicide layer includes aluminum, a first metal that bonds more easily to silicon than aluminum, and a second metal that bonds more easily to carbon than aluminum.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: The (e) step comprises the following steps: (e1) forming a first metal layer that is in contact with the lower surface of the collector region and includes the first metal; (e2) forming a second metal layer covering the lower surface of the first metal layer and comprising aluminum and the second metal; and (e3) Performing a heat treatment to react the semiconductor substrate, the first metal layer, and the second metal layer to form the silicide layer.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: In the step (e3), the heat treatment is performed by irradiating the lower surface of the semiconductor substrate with laser light from the second metal layer side.

10. The method for manufacturing a semiconductor device according to claim 8, wherein: The thickness of the first metal layer is less than 30 nm.

11. The method for manufacturing a semiconductor device according to claim 10, wherein: The first metal layer has a thickness of 10 nm or more.

12. The method for manufacturing a semiconductor device according to claim 7, wherein: The first metal is nickel, cobalt or molybdenum.

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