Method for manufacturing a photomask and a semiconductor structure

Abstract

The present application relates to a photomask and a method for manufacturing a semiconductor structure. The photomask is provided with a plurality of first photomask patterns arranged in parallel at intervals, and a second photomask pattern is provided in the extending direction of the first photomask patterns. Among them, there is a first distance between the first photomask pattern and the second photomask pattern. The first projection of the second photomask pattern on the target area of the device to be exposed coincides at least partially with the second projection of the plurality of first photomask patterns on the target area. The first distance is set according to the exposure parameters of the device to be exposed. Since two different photomask patterns are designed on the same photomask in the present application, and two different exposure patterns can be formed by moving the photomask according to different application requirements, the layout design area can be reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular, to a photomask and a method for manufacturing a semiconductor structure. Background Art

[0002] In the field of semiconductor technology, Testkey refers to a test structure on a wafer used to collect wafer acceptance test (WAT) data. Before the development of a process platform, developers need to design various different Testkey structures, and then adjust the process based on the WAT results of these Testkeys.

[0003] When performing WAT testing on the Flash Cells (memory cells) of an Embedded Flash Memory (E-Flash), it is also necessary to design different Flash Cell Testkey structures. By performing ion implantation on different regions of the Flash Cells, different Flash Cell Testkey structures can be formed. In the traditional technology, different cell source / drain (CSD) photomasks usually need to be designed to achieve ion implantation in different regions, resulting in an increase in the layout design area. Summary of the Invention

[0004] Based on this, it is necessary to provide a photomask and a method for manufacturing a semiconductor structure that can reduce the layout design area.

[0005] To achieve the above object, on the one hand, the present invention provides a photomask. The photomask is provided with a plurality of first photomask patterns arranged in parallel at intervals, and a second photomask pattern is provided in the extending direction of the first photomask patterns. Among them,

[0006] The first photomask pattern and the second photomask pattern have a first spacing. The first projection of the second photomask pattern on the target area of the device to be exposed coincides at least partially with the second projection of the plurality of first photomask patterns on the target area. The first spacing is set according to the exposure parameters of the device to be exposed.

[0007] In one embodiment, the photomask is further provided with a first alignment mark pattern and a second alignment mark pattern; the first alignment mark pattern and the second alignment mark pattern are located in the empty area of the photomask; the third projection of the first alignment mark pattern on the alignment area of the device to be exposed coincides completely with the fourth projection of the second alignment mark pattern on the alignment area; there is a second spacing between the first alignment mark pattern and the second alignment mark pattern, and the second spacing is equal to the first spacing.

[0008] In one embodiment, the first alignment mark pattern includes a first sub-alignment mark pattern, a second sub-alignment mark pattern, a third sub-alignment mark pattern, and a fourth sub-alignment mark pattern. The first sub-alignment mark pattern and the second sub-alignment mark pattern are arranged in parallel at intervals. The third sub-alignment mark pattern and the fourth sub-alignment mark pattern are arranged in parallel at intervals. The extending directions of the first sub-alignment mark pattern and the third sub-alignment mark pattern intersect. The second alignment mark pattern includes a fifth sub-alignment mark pattern, a sixth sub-alignment mark pattern, a seventh sub-alignment mark pattern, and an eighth sub-alignment mark pattern. The fifth sub-alignment mark pattern and the sixth sub-alignment mark pattern are arranged in parallel at intervals. The seventh sub-alignment mark pattern and the eighth sub-alignment mark pattern are arranged in parallel at intervals. The extending directions of the fifth sub-alignment mark pattern and the seventh sub-alignment mark pattern intersect.

[0009] The above-mentioned photomask is provided with a plurality of first photomask patterns arranged in parallel at intervals, and a second photomask pattern is provided in the extending direction of the first photomask pattern. Among them, there is a first distance between the first photomask pattern and the second photomask pattern. The first projection of the second photomask pattern on the target area of the device to be exposed coincides at least partially with the second projection of the plurality of first photomask patterns on the target area. The first distance is set according to the exposure parameters of the device to be exposed. Since two different photomask patterns are designed on the same photomask, and two different exposure patterns can be formed by moving the photomask according to different application requirements, the layout design area can be reduced.

[0010] On the other hand, the present application also provides a method for manufacturing a semiconductor structure, including:

[0011] Providing a substrate;

[0012] Forming a plurality of first active regions arranged at intervals in the substrate; each of the first active regions extends along a first direction;

[0013] Forming a plurality of polysilicon structures on the first active regions; each of the polysilicon structures extends along a second direction; the second direction intersects with the first direction;

[0014] Exposing and performing a first ion implantation on each of the first active regions by using each of the first photomask patterns of the photomask described in any one of the above embodiments to form a plurality of first ion implantation regions in the first active regions between the polysilicon structures; or, exposing and performing a first ion implantation on each of the first active regions by using the second photomask pattern of the photomask described in any one of the above embodiments to form a plurality of first ion implantation regions in the first active regions between the polysilicon structures.

[0015] In one embodiment, after forming the plurality of first ion implantation regions, the method further includes:

[0016] Exposing and performing a second ion implantation on each of the first active regions to form a plurality of second ion implantation regions within the first active regions.

[0017] In one embodiment, the ions implanted by the first ion implantation include boron ions; the ions implanted by the second ion implantation include boron difluoride ions.

[0018] In one embodiment, the method further includes:

[0019] While forming a plurality of first active regions arranged at intervals within the substrate, a second active region is formed within the substrate; the second active region extends along the second direction.

[0020] In one embodiment, the method further includes:

[0021] Forming a first pad and a second pad on one side of the semiconductor structure;

[0022] Forming a third pad and a fourth pad on the other side of the semiconductor structure; wherein,

[0023] The first pad is connected to each of the first active regions; the second pad is connected to the second active region; the third pad is connected to each of the polysilicon structures close to the second active region; the fourth pad is connected to each of the polysilicon structures far from the second active region.

[0024] In one embodiment, when performing exposure and first ion implantation on each of the first active regions using each of the first photomask patterns of the photomask described in any of the above embodiments, the method further includes:

[0025] Controlling the movement of the photomask so that each of the first photomask patterns is located between the second pad and the third pad, and the second photomask pattern is located between the third pad and the fourth pad.

[0026] In one embodiment, when performing exposure and first ion implantation on each of the first active regions using the second photomask pattern of the photomask described in any of the above embodiments, the method further includes:

[0027] Controlling the movement of the photomask so that each of the first photomask patterns is located between the first pad and the second pad, and the second photomask pattern is located between the second pad and the third pad.

[0028] The method for preparing the above semiconductor structure includes forming a plurality of first active regions arranged at intervals in the substrate, each of the first active regions extending along a first direction; forming a plurality of polysilicon structures on the first active regions, each of the polysilicon structures extending along a second direction; the second direction intersecting the first direction; performing exposure and first ion implantation on each of the first active regions using each of the first photomask patterns of the photomask described in any of the above embodiments, so as to form a plurality of first ion implantation regions in the first active regions between the polysilicon structures; or performing exposure and first ion implantation on each of the first active regions using the second photomask pattern of the photomask described in any of the above embodiments, so as to form a plurality of first ion implantation regions in the first active regions between the polysilicon structures. Since two different photomask patterns are designed on the same photomask, and two different exposure patterns can be formed by moving the photomask according to different application requirements, and then two different semiconductor structures can be formed, thereby reducing the layout design area. Description of the Drawings

[0029] To more clearly illustrate the technical solutions in the embodiments of the present application or in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0030] Figure 1 It is a schematic structural diagram of a photomask provided in an embodiment;

[0031] Figure 2 It is a schematic structural diagram of the alignment mark pattern of a photomask provided in an embodiment;

[0032] Figure 3 It is a schematic structural diagram of the alignment mark pattern of a photomask provided in another embodiment;

[0033] Figure 4 It is a flowchart of a method for preparing a semiconductor structure provided in an embodiment;

[0034] Figure 5 It is a schematic structural diagram of the structure obtained in step S102 in a method for preparing a semiconductor structure provided in an embodiment;

[0035] Figure 6 It is a schematic structural diagram of the structure obtained in step S103 in a method for preparing a semiconductor structure provided in an embodiment;

[0036] Figure 7Schematic top view of the structure obtained in step S104 of the method for preparing a semiconductor structure provided in an embodiment;

[0037] Figure 8 Schematic cross-sectional view of the structure obtained in step S104 of the method for preparing a semiconductor structure provided in an embodiment in the Figure 7 A-A' direction;

[0038] Figure 9 Schematic top view of the structure obtained in step S104 of the method for preparing a semiconductor structure provided in another embodiment;

[0039] Figure 10 Schematic cross-sectional view of the structure obtained in step S104 of the method for preparing a semiconductor structure provided in an embodiment in the Figure 9 B-B' direction;

[0040] Figure 11 Schematic cross-sectional view of the structure obtained after forming a plurality of second ion implantation regions in the method for preparing a semiconductor structure provided in an embodiment;

[0041] Figure 12 Schematic cross-sectional view of the structure obtained after forming a plurality of second ion implantation regions in the method for preparing a semiconductor structure provided in another embodiment;

[0042] Figure 13 Schematic cross-sectional view of the structure obtained after forming a second active region in the substrate in the method for preparing a semiconductor structure provided in an embodiment;

[0043] Figure 14 Schematic cross-sectional view of the structure obtained after forming each pad in the method for preparing a semiconductor structure provided in an embodiment;

[0044] Figure 15 Schematic top view of the structure when each first active region is exposed using each first photomask pattern in the method for preparing a semiconductor structure provided in an embodiment;

[0045] Figure 16 Schematic top view of the structure when each first active region is exposed using a second photomask pattern in the method for preparing a semiconductor structure provided in an embodiment;

[0046] Figure 17 Schematic cross-sectional view of the structure obtained in step S104 of the method for preparing a semiconductor structure provided in yet another embodiment;

[0047] Figure 18 Schematic cross-sectional view of the structure obtained in step S104 of the method for preparing a semiconductor structure provided in yet another embodiment.

[0048] Description of reference numerals in the drawings: 101 - first photomask pattern, 102 - second photomask pattern, 201 - first alignment mark pattern, 2011 - first sub - alignment mark pattern, 2012 - second sub - alignment mark pattern, 2013 - third sub - alignment mark pattern, 2014 - fourth sub - alignment mark pattern, 202 - second alignment mark pattern, 2021 - fifth sub - alignment mark pattern, 2022 - sixth sub - alignment mark pattern, 2023 - seventh sub - alignment mark pattern, 2024 - eighth sub - alignment mark pattern, 203 - front - layer alignment mark pattern, 30 - first active region, 301 - first ion - implantation region, 302 - second ion - implantation region, 40 - polysilicon structure, 401 - select gate structure, 402 - control gate structure, 4021 - floating gate, 4022 - inter - gate dielectric layer, 4023 - control gate, 50 - second active region, 601 - first pad, 602 - second pad, 603 - third pad, 604 - fourth pad, 70 - device to be exposed. Detailed implementation manners

[0049] To facilitate the understanding of this application, the following will describe this application more comprehensively with reference to the relevant drawings. Embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of this application more thorough and comprehensive.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the description of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0051] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, without departing from the teachings of the present invention, the first element, component, region, layer, doping type, or portion discussed below may be referred to as the second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0052] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. In addition, the device may also include additional orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0053] As used herein, the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising" or "has / having" etc. specify the presence of the stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0054] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the invention, so that variations in the shapes shown, for example due to manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions shown herein, but include shape deviations due to, for example, manufacturing techniques. For example, an implantation region shown as rectangular will typically have rounded or curved features and / or an implantation concentration gradient at its edges, rather than a binary change from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Thus, the regions shown in the figures are substantially schematic, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the invention.

[0055] Please refer to Figure 1 , this application provides a photomask. The photomask is provided with a plurality of first photomask patterns 101 arranged in parallel at intervals, and a second photomask pattern 102 is provided in the extending direction of the first photomask patterns 101. Wherein, there is a first distance between the first photomask pattern 101 and the second photomask pattern 102, and at least part of the first projection of the second photomask pattern 102 orthographically projected on the target region of the device 70 to be exposed coincides with the second projection of the plurality of first photomask patterns 101 orthographically projected on the target region, and the first distance is set according to the exposure parameters of the device 70 to be exposed.

[0056] Wherein, the exposure parameters of the device 70 to be exposed refer to parameters such as the size of each exposure region, the shape of each exposure region, and the distance between each exposure region of the device 70 during exposure. Since during the exposure process, each photomask pattern of the photomask will be exposed simultaneously to form corresponding exposure patterns in each exposure region of the device 70 to be exposed. For example, when using each first photomask pattern for exposure, the second photomask pattern will also be exposed. If the exposure pattern formed by using the second photomask pattern happens to be formed in the functional region of the device 70 to be exposed, it is likely to affect the performance of the device 70 to be exposed. Therefore, setting the first distance according to the exposure parameters of the device 70 to be exposed can ensure that the performance of the device 70 to be exposed will not be affected.

[0057] The photomask in this embodiment is provided with a plurality of first photomask patterns 101 arranged in parallel at intervals, and a second photomask pattern 102 is provided in the extending direction of the first photomask pattern 101. Among them, there is a first distance between the first photomask pattern 101 and the second photomask pattern 102. The first projection of the second photomask pattern 102 on the target area of the device 70 to be exposed coincides at least partially with the second projection of the plurality of first photomask patterns 101 on the target area. The first distance is set according to the exposure parameters of the device 70 to be exposed. Since two different photomask patterns are designed on the same photomask, and two different exposure patterns can be formed by moving the photomask according to different application requirements, the layout design area can be reduced.

[0058] Optionally, the first distance can include 100um to 300um. Specifically, the first distance can include 150um, 170um, 190um, 210um or 230um, etc. Of course, the first distance can also be other suitable distances, which are not limited in this embodiment.

[0059] Please refer to Figure 2 , in one embodiment, the photomask is further provided with a first alignment mark pattern 201 and a second alignment mark pattern 202; the first alignment mark pattern 201 and the second alignment mark pattern 202 are located in the blank area of the photomask; the third projection of the first alignment mark pattern 201 on the alignment area of the device 70 to be exposed coincides completely with the fourth projection of the second alignment mark pattern 202 on the alignment area; there is a second distance between the first alignment mark pattern 201 and the second alignment mark pattern 202, and the second distance is equal to the first distance.

[0060] Among them, the pattern formed in the blank area of the photomask will not affect the normal performance of the device 70 to be exposed after being exposed to the device 70 to be exposed. For example, the edge area of the photomask, etc. Each alignment mark pattern of the photomask is formed in the blank area of the photomask to play an alignment role during the exposure process, and the respective exposure patterns corresponding to be formed on the device 70 to be exposed after being exposed are located in the alignment area of the device 70 to be exposed rather than in the functional area of the device 70 to be exposed, so that the performance of the device 70 to be exposed will not be affected.

[0061] In addition, for the convenience of understanding this solution, Figure 2 each alignment mark pattern is located below each photomask pattern, and Figure 2The widths of the alignment mark patterns in each are the same as those of the corresponding mask patterns. It should be understood, however, that the alignment mark patterns are not limited to being disposed below the mask patterns, but can be arranged in other vacant areas of the mask, and the widths of the alignment mark patterns do not have to be the same as those of the mask patterns, as long as the second spacing between the alignment mark patterns is equal to the first spacing between the mask patterns. This embodiment places no restrictions here.

[0062] Please refer to Figure 3 , in one embodiment, the first alignment mark pattern 201 includes a first sub-alignment mark pattern 2011, a second sub-alignment mark pattern 2012, a third sub-alignment mark pattern 2013, and a fourth sub-alignment mark pattern 2014. The first sub-alignment mark pattern 2011 and the second sub-alignment mark pattern 2012 are arranged in parallel at intervals, the third sub-alignment mark pattern 2013 and the fourth sub-alignment mark pattern 2014 are arranged in parallel at intervals, and the extending directions of the first sub-alignment mark pattern 2011 and the third sub-alignment mark pattern 2013 intersect; the second alignment mark pattern 202 includes a fifth sub-alignment mark pattern 2021, a sixth sub-alignment mark pattern 2022, a seventh sub-alignment mark pattern 2023, and an eighth sub-alignment mark pattern 2024. The fifth sub-alignment mark pattern 2021 and the sixth sub-alignment mark pattern 2022 are arranged in parallel at intervals, the seventh sub-alignment mark pattern 2023 and the eighth sub-alignment mark pattern 2024 are arranged in parallel at intervals, and the extending directions of the fifth sub-alignment mark pattern 2021 and the seventh sub-alignment mark pattern 2023 intersect.

[0063] Among them, during the exposure process of forming the previous layer material layer (such as a polysilicon layer) in the previous process, the previous layer alignment mark pattern 203 also needs to be provided on the mask corresponding to the previous layer material layer to play an alignment role. Then, after exposure, the alignment mark pattern formed by the previous layer material layer in the alignment area of the device 70 to be exposed can be regarded as Figure 3 the previous layer alignment mark pattern 203 shown in. At this time, by measuring the distances between the previous layer alignment mark pattern 203 and each sub-mark pattern, the offset of each sub-alignment mark pattern can be calculated, and whether the mask is aligned can be determined by the magnitude of the offset. In this application, if it is necessary to use the first mask patterns 101 of the mask for exposure, the first alignment mark pattern 201 is aligned with the alignment area of the device 70 to be exposed, and then the offset between each sub-alignment mark pattern and each previous layer alignment mark pattern 203 is calculated to determine whether the mask is aligned; when it is necessary to use the second mask patterns 102 of the mask for exposure, only the mask is moved so that the second alignment mark pattern 202 is aligned with the alignment area of the device 70 to be exposed, and then the offset between each sub-alignment mark pattern and each previous layer alignment mark pattern 203 is calculated to determine whether the mask is aligned.

[0064] In addition, by making the second spacing between the first pair of alignment mark patterns 201 and the second pair of alignment mark patterns 202 equal to the first spacing between the first mask pattern 101 and the second mask pattern 102, before and after moving the mask, it is possible to determine whether the mask is aligned by the offset amounts of the respective alignment mark patterns.

[0065] In addition, for a better understanding of this solution, Figure 3 the number of each sub-alignment mark pattern shown is 4, and the shape is rectangular. Each sub-alignment mark pattern is arranged in the manner as Figure 3 shown. Of course, in the actual manufacturing process and application environment, the number, shape, and arrangement manner of each sub-alignment mark pattern can also be other suitable numbers, shapes, and arrangement manners. For example, each sub-alignment mark pattern can also be radially distributed, or there is a parallel interval distribution between each sub-alignment mark pattern, etc. This embodiment does not make any restrictions here.

[0066] Please refer to Figure 4 , this application also provides a method for manufacturing a semiconductor structure, including:

[0067] S101: Provide a substrate;

[0068] S102: Form a plurality of first active regions arranged at intervals in the substrate; each first active region extends along a first direction;

[0069] S103: Form a plurality of polysilicon structures on the first active regions; each polysilicon structure extends along a second direction; the second direction intersects the first direction;

[0070] S104: Use each first mask pattern of the mask in any of the above embodiments to expose and perform a first ion implantation on each first active region, so as to form a plurality of first ion implantation regions in the first active regions between each polysilicon structure; or, use the second mask pattern of the mask in any of the above embodiments to expose and perform a first ion implantation on each first active region, so as to form a plurality of first ion implantation regions in the first active regions between each polysilicon structure.

[0071] The method for preparing the above semiconductor structure includes forming a plurality of first active regions arranged at intervals in a substrate, each first active region extending along a first direction; forming a plurality of polysilicon structures on the first active regions, each polysilicon structure extending along a second direction; the second direction intersecting the first direction; performing exposure and first ion implantation on each first active region using each first photomask pattern of the photomask in any of the above embodiments to form a plurality of first ion implantation regions in the first active regions between the polysilicon structures; or performing exposure and first ion implantation on each first active region using the second photomask pattern of the photomask in any of the above embodiments to form a plurality of first ion implantation regions in the first active regions between the polysilicon structures. Since two different photomask patterns are designed on the same photomask, and two different exposure patterns can be formed by moving the photomask according to different application requirements, and then two different semiconductor structures can be formed, the layout design area can be reduced.

[0072] In step S101, refer to Figure 4 step S101 in Figure 5 and provide a substrate.

[0073] The material of the substrate can be any suitable substrate material known in the art. For example, it can be at least one of the materials mentioned below: silicon (Si), germanium (Ge), red phosphorus, silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, and also includes multilayer structures composed of these semiconductors, etc. Or it can be silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI). Or it can also be a double-sided polished wafer (DSP), or a ceramic substrate such as alumina, a quartz or glass substrate, etc. This embodiment does not limit this here.

[0074] In step S102, refer to Figure 4 step S102 in Figure 5 and form a plurality of first active regions 30 arranged at intervals in the substrate; each first active region 30 extends along a first direction.

[0075] Among them, the first direction can be the vertical direction as shown in Figure 5 . Of course, in other manufacturing processes and application environments, the first direction can also be other suitable directions. This embodiment does not limit this here.

[0076] In step S102, refer to Figure 4Step S102 in and Figure 6 , a plurality of polysilicon structures 40 are formed above the first active region 30, and each polysilicon structure 40 extends along a second direction; the second direction intersects the first direction.

[0077] Among them, the second direction may be perpendicular to the first direction, and the second direction may be, for example, the Figure 6 horizontal direction in. Of course, in other manufacturing processes and application environments, the second direction may also be other suitable directions, which are not limited in this embodiment.

[0078] In step S102, please refer to Figure 4 step S102 in and Figure 7 and Figure 8 , and each first active region 30 is exposed and first ion-implanted by using each first photomask pattern 101 of the photomask in any of the above embodiments to form a plurality of first ion-implanted regions 301 in the first active region 30 between the polysilicon structures 40; or, please refer to Figure 4 step S102 in and Figure 9 and Figure 10 , and each first active region 30 is exposed and first ion-implanted by using the second photomask pattern 102 of the photomask in any of the above embodiments to form a plurality of first ion-implanted regions 301 in the first active region 30 between the polysilicon structures 40.

[0079] Among them, the first ion implantation may be a cell source / drain (CSD) ion implantation process. Of course, it may also be other suitable ion implantation processes, which are not limited in this embodiment.

[0080] When performing a wafer acceptance test (WAT) on a Flash Cell (memory cell) of an Embedded Flash Memory (E-Flash), different regions of the first active region 30 are first ion-implanted to form a plurality of first ion-implanted regions 301, thereby forming different Flash Cell Testkey structures. During the preparation process of the Flash Cell Testkey structure, for example, as shown in Figures 7 to 10 , Figure 7 and Figure 8 , the semiconductor structure formed is a kind of Flash Cell Testkey structure, Figure 9 and Figure 10 , the semiconductor structure formed is another kind of Flash Cell Testkey structure. Of course, it can be understood that the positions of the first ion-implanted regions 301 are not limited toFigures 7 to 10 In the positions shown, in other fabrication processes and application environments, the formation position of the first ion implantation region 301 can also be determined by adjusting parameters such as the shape, size, or quantity of the first mask pattern 101 and the second mask pattern 102. This embodiment does not limit this here.

[0081] Since in this application, two different mask patterns are designed on the same mask, during the ion implantation process, only the mask needs to be moved instead of replaced to form different ion implantation regions on the semiconductor structure through the exposure process, thereby fabricating different Flash Cell Testkey structures. Thus, this application does not require designing multiple masks, and can thereby reduce the layout design area. For example, if it is necessary to design two different Flash Cell Testkey structures on the same wafer, then in the upper half of the wafer, each first mask pattern 101 of the mask can be used to expose and perform the first ion implantation on each first active region 30, while in the lower half of the wafer, only the mask needs to be moved, and the second mask pattern 102 of the mask can be used to expose and perform the first ion implantation on each first active region 30, so that two different Flash Cell Testkey structures can be formed on one wafer without replacing the mask, thereby reducing the layout design area. Of course, it can be understood that the solution of this application is not limited to designing different Flash Cell Testkey structures, and the core design concept of this application's solution can also be used to design other different semiconductor structures. This embodiment does not limit this here.

[0082] In addition, when designing the photomask in this application, by controlling the first spacing between the first photomask pattern 101 and the second photomask pattern 102, when each first photomask pattern 101 is used to expose and perform the first ion implantation on each first active region 30, the second photomask pattern 102 is located in the shallow trench isolation (STI) region between the first active regions 30 or other vacant regions that will not affect the formed semiconductor structure. Therefore, when each first photomask pattern 101 is used to expose and perform the first ion implantation on each first active region 30, although exposure and the first ion implantation will also be performed on the substrate corresponding to the second photomask pattern 102 of the photomask, the first ion implantation regions 301 formed on the substrate after being exposed and first ion implanted by the second photomask pattern 102 at this time will not affect the performance of the formed semiconductor structure. Similarly, when the second photomask pattern 102 is used to expose and perform the first ion implantation on each first active region 30, each first photomask pattern 101 is located in the STI region between the first active regions 30 or other vacant regions that will not affect the formed semiconductor structure, so that the first ion implantation regions 301 formed on the substrate after being exposed and first ion implanted by each first photomask pattern 101 at this time will not affect the performance of the formed semiconductor structure.

[0083] Please refer to Figure 11 and Figure 12 , in one embodiment, after step S104, it may further include: exposing and performing a second ion implantation on each first active region 30 to form a plurality of second ion implantation regions 302 in the first active region 30.

[0084] Among them, the second ion implantation may include PPLUS ion implantation. In step S104, if each first photomask pattern 101 is used to expose and perform the first ion implantation on the first active region 30, the semiconductor structure after forming the plurality of second ion implantation regions 302 is as Figure 11 shown; if the second photomask pattern 102 is used to expose and perform the second ion implantation on the first active region 30, the semiconductor structure after forming the plurality of second ion implantation regions 302 is as Figure 12 shown.

[0085] In addition, although Figure 11 and Figure 12 show that the positions of the second ion implantation regions 302 are fixed, the positions of the second ion implantation regions 302 may also vary according to the different semiconductor structures. At this time, only the photomask for forming the second ion implantation regions 302 needs to be improved with reference to the photomask of the above first ion region, and by the same method of moving the photomask as in the above embodiment, it can be realized that the positions of the second ion implantation regions 302 also vary, so as to further reduce the layout design area.

[0086] In one embodiment, the ions implanted by the first ion implantation include boron ions; the ions implanted by the second ion implantation include boron difluoride ions. Of course, in actual manufacturing processes and application scenarios, the ions implanted by the first ion implantation and the ions implanted by the second ion implantation can also be other suitable ions, which are not limited in this embodiment.

[0087] Please refer to Figure 13 , in one embodiment, while performing step S102, it may further include: forming a second active region 50 in the substrate; the second active region 50 extends along a second direction.

[0088] Optionally, the second active region 50 is disposed on the same layer as the first active region 30.

[0089] As Figure 13 shown, by forming the second active region 50 at the middle position of Figure 13 , the source regions of the formed semiconductor structure can be connected to save chip area. Of course, there may be multiple second active regions 50, or they may be formed at other suitable positions to connect the source regions of the formed semiconductor structure and / or the internal node regions.

[0090] Please refer to Figure 14 , in one embodiment, the method for manufacturing a semiconductor structure further includes: forming a first pad 601 and a second pad 602 on one side of the semiconductor structure; forming a third pad 603 and a fourth pad 604 on the other side of the semiconductor structure;

[0091] Wherein, as Figure 14 shown, the first pad 601 is connected to each first active region 30; the second pad 602 is connected to the second active region 50; the third pad 603 is connected to each polysilicon structure 40 close to the second active region 50; the fourth pad 604 is connected to each polysilicon structure 40 far from the second active region 50.

[0092] In one embodiment, please refer to Figure 15 , when performing exposure and first ion implantation on each first active region 30 using each first photomask pattern 101 of the photomask in any of the above embodiments, it may further include: controlling the movement of the photomask so that each first photomask pattern 101 is located between the second pad 602 and the third pad 603, and the second photomask pattern 102 is located between the third pad 603 and the fourth pad 604.

[0093] When designing the photomask, by adjusting the first spacing between each first photomask pattern 101 and each second photomask pattern 102, when each first photomask pattern 101 of the photomask in any of the above embodiments is used to expose and perform the first ion implantation on each first active region 30, as Figure 15 shown, each first photomask pattern 101 is located between the second pad 602 and the third pad 603, and the second photomask pattern 102 is located between the third pad 603 and the fourth pad 604. At this time, each first ion implantation region 301 formed on the substrate after being exposed by the second photomask pattern 102 and the first ion implantation will not affect the performance of the formed semiconductor structure, nor will it affect the performance of each pad.

[0094] In one embodiment, please refer to Figure 16 , when the second photomask pattern 102 of the photomask in any of the above embodiments is used to expose and perform the first ion implantation on each first active region 30, it may further include: controlling the movement of the photomask so that each first photomask pattern 101 is located between the first pad 601 and the second pad 602, and the second photomask pattern 102 is located between the second pad 602 and the third pad 603.

[0095] When designing the photomask, by adjusting the first spacing between each first photomask pattern 101 and each second photomask pattern 102, when the second photomask pattern 102 of the photomask in any of the above embodiments is used to expose and perform the first ion implantation on each first active region 30, as Figure 16 shown, each first photomask pattern 101 is located between the first pad 601 and the second pad 602, and the second photomask pattern 102 is located between the second pad 602 and the third pad 603. At this time, each first ion implantation region 301 formed on the substrate after being exposed by each first photomask pattern 101 and the first ion implantation will not affect the performance of the formed semiconductor structure, nor will it affect the performance of each pad.

[0096] In one embodiment, please refer to Figure 17 and Figure 18 , in the above step S103, the polysilicon structure 40 may further include a control gate structure 402 and a select gate structure 401, and the control gate structure 402 may further include a floating gate 4021, an inter-gate dielectric layer 4022, and a control gate 4023. Thus, after step S104, a structure as Figure 17 or as Figure 18 shown is formed. Among them, the inter-gate dielectric layer 4022 may include an oxide-nitride-oxide (ONO).

[0097] In the description of this specification, the descriptions referring to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. mean that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0098] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as within the scope described in this specification.

[0099] The above-described embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A photomask, characterized in that, The photomask is provided with a plurality of first photomask patterns arranged in parallel at intervals, and a second photomask pattern is provided in the extending direction of the first photomask patterns, wherein, a first distance exists between the first photomask pattern and the second photomask pattern, and a first projection of the second photomask pattern orthographically projected on a target area of a device to be exposed and a second projection of the plurality of first photomask patterns orthographically projected on the target area at least partially overlap, and the first distance is set according to exposure parameters of the device to be exposed; the photomask is further provided with a first alignment mark pattern and a second alignment mark pattern; the first alignment mark pattern and the second alignment mark pattern are located in a blank area of the photomask; a third projection of the first alignment mark pattern orthographically projected on an alignment area of the device to be exposed completely coincides with a fourth projection of the second alignment mark pattern orthographically projected on the alignment area; a second distance exists between the first alignment mark pattern and the second alignment mark pattern, and the second distance is equal to the first distance; wherein, the target area is a first active area of the device to be exposed. When each of the first photomask patterns is used to expose and perform first ion implantation on the first active area, the second photomask pattern is located in a shallow trench isolation structure area between the first active areas or in a blank area that does not affect the formed semiconductor structure; when each of the second photomask patterns is used to expose and perform first ion implantation on the first active area, the first photomask pattern is located in a shallow trench isolation structure area between the first active areas or in a blank area that does not affect the formed semiconductor structure.

2. The photomask according to claim 1, characterized in that, The first alignment mark pattern includes a first sub-alignment mark pattern, a second sub-alignment mark pattern, a third sub-alignment mark pattern and a fourth sub-alignment mark pattern. The first sub-alignment mark pattern and the second sub-alignment mark pattern are arranged in parallel at intervals. The third sub-alignment mark pattern and the fourth sub-alignment mark pattern are arranged in parallel at intervals. The extending directions of the first sub-alignment mark pattern and the third sub-alignment mark pattern intersect; the second alignment mark pattern includes a fifth sub-alignment mark pattern, a sixth sub-alignment mark pattern, a seventh sub-alignment mark pattern and an eighth sub-alignment mark pattern. The fifth sub-alignment mark pattern and the sixth sub-alignment mark pattern are arranged in parallel at intervals. The seventh sub-alignment mark pattern and the eighth sub-alignment mark pattern are arranged in parallel at intervals. The extending directions of the fifth sub-alignment mark pattern and the seventh sub-alignment mark pattern intersect.

3. A method for preparing a semiconductor structure, characterized in that, Including: providing a substrate; forming a plurality of first active areas arranged at intervals in the substrate; each of the first active areas extends along a first direction; forming a plurality of polysilicon structures on the first active areas, and each of the polysilicon structures extends along a second direction; the second direction intersects with the first direction; using each of the first photomask patterns of the photomask as claimed in claim 1 or 2 to expose and perform first ion implantation on each of the first active areas, so as to form a plurality of first ion implantation areas in the first active areas between the polysilicon structures; Alternatively, perform exposure and first ion implantation on each of the first active regions using the second photomask pattern of the photomask as described in claim 1 or 2, to form a plurality of first ion implantation regions in the first active regions between the polysilicon structures.

4. The method for manufacturing a semiconductor structure according to claim 3, wherein, After forming the plurality of first ion implantation regions, the method further includes: Performing exposure and second ion implantation on each of the first active regions to form a plurality of second ion implantation regions in the first active regions.

5. The manufacturing method of the semiconductor structure according to claim 4, wherein, The ions implanted in the first ion implantation include boron ions; the ions implanted in the second ion implantation include boron difluoride ions.

6. The method for preparing the semiconductor structure according to claim 4, wherein The method further includes: While forming a plurality of first active regions arranged at intervals in the substrate, forming a second active region in the substrate; the second active region extends along the second direction.

7. The method for preparing a semiconductor structure according to claim 6, wherein, The method further includes: Forming a first pad and a second pad on one side of the semiconductor structure; Forming a third pad and a fourth pad on the other side of the semiconductor structure; wherein, The first pad is connected to each of the first active regions; the second pad is connected to the second active region; the third pad is connected to each of the polysilicon structures close to the second active region; the fourth pad is connected to each of the polysilicon structures far from the second active region.

8. The method for preparing a semiconductor structure according to claim 7, wherein When performing exposure and first ion implantation on each of the first active regions using each of the first photomask patterns of the photomask as described in claim 1 or 2, the method further includes: Controlling the movement of the photomask so that each of the first photomask patterns is located between the second pad and the third pad, and the second photomask pattern is located between the third pad and the fourth pad.

9. The method for preparing a semiconductor structure according to claim 8, wherein, When performing exposure and first ion implantation on each of the first active regions using the second photomask pattern of the photomask as described in claim 1 or 2, the method further includes: Controlling the movement of the photomask so that each of the first photomask patterns is located between the first pad and the second pad, and the second photomask pattern is located between the second pad and the third pad.

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