Bandgap reference circuit

Abstract

Embodiments of the present disclosure provide a bandgap reference circuit, which includes a start-up circuit, a bandgap reference core circuit, and a clamping op-amp circuit. The start-up circuit generates a start-up current according to a supply voltage and a first bias current, and provides the start-up current to a reference voltage output terminal of the bandgap reference circuit to pull the bandgap reference circuit away from a degenerate state. The bandgap reference core circuit generates a core current to control voltages of a first node and a second node. The clamping op-amp circuit adjusts the reference voltage according to a voltage difference between the first node and the second node, the first bias current, and a second bias current, so that the voltages of the first node and the second node are equal. The bandgap reference core circuit includes a first transistor and a second transistor. Collector electrodes of the first transistor and the second transistor are directly coupled to a supply voltage terminal. Base electrodes of the first transistor and the second transistor are coupled to the reference voltage output terminal.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of integrated circuits, and in particular, to bandgap reference circuits. BACKGROUND

[0002] In a power management chip, an accurate reference voltage is needed to provide a reference voltage for loop regulation control of internal circuits, and this reference voltage needs to maintain a high reliability and high precision output under different environmental temperatures, different power supply voltages, and different process offsets, so as to maintain the system output voltage or output current accurate enough. However, after reliability tests such as high-temperature aging, the reference voltage output by the existing bandgap reference circuit often shows a large offset. SUMMARY

[0003] Embodiments described herein provide a bandgap reference circuit.

[0004] According to a first aspect of the present disclosure, a bandgap reference circuit is provided. The bandgap reference circuit comprises a start-up circuit, a bandgap reference core circuit, and a clamping operational amplifier circuit. The start-up circuit is configured to generate a start-up current according to a supply voltage from a supply voltage terminal and a first bias current from a first bias current terminal, and to provide the start-up current to a reference voltage output terminal of the bandgap reference circuit to pull the bandgap reference circuit out of degenerate state. The bandgap reference core circuit is configured to generate a core current to control voltages of a first node and a second node. The clamping operational amplifier circuit is configured to adjust a reference voltage according to a voltage difference between the first node and the second node, the first bias current, and a second bias current from a second bias current terminal, so that the voltages of the first node and the second node are equal. The bandgap reference core circuit comprises a first transistor and a second transistor. The collector of the first transistor and the collector of the second transistor are directly coupled to the supply voltage terminal. The base of the first transistor and the base of the second transistor are coupled to the reference voltage output terminal.

[0005] In some embodiments of the present disclosure, the bandgap reference core circuit further comprises a first resistor, a second resistor, a third resistor, and a trimming resistor. The first end of the first resistor is coupled to the emitter of the first transistor. The second end of the first resistor is coupled to the first node and the first end of the second resistor. The second end of the second resistor is coupled to the first end of the trimming resistor. The second end of the trimming resistor is coupled to the second voltage terminal. The first end of the third resistor is coupled to the emitter of the second transistor and the second node. The second end of the third resistor is coupled to the second voltage terminal.

[0006] In some embodiments of the present disclosure, the ratio of the emitter area of the first transistor to the emitter area of the second transistor is N:1. The ratio of the resistance values of the second resistor and the third resistor is 1:1. N is greater than 1.

[0007] In some embodiments of this disclosure, the ratio of the emitter area of ​​the first transistor to the emitter area of ​​the second transistor is 1:1. The ratio of the resistance values ​​of the second resistor to the third resistor is N:1, where N is greater than 1.

[0008] In some embodiments of this disclosure, the clamping operational amplifier circuit is also configured to periodically use one of the following as the voltage difference between the first node and the second node: the voltage of the first node minus the voltage of the second node; and the voltage of the second node minus the voltage of the first node.

[0009] In some embodiments of this disclosure, the startup circuit includes a third transistor, a fourth transistor, a fifth transistor, and a fourth resistor. The control terminal and second terminal of the third transistor are coupled to the first terminal of the fourth transistor. The first terminal of the third transistor is coupled to a second voltage terminal. The control terminal and second terminal of the fourth transistor are coupled to a first bias current terminal. The control terminal of the fifth transistor is coupled to the control terminal of the fourth transistor. The first terminal of the fifth transistor is coupled to a reference voltage output terminal. The second terminal of the fifth transistor is coupled to the first terminal of the fourth resistor. The second terminal of the fourth resistor is coupled to a power supply voltage terminal.

[0010] In some embodiments of this disclosure, the bandgap reference circuit further includes a low-temperature compensation circuit. The low-temperature compensation circuit is configured to raise the reference voltage when the temperature of the bandgap reference circuit is below a first threshold temperature.

[0011] In some embodiments of this disclosure, the bandgap reference circuit further includes a high-temperature compensation circuit. The high-temperature compensation circuit is configured to raise the reference voltage when the temperature of the bandgap reference circuit is higher than a second threshold temperature.

[0012] In some embodiments of this disclosure, the bandgap reference circuit further includes a bias current generating circuit. The bias current generating circuit is configured to generate a first bias current based on a second bias current, and output the first bias current from a first bias current terminal.

[0013] According to a second aspect of this disclosure, a bandgap reference circuit is provided. The bandgap reference circuit includes: a first transistor to a forty-sixth transistor, a first resistor to a thirteenth resistor, a first capacitor, and a trimming resistor, wherein the collector of the first transistor and the collector of the second transistor are coupled to a power supply voltage terminal. The base of the first transistor and the base of the second transistor are coupled to a reference voltage output terminal. A first terminal of the first resistor is coupled to the emitter of the first transistor. A second terminal of the first resistor is coupled to a first terminal of the second resistor. A second terminal of the second resistor is coupled to a first terminal of the trimming resistor. A second terminal of the trimming resistor is coupled to a second voltage terminal. A first terminal of a third resistor is coupled to the emitter of the second transistor. A second terminal of the third resistor is coupled to the second voltage terminal. The control terminal and the second terminal of the third transistor are coupled to the first terminal of a fourth transistor. The first terminal of the third transistor is coupled to the second voltage terminal. The control terminal and the second terminal of the fourth transistor are coupled to the second terminal of the thirteenth transistor. The control terminal of a fifth transistor is coupled to the control terminal of the fourth transistor. The first terminal of the fifth transistor is coupled to the reference voltage output terminal. The second terminal of the fifth transistor is coupled to the first terminal of the fourth resistor. The second terminal of the fourth resistor is coupled to a power supply voltage terminal. The first terminal of the fifth resistor is coupled to the second bias current terminal, the control terminal of the sixth transistor, and the control terminal of the ninth transistor. The second terminal of the fifth resistor is coupled to the second terminal of the sixth transistor, the control terminal of the seventh transistor, and the control terminal of the eighth transistor. The first terminal of the sixth transistor is coupled to the second terminal of the seventh transistor. The first terminal of the seventh transistor is coupled to the second voltage terminal and the first terminal of the eighth transistor. The second terminal of the eighth transistor is coupled to the first terminal of the ninth transistor. The second terminal of the ninth transistor is coupled to the first terminal of the sixth resistor, the control terminal of the tenth transistor, and the control terminal of the thirteenth transistor. The second terminal of the sixth resistor is coupled to the second terminal of the tenth transistor, the control terminal of the eleventh transistor, and the control terminal of the twelfth transistor. The first terminal of the tenth transistor is coupled to the second terminal of the eleventh transistor. The first terminal of the eleventh transistor is coupled to the power supply voltage terminal and the first terminal of the twelfth transistor. The second terminal of the twelfth transistor is coupled to the first terminal of the thirteenth transistor. The control terminal of the fourteenth transistor is coupled to the control terminal of the third transistor. The first terminal of the fourteenth transistor is coupled to the first terminal of the seventh resistor. The second terminal of the fourteenth transistor is coupled to the second terminal of the thirty-third transistor, the control terminal of the thirty-ninth transistor, and the control terminal of the fortieth transistor. The second terminal of the seventh resistor is coupled to the second voltage terminal. The control terminal of the fifteenth transistor is coupled to the first terminal of the seventeenth transistor. The first terminal of the fifteenth transistor is coupled to the first terminal of the sixteenth transistor and the second terminal of the nineteenth transistor. The second terminal of the fifteenth transistor is coupled to the second terminal of the seventeenth transistor, the first terminal of the eighth resistor, and the control terminal of the twenty-fourth transistor. The control terminal of the sixteenth transistor is coupled to the first terminal of the eighteenth transistor. The second terminal of the sixteenth transistor is coupled to the second terminal of the eighteenth transistor, the first terminal of the ninth resistor, and the control terminal of the twenty-third transistor.The control terminal of transistor 17 is coupled to the second terminals of transistors 44 and 45. The control terminal of transistor 18 is coupled to the second terminals of transistors 42 and 43. The second terminal of resistor 8 is coupled to the second voltage terminal and the second terminal of resistor 9. The control terminal of transistor 19 is coupled to the control terminal of transistor 10. The first terminal of transistor 19 is coupled to the second terminal of transistor 20. The control terminal of transistor 20 is coupled to the control terminal of transistor 11. The first terminal of transistor 20 is coupled to the power supply voltage terminal and the first terminal of transistor 21. The control terminal of transistor 21 is coupled to the control terminal of transistor 11. The second terminal of transistor 21 is coupled to the first terminal of transistor 22. The control terminal of transistor 22 is coupled to the control terminal of transistor 10. The second terminal of transistor 22 is coupled to the first terminals of transistors 23 and 24. The second terminal of transistor 23 is coupled to the second terminals of transistors 25, 27, and 28. The second terminal of transistor 24 is coupled to the second terminals of transistors 26, 29, and 30. The control terminal of transistor 25 is coupled to the control terminal of transistor 26 and the control terminal of transistor 7. The control terminal of transistor 27 is coupled to the control terminal of transistor 30 and the first clock signal terminal. The second terminal of transistor 27 is coupled to the second terminal of transistor 29 and the first terminal of transistor 31. The control terminal of transistor 28 is coupled to the control terminal of transistor 29 and the second clock signal terminal. The second terminal of transistor 28 is coupled to the second terminal of transistor 30 and the first terminal of transistor 32. The control terminal of transistor 31 is coupled to the control terminal of transistor 32 and the second bias current terminal. The second terminal of transistor 31 is coupled to the second terminal of transistor 33. The second terminal of transistor 32 is coupled to the second terminal of transistor 34, the control terminal of transistor 41, and the first terminal of the first capacitor. The control terminal of transistor 33 is coupled to the control terminal of transistor 34. The first terminal of transistor 33 is coupled to the second terminal of transistor 35 and the second terminal of transistor 37. The first terminal of transistor 34 is coupled to the second terminal of transistor 36 and the second terminal of transistor 38. The control terminal of transistor 35 is coupled to the control terminal of transistor 38 and the second clock signal terminal. The first terminal of transistor 35 is coupled to the first terminal of transistor 36 and the second terminal of transistor 39. The control terminal of transistor 36 is coupled to the control terminal of transistor 37 and the first clock signal terminal. The first terminal of the thirty-seventh transistor is coupled to the first terminal of the thirty-eighth transistor and the second terminal of the fortieth transistor. The first terminal of the thirty-ninth transistor is coupled to the first terminal of the fortieth transistor and the power supply voltage terminal. The first terminal of the forty-first transistor is coupled to the reference voltage output terminal, and the second terminal of the forty-first transistor is coupled to the first terminal of the tenth resistor.The second terminal of the first capacitor is coupled to the second voltage terminal. The second terminal of the tenth resistor is coupled to the power supply voltage terminal. The control terminal of the forty-second transistor is coupled to the control terminal of the forty-fifth transistor and the first clock signal terminal. The first terminal of the forty-second transistor is coupled to the emitter of the second transistor and the first terminal of the forty-fourth transistor. The control terminal of the forty-third transistor is coupled to the control terminal of the forty-fourth transistor and the second clock signal terminal. The first terminal of the forty-third transistor is coupled to the second terminal of the first resistor and the first terminal of the forty-fifth transistor. The control terminal of the forty-sixth transistor is coupled to the first terminal of the eleventh resistor and the first terminal of the twelfth resistor. The first terminal of the forty-sixth transistor is coupled to the first terminal of the thirteenth resistor. The second terminal of the forty-sixth transistor is coupled to the second terminal of the thirty-third transistor. The second terminal of the eleventh resistor is coupled to the reference voltage output terminal. The second terminal of the twelfth resistor is coupled to the second voltage terminal and the second terminal of the thirteenth resistor. Attached Figure Description

[0014] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0015] Figure 1 This is a schematic block diagram of a bandgap reference circuit according to an embodiment of the present disclosure;

[0016] Figure 2 This is another schematic block diagram of a bandgap reference circuit according to an embodiment of the present disclosure;

[0017] Figure 3 This is yet another schematic block diagram of a bandgap reference circuit according to an embodiment of the present disclosure;

[0018] Figure 4 This is an exemplary circuit diagram of a bandgap reference circuit according to embodiments of the present disclosure; and

[0019] Figure 5 This is a schematic diagram of the temperature characteristics of the reference voltage output by the bandgap reference circuit.

[0020] In the accompanying diagram, markers with the same last two digits correspond to the same elements. It should be noted that the elements in the diagram are schematic and not drawn to scale. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0022] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0023] In all embodiments of this disclosure, since the source and drain of a metal-oxide-semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, the controlled middle terminal of the MOS transistor is referred to as the control terminal, and the remaining two terminals of the MOS transistor are referred to as the first terminal and the second terminal, respectively. For ease of consistent expression, in this context, the base of a bipolar junction transistor (BJT) is referred to as the control terminal, the emitter of the BJT is referred to as the first terminal, and the collector of the BJT is referred to as the second terminal. Furthermore, terms such as "first" and "second" are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0024] The inventors of this disclosure have discovered that the reason why the reference voltage output by the existing bandgap reference circuit exhibits a large deviation after reliability tests such as high-temperature aging is that the collectors of the two N-type reference core transistors in the bandgap reference circuit are at low positions and have different potentials. Furthermore, these two reference core transistors typically have different emitter areas and single-transistor current densities, which makes it impossible to achieve good matching of the leakage current from the collector to the reverse-biased PN junction of the P-type substrate. This results in a deviation of the reference core current (the current flowing through the reference core transistor, which can also be referred to as the "core current" in this context). This deviation is nonlinear and random, and cannot be adjusted by single-point trimming with a trimming resistor, thus affecting the reliability of the bandgap reference circuit.

[0025] The embodiments of this disclosure present a highly reliable and accurate bandgap reference circuit. By moving two NPN reference core transistors to a higher position (power supply voltage side), and connecting the collectors of these two reference core transistors together and both connected to the power supply voltage terminal, the leakage current from the collectors of the two reference core transistors to the P-type substrate can be equal and both drawn from the power supply voltage terminal without affecting the magnitude of the core current. This avoids the reference voltage shift caused by the non-ideal factor of leakage current from the reverse-biased PN junction of the reference core transistors, thus improving the reliability of the bandgap reference circuit.

[0026] Figure 1 A schematic block diagram of a bandgap reference circuit 100 according to an embodiment of the present disclosure is shown. The bandgap reference circuit 100 includes a startup circuit 110, a bandgap reference core circuit 120, and a clamping operational amplifier circuit 130.

[0027] The startup circuit 110 can be coupled to the power supply voltage terminal VDD, the first bias current terminal Ib1, and the reference voltage output terminal Vbg. The startup circuit 110 can also be coupled to the bandgap reference core circuit 120 and the clamping operational amplifier circuit 130. The startup circuit 110 can be configured to generate a startup current based on the power supply voltage VDD from the power supply voltage terminal VDD and the first bias current Ib1 from the first bias current terminal Ib1, and provide the startup current to the reference voltage output terminal Vbg of the bandgap reference circuit 100 to pull the bandgap reference circuit 100 away from the degenerate state. In some embodiments of this disclosure, the startup circuit 110 provides the startup current to the reference voltage output terminal Vbg to pull the bandgap reference circuit 100 away from the degenerate state during the process of the power supply voltage VDD rising from zero volts to its stable state (startup phase). After the reference voltage Vbg is properly established, the startup circuit 110 can stop operating (stop outputting the startup current) to prevent the startup current from affecting the normal operation of the bandgap reference circuit 100.

[0028] The bandgap reference core circuit 120 can be coupled to the clamping operational amplifier circuit 130 via a first node A and a second node B. The bandgap reference core circuit 120 and the clamping operational amplifier circuit 130 can be jointly coupled to the reference voltage output terminal Vbg. The bandgap reference core circuit 120 can also be coupled to the power supply voltage terminal VDD. The bandgap reference core circuit 120 can be configured to generate a core current to control the voltages of the first node A and the second node B. The bandgap reference core circuit 120 may include a first transistor Q1 and a second transistor Q2. The collector of the first transistor Q1 and the collector of the second transistor Q2 are directly coupled to the power supply voltage terminal VDD. The base of the first transistor Q1 and the base of the second transistor Q2 are coupled to the reference voltage output terminal Vbg. The core current is the current flowing through the first transistor Q1 and the second transistor Q2. The first transistor Q1 and the second transistor Q2 are reference core transistors. In some embodiments of this disclosure, the first transistor Q1 and the second transistor Q2 are NPN bipolar transistors.

[0029] The clamping operational amplifier circuit 130 can be coupled to the bandgap reference core circuit 120 via a first node A and a second node B. The clamping operational amplifier circuit 130 can also be coupled to a first bias current terminal Ib1, a second bias current terminal Ib2, and a power supply voltage terminal VDD. The clamping operational amplifier circuit 130 can be configured to adjust the reference voltage Vbg based on the voltage difference between the first node A and the second node B, the first bias current Ib1, and the second bias current Ib2 from the second bias current terminal Ib2, so that the voltages of the first node A and the second node B are equal.

[0030] In practical applications, offset voltages may exist at the first node A and the second node B. In some embodiments of this disclosure, the clamping operational amplifier circuit 130 may also be configured to periodically use one of the following as the voltage difference between the first node A and the second node B: the voltage of the first node A minus the voltage of the second node B; and the voltage of the second node B minus the voltage of the first node A. In other words, in the first half of a cycle, the result of subtracting the voltage of the second node B from the voltage of the first node A is used as the voltage difference between the first node A and the second node B. Then, in the second half of a cycle, the result of subtracting the voltage of the first node A from the voltage of the second node B is used as the voltage difference between the first node A and the second node B. This allows the direction of the offset voltage to be periodically exchanged. By periodically exchanging the direction of the offset voltage, while ensuring that the loop polarity inside the clamping operational amplifier circuit 130 remains unchanged, the offset voltage of the clamping operational amplifier circuit 130 can be averaged to zero, thereby avoiding the adverse effects of introducing offset voltage into the reference voltage.

[0031] The embodiments of this disclosure further consider the effect of ambient temperature. The reference voltage Vbg decreases significantly when the ambient temperature is too high or too low. Figure 2A schematic block diagram of a bandgap reference circuit 200 according to an embodiment of the present disclosure is shown. The bandgap reference circuit 200 may further include a low-temperature compensation circuit 240. The low-temperature compensation circuit 240 is configured to raise the reference voltage Vbg when the temperature of the bandgap reference circuit 200 is below a first threshold temperature. The bandgap reference circuit 200 may further include a high-temperature compensation circuit 250. The high-temperature compensation circuit 250 is configured to raise the reference voltage Vbg when the temperature of the bandgap reference circuit 200 is above a second threshold temperature. The low-temperature compensation circuit 240 and / or the high-temperature compensation circuit 250 may be coupled to a clamping operational amplifier circuit 130 via a third node C. The low-temperature compensation circuit 240 and / or the high-temperature compensation circuit 250 can cause the clamping operational amplifier circuit 130 to adjust the reference voltage Vbg by changing the voltage of the third node C.

[0032] In cases where only one external bias current is available, the bandgap reference circuit 300 according to embodiments of the present disclosure may further include a bias current generating circuit 360. Figure 3 A schematic block diagram of a bandgap reference circuit 300 according to an embodiment of the present disclosure is shown. A bias current generation circuit 360 may be coupled to a second bias current terminal Ib2. The bias current generation circuit 360 may be configured to generate a first bias current Ib1 based on the second bias current Ib2 and output the first bias current Ib1 from the first bias current terminal Ib1. The bias current generation circuit 360 may be coupled to a startup circuit 110 and a clamping operational amplifier circuit 130 to provide the first bias current Ib1 to the startup circuit 110 and the clamping operational amplifier circuit 130.

[0033] Figure 4 Show Figure 3An exemplary circuit diagram of the bandgap reference circuit 300 is shown. The bandgap reference core circuit 420 may include: a first transistor Q1, a second transistor Q2, a first resistor R1, a second resistor R2, a third resistor R3, and a trimming resistor RT. The collector of the first transistor Q1 and the collector of the second transistor Q2 are coupled to the power supply voltage terminal VDD. The base of the first transistor Q1 and the base of the second transistor Q2 are coupled to the reference voltage output terminal Vbg. The first terminal of the first resistor R1 is coupled to the emitter of the first transistor Q1. The second terminal of the first resistor R1 is coupled to the first node A and the first terminal of the second resistor R2. The second terminal of the second resistor R2 is coupled to the first terminal of the trimming resistor RT. The second terminal of the trimming resistor RT is coupled to the second voltage terminal V2. The first terminal of the third resistor R3 is coupled to the emitter of the second transistor Q2 and the second node B. The second terminal of the third resistor R3 is coupled to the second voltage terminal V2. In some embodiments of this disclosure, the resistance value of the trimming resistor RT can be adjusted according to a preset ratio. In one example, the resistance value of the adjustment resistor RT could be r × k, where r represents the unit adjustment increment and k represents the scaling factor (e.g., 0 to 2). 5 In practical applications, the resistance values ​​of the first resistor R1 and the second resistor R2 may have errors. The resistance value of the adjustment resistor RT can be determined based on the ratio of the resistance values ​​of the second resistor R2 to the first resistor R1 in the actual application.

[0034] In some embodiments of this disclosure, the ratio of the emitter area of ​​the first transistor Q1 to the emitter area of ​​the second transistor Q2 is N:1. The ratio of the resistance values ​​of the second resistor R2 and the third resistor R3 is 1:1. N is greater than 1. In one example, N is 8. Since the clamping operational amplifier circuit 430 makes the voltage at the first node A equal to the voltage at the second node B, the voltage difference ΔVBE between the base-emitter voltage difference VBE1 of the first transistor Q1 and the base-emitter voltage difference VBE2 of the second transistor Q2 falls across the first resistor R1. Thus, the voltage difference across the first resistor R1 has a positive temperature coefficient, and therefore, the current flowing through the first resistor R1 also has a positive temperature coefficient. The reference voltage Vbg can be calculated as:

[0035]

[0036] In the above formula, Vbg represents the reference voltage, R1 represents the resistance value of the first resistor R1, R2 represents the resistance value of the second resistor R2, and RT represents the resistance value of the adjustment resistor RT. VBE2 has a negative temperature coefficient, and ΔVBE has a positive temperature coefficient. The superposition of the two can compensate for the temperature coefficient of the reference voltage Vbg, thereby achieving a reference voltage output with zero temperature coefficient.

[0037] The collector current of a transistor can usually be calculated using the following formula:

[0038]

[0039] Where k represents the Boltzmann constant, q represents the electron charge, Iso represents the reverse saturation current, T represents the temperature, and V represents the voltage. BE This represents the base-emitter voltage difference of a transistor.

[0040] According to equation (2), we can obtain in, This represents thermal voltage.

[0041] therefore,

[0042] Among them, I C1 I represents the collector current of the first transistor Q1. SO1 I represents the reverse saturation current of the first transistor Q1. C2 I represents the collector current of the second transistor Q2. SO2 This represents the reverse saturation current of the second transistor Q2.

[0043] Because the ratio of the emitter area of ​​the first transistor Q1 to the emitter area of ​​the second transistor Q2 is N:1, therefore, I SO1 =N×I SO2 , while I C2 =I C1 Therefore, VBE2 - VBE1 = V T ×lnN. Therefore:

[0044]

[0045] In the above equation, since VBE2 has a negative temperature coefficient, V T Having a positive temperature coefficient, the two combined can compensate for the temperature coefficient of the reference voltage Vbg, achieving a reference voltage output with zero temperature coefficient.

[0046] The inventors of this disclosure further discovered that chip packaging plays a crucial role in placing, fixing, sealing, protecting, and enhancing the electrothermal performance of the chip. However, the resulting packaging stress can also cause deviations in the performance of the internal circuitry of the chip, thereby affecting the chip's reliability. To obtain a sufficient positive temperature compensation coefficient, the ratio of the emitter area of ​​the first transistor Q1 to the emitter area of ​​the second transistor Q2 is set to N:1. Therefore, the first transistor Q1 and the second transistor Q2 exhibit different degrees of current deviation when subjected to packaging stress.

[0047] Some embodiments of this disclosure propose setting the ratio of the emitter area of ​​the first transistor Q1 to the emitter area of ​​the second transistor Q2 to 1:1, and setting the ratio of the resistance values ​​of the second resistor R2 and the third resistor R3 to N:1. N is greater than 1. In one example, N is 8. This also allows for obtaining a sufficient positive temperature compensation coefficient.

[0048] The collector current of a transistor affected by stress can be calculated using the following formula:

[0049]

[0050] in, c1 represents the stress coefficient, c2 represents the encapsulation material coefficient, c2 represents the stress direction coefficient, σ represents the stress amplitude, k represents the Boltzmann constant, q represents the electron charge, Iso is the reverse saturation current, T represents the temperature, and V represents the stress coefficient. BE This represents the base-emitter voltage difference of the transistor. Substituting equation (6) into equation (4) yields...

[0051]

[0052] Where, γ v1 γ represents the stress coefficient of the first transistor Q1. v2 This represents the stress coefficient of the second transistor Q2.

[0053] Substituting equation (7) into equation (1) yields

[0054]

[0055] Under the condition that the packaging stress on the first transistor Q1 and the second transistor Q2 is uniform and consistent, γ v1 With γ v2 Since they are equal, their effects cancel each other out, thus maintaining the output of the reference voltage as expressed in equation (5).

[0056] In some embodiments of this disclosure, the first transistor Q1 and the second transistor Q2 can be cross-matched on the layout of the chip where the bandgap reference circuit 400 is located, and the assistance of redundant devices and layout centering can be used to ensure that the packaging stress borne by the first transistor Q1 and the second transistor Q2 is uniform and consistent.

[0057] exist Figure 4In the example, the startup circuit 410 may include: a third transistor Q3, a fourth transistor M4, a fifth transistor M5, and a fourth resistor R4. The control terminal and the second terminal of the third transistor Q3 are coupled to the first terminal of the fourth transistor M4. The first terminal of the third transistor Q3 is coupled to the second voltage terminal V2. The control terminal and the second terminal of the fourth transistor M4 are coupled to the first bias current terminal Ib1. The control terminal of the fifth transistor M5 is coupled to the control terminal of the fourth transistor M4. The first terminal of the fifth transistor M5 is coupled to the reference voltage output terminal Vbg. The second terminal of the fifth transistor M5 is coupled to the first terminal of the fourth resistor R4. The second terminal of the fourth resistor R4 is coupled to the power supply voltage terminal VDD. In some embodiments of this disclosure, the resistance value of the fourth resistor R4 may be zero ohms.

[0058] During startup, the power supply voltage VDD rises from zero volts. The first bias current Ib1 from the first bias current terminal Ib1 is supplied to the fourth transistor M4, which is then mirrored to the fifth transistor M5. The current flowing through the fifth transistor M5 is supplied to the reference voltage output terminal Vbg. With the bandgap reference circuit 400 under load, the reference voltage Vbg is gradually increased. Because the voltage at the control terminal of the fifth transistor M5 is clamped by the third transistor Q3 and the fourth transistor M4, the fifth transistor M5 will turn off and no longer affect the reference voltage Vbg when the reference voltage Vbg is increased to a level where the voltage difference between the control terminal and the first terminal of the fifth transistor M5 is less than the threshold voltage of the fifth transistor M5.

[0059] The bias current generating circuit 460 may include: a sixth transistor M6 to a thirteenth transistor M13, a fifth resistor R5, and a sixth resistor R6. The first terminal of the fifth resistor R5 is coupled to the second bias current terminal Ib2, the control terminal of the sixth transistor M6, and the control terminal of the ninth transistor M9. The second terminal of the fifth resistor R5 is coupled to the second terminal of the sixth transistor M6, the control terminal of the seventh transistor M7, and the control terminal of the eighth transistor M8. The first terminal of the sixth transistor M6 is coupled to the second terminal of the seventh transistor M7. The first terminal of the seventh transistor M7 is coupled to the second voltage terminal V2 and the first terminal of the eighth transistor M8. The second terminal of the eighth transistor M8 is coupled to the first terminal of the ninth transistor M9. The second terminal of the ninth transistor M9 is coupled to the first terminal of the sixth resistor R6, the control terminal of the tenth transistor M10, and the control terminal of the thirteenth transistor M13. The second terminal of the sixth resistor R6 is coupled to the second terminal of the tenth transistor M10, the control terminal of the eleventh transistor M11, and the control terminal of the twelfth transistor M12. The first terminal of the tenth transistor M10 is coupled to the second terminal of the eleventh transistor M11. The first terminal of the eleventh transistor M11 is coupled to the power supply voltage terminal VDD and the first terminal of the twelfth transistor M12. The second terminal of the twelfth transistor M12 is coupled to the first terminal of the thirteenth transistor M13. The second terminal of the thirteenth transistor M13 is coupled to the first bias current terminal Ib1.

[0060] The low-temperature compensation circuit 440 may include: a fourteenth transistor M14 and a seventh resistor R7. The control terminal of the fourteenth transistor M14 is coupled to the control terminal of the third transistor Q3. The first terminal of the fourteenth transistor M14 is coupled to the first terminal of the seventh resistor R7. The second terminal of the fourteenth transistor M14 is coupled to the third node C, the second terminal of the thirty-third transistor M33, the control terminal of the thirty-ninth transistor M39, and the control terminal of the fortieth transistor M40. The second terminal of the seventh resistor R7 is coupled to the second voltage terminal V2.

[0061] The clamping operational amplifier circuit 430 may include: fifteenth transistor Q15 through forty-fifth transistor M45, a first capacitor C1, and eighth resistors R8 through tenth resistors R10. The control terminal of the fifteenth transistor Q15 is coupled to the first terminal of the seventeenth transistor Q17. The first terminal of the fifteenth transistor Q15 is coupled to the first terminal of the sixteenth transistor Q16 and the second terminal of the nineteenth transistor M19. The second terminal of the fifteenth transistor Q15 is coupled to the second terminal of the seventeenth transistor Q17, the first terminal of the eighth resistor R8, and the control terminal of the twenty-fourth transistor Q24. The control terminal of the sixteenth transistor Q16 is coupled to the first terminal of the eighteenth transistor Q18. The second terminal of the sixteenth transistor Q16 is coupled to the second terminal of the eighteenth transistor Q18, the first terminal of the ninth resistor R9, and the control terminal of the twenty-third transistor Q23. The control terminal of the seventeenth transistor Q17 is coupled to the second terminal of the forty-fourth transistor M44 and the second terminal of the forty-fifth transistor M45. The control terminal of the eighteenth transistor Q18 is coupled to the second terminal of the forty-second transistor M42 and the second terminal of the forty-third transistor M43. The second terminal of the eighth resistor R8 is coupled to the second voltage terminal V2 and the second terminal of the ninth resistor R9. The control terminal of the nineteenth transistor M19 is coupled to the control terminal of the tenth transistor M10. The first terminal of the nineteenth transistor M19 is coupled to the second terminal of the twentieth transistor M20. The control terminal of the twentieth transistor M20 is coupled to the control terminal of the eleventh transistor M11. The first terminal of the twentieth transistor M20 is coupled to the power supply voltage terminal VDD and the first terminal of the twenty-first transistor M21. The control terminal of the twenty-first transistor M21 is coupled to the control terminal of the eleventh transistor M11. The second terminal of the twenty-first transistor M21 is coupled to the first terminal of the twenty-second transistor M22. The control terminal of the twenty-second transistor M22 is coupled to the control terminal of the tenth transistor M10. The second terminal of the twenty-second transistor M22 is coupled to the first terminal of the twenty-third transistor Q23 and the first terminal of the twenty-fourth transistor Q24. The second terminal of the twenty-third transistor Q23 is coupled to the second terminal of the twenty-fifth transistor M25, the first terminal of the twenty-seventh transistor M27, and the first terminal of the twenty-eighth transistor M28. The second terminal of transistor Q24 is coupled to the second terminal of transistor M26 (26th), the first terminal of transistor M29 (29th), and the first terminal of transistor M30 (30th). The control terminal of transistor M25 (25th) is coupled to the control terminal of transistor M26 (26th) and transistor M7 (7th). The control terminal of transistor M27 (27th) is coupled to the control terminal of transistor M30 (30th) and the first clock signal terminal clkcb. The second terminal of transistor M27 (27th) is coupled to the second terminal of transistor M29 (29th) and the first terminal of transistor M31 (31st). The control terminal of transistor M28 (28th) is coupled to the control terminal of transistor M29 (29th) and the second clock signal terminal clkc. The second terminal of transistor M28 (28th) is coupled to the second terminal of transistor M30 (30th) and the first terminal of transistor M32 (32nd).The control terminal of transistor M31 (31st transistor) is coupled to the control terminal of transistor M32 (32nd transistor) and the second bias current terminal Ib2. The second terminal of transistor M31 (31st transistor) is coupled to the second terminal of transistor M33 (33rd transistor). The second terminal of transistor M32 (32nd transistor) is coupled to the second terminal of transistor M34 (34th transistor), the control terminal of transistor M41 (41st transistor), and the first terminal of capacitor C1. The control terminal of transistor M33 (33rd transistor) is coupled to the control terminal of transistor M34 (34th transistor). The first terminal of transistor M33 (33rd transistor) is coupled to the second terminals of transistors M35 (35th transistor) and M37 (37th transistor). The first terminal of transistor M34 (34th transistor) is coupled to the second terminals of transistors M36 (36th transistor) and M38 (38th transistor). The control terminal of transistor M35 (35th transistor) is coupled to the control terminal of transistor M38 (38th transistor) and the second clock signal terminal clkc. The first terminal of transistor M35 (35th transistor) is coupled to the first terminal of transistor M36 (36th transistor) and the second terminal of transistor M39 (39th transistor). The control terminal of transistor M36 (36th transistor) is coupled to the control terminal of transistor M37 (37th transistor) and the first clock signal terminal clkcb. The first terminal of transistor M37 (37th transistor) is coupled to the first terminal of transistor M38 (38th transistor) and the second terminal of transistor M40 (40th transistor). The first terminal of transistor M39 (39th transistor) is coupled to the first terminal of transistor M40 (40th transistor) and the power supply voltage terminal VDD. The first terminal of transistor M41 (41st transistor) is coupled to the reference voltage output terminal Vbg, and the second terminal of transistor M41 (41st transistor) is coupled to the first terminal of resistor R10 (10th resistor). The second terminal of capacitor C1 (11th capacitor) is coupled to the second voltage terminal V2. The second terminal of resistor R10 (10th resistor) is coupled to the power supply voltage terminal VDD. The control terminal of transistor M42 (42nd transistor) is coupled to the control terminal of transistor M45 (45th transistor) and the first clock signal terminal clkcb. The first terminal of transistor M42 (42nd transistor) is coupled to the emitter of transistor Q2 (2nd transistor) and the first terminal of transistor M44 (44th transistor). The control terminal of transistor M43 (43rd transistor) is coupled to the control terminal of transistor M44 (44th transistor) and the second clock signal terminal clkc. The first terminal of transistor M43 (43rd transistor) is coupled to the second terminal of resistor R1 (11th resistor) and the first terminal of transistor M45 (45th transistor). In some embodiments of this disclosure, the resistance value of the tenth resistor R10 can be zero ohms. The first clock signal clkcb output from the first clock signal terminal clkcb and the second clock signal clkc output from the second clock signal terminal clkc are inverse signals.

[0062] The high-temperature compensation circuit 450 may include: a forty-sixth transistor Q46, an eleventh resistor R11, a twelfth resistor R12, and a thirteenth resistor R13. The control terminal of the forty-sixth transistor Q46 is coupled to the first terminal of the eleventh resistor R11 and the first terminal of the twelfth resistor R12. The first terminal of the forty-sixth transistor Q46 is coupled to the first terminal of the thirteenth resistor R13. The second terminal of the forty-sixth transistor Q46 is coupled to the third node C and the second terminal of the thirty-third transistor M33. The second terminal of the eleventh resistor R11 is coupled to the reference voltage output terminal Vbg. The second terminal of the twelfth resistor R12 is coupled to the second voltage terminal V2 and the second terminal of the thirteenth resistor R13.

[0063] exist Figure 4 In the example, the power supply voltage from the power supply voltage terminal VDD rises from 0V to the normal operating voltage, and the second voltage terminal V2 is grounded. The first transistor Q1 to the third transistor Q3 and the forty-sixth transistor Q46 are NPN bipolar transistors. The fifteenth transistor Q15 to the eighteenth transistor Q18 and the twenty-third transistor Q23 to the twenty-fourth transistor Q24 are PNP bipolar transistors. The fourth transistor M4 to the ninth transistor M9, the fourteenth transistor M14, the twenty-fifth transistor M25 to the thirty-second transistor M32, and the forty-first transistor M41 to the forty-fifth transistor M45 are NMOS transistors. The tenth transistor M10 to the thirteenth transistor M13, the nineteenth transistor M19 to the twenty-second transistor M22, and the thirty-third transistor M33 to the fortieth transistor M40 are PMOS transistors. Those skilled in the art will understand that, based on the above inventive concept... Figure 4 Any modifications to the circuit shown should also fall within the scope of this disclosure. In such modifications, the transistor and voltage terminals may also have the same characteristics as described above. Figure 4 The examples shown have different settings.

[0064] Those skilled in the art should understand that Figure 4 The internal structure of each circuit in the example is exemplary, and it can also be implemented using other circuits.

[0065] As described above, offset voltages may exist at the first node A and the second node B. The first clock signal clkcb and the second clock signal clkc can be used to control the first node A and the second node B to be periodically (alternatingly) coupled to the control terminals of the seventeenth transistor Q17 and the eighteenth transistor Q18, respectively. This allows the direction of the offset voltage to be periodically exchanged, ensuring that the periodic average value of the offset voltage of the op-amp input pair (the seventeenth transistor Q17 and the eighteenth transistor Q18) is zero while maintaining the loop polarity. This avoids introducing the adverse effects of offset voltage into the reference voltage Vbg.

[0066] Figure 5 A schematic diagram of the temperature characteristics of the reference voltage Vbg output by the bandgap reference circuit 400 is shown. Curve Vbg1 represents the change of the reference voltage Vbg with temperature without the low-temperature compensation circuit 440 and the high-temperature compensation circuit 450. It can be observed that when the temperature is below the first threshold temperature T... L Or the temperature is higher than the second threshold temperature T. H Under these conditions, the reference voltage Vbg shows a significant decrease. Curve Vbg2 represents the change in reference voltage with temperature when both the low-temperature compensation circuit 440 and the high-temperature compensation circuit 450 are present.

[0067] When the temperature is below the first threshold temperature T L In this case, the threshold voltage of the third transistor Q3 increases, causing the fourteenth transistor M14 to conduct, thereby pulling down the voltage at the third node C. With the voltage at the third node C pulled down, the voltage at the control electrode of the forty-first transistor M41 increases, thereby pulling up the reference voltage Vbg. When the temperature is equal to or higher than the first threshold temperature T... L In this case, the threshold voltage of the third transistor Q3 is insufficient to turn on the fourteenth transistor M14. Therefore, the low temperature compensation circuit 440 does not work and does not affect the magnitude of the reference voltage Vbg.

[0068] When the temperature is above the second threshold temperature T H In this condition, the threshold voltage of the forty-sixth transistor Q46 decreases to the point that Q46 turns on, thereby pulling down the voltage at the third node C. With the voltage at the third node C pulled down, the voltage at the control electrode of the forty-first transistor M41 increases, thereby pulling up the reference voltage Vbg. When the temperature is equal to or below the second threshold temperature T... H In this case, the threshold voltage of the forty-sixth transistor Q46 is too high, insufficient to turn on the forty-sixth transistor Q46. Therefore, the high temperature compensation circuit 450 does not work and does not affect the magnitude of the reference voltage Vbg.

[0069] In summary, the bandgap reference circuit according to embodiments of this disclosure, by shifting two NPN-type reference core transistors to a higher position and connecting their collectors to the power supply voltage terminal, ensures that the leakage current from the collectors of the two reference core transistors to the P-type substrate is equal and both are drawn from the power supply voltage terminal without affecting the magnitude of the core current. This avoids the reference voltage shift caused by the non-ideal factor of leakage current from the reverse-biased PN junction of the reference core transistors, thus improving the reliability of the bandgap reference circuit. The bandgap reference circuit according to embodiments of this disclosure, by setting the emitter area ratio of the two reference core transistors to 1:1, avoids the influence of packaging stress on the current shift of the two reference core transistors. The bandgap reference circuit according to embodiments of this disclosure, by periodically changing the direction of the offset voltage, avoids the adverse effects of introducing offset voltage into the reference voltage. The bandgap reference circuit according to embodiments of this disclosure, by incorporating low-temperature compensation circuits and high-temperature compensation circuits, achieves relatively small reference voltage variations over a wide temperature range. The bandgap reference circuit according to embodiments of the present disclosure can provide a reliable and accurate reference voltage in circuit systems with wide temperature variations, large supply voltage amplitudes, and significant process drift effects.

[0070] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0071] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0072] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A bandgap reference circuit, comprising: The circuit includes a startup circuit, a bandgap reference core circuit, and a clamping operational amplifier circuit. The startup circuit is configured to generate a startup current based on the power supply voltage from the power supply voltage terminal and the first bias current from the first bias current terminal, and to provide the startup current to the reference voltage output terminal of the bandgap reference circuit to pull the bandgap reference circuit away from the degenerate state. The bandgap reference core circuit is configured to generate a core current to control the voltage of the first node and the second node. The clamping operational amplifier circuit is configured to adjust the reference voltage based on the voltage difference between the first node and the second node, the first bias current, and the second bias current from the second bias current terminal so that the voltages of the first node and the second node are equal. The bandgap reference core circuit includes a first transistor and a second transistor. The collectors of the first transistor and the second transistor are directly coupled to the power supply voltage terminal, and the bases of the first transistor and the second transistor are coupled to the reference voltage output terminal.

2. The bandgap reference circuit according to claim 1, wherein, The core circuit of the bandgap reference also includes: a first resistor, a second resistor, a third resistor, and an adjustment resistor. Wherein, the first end of the first resistor is coupled to the emitter of the first transistor, and the second end of the first resistor is coupled to the first node and the first end of the second resistor; The second end of the second resistor is coupled to the first end of the adjustment resistor; The second end of the adjustment resistor is coupled to the second voltage terminal; The first end of the third resistor is coupled to the emitter of the second transistor and the second node, and the second end of the third resistor is coupled to the second voltage terminal.

3. The bandgap reference circuit according to claim 2, wherein, The ratio of the emitter area of ​​the first transistor to the emitter area of ​​the second transistor is N:1, the ratio of the resistance values ​​of the second resistor to the third resistor is 1:1, and N is greater than 1.

4. The bandgap reference circuit according to claim 2, wherein, The ratio of the emitter area of ​​the first transistor to the emitter area of ​​the second transistor is 1:1, and the ratio of the resistance values ​​of the second resistor to the third resistor is N:1, where N is greater than 1.

5. The bandgap reference circuit according to claim 1, wherein, The clamping operational amplifier circuit is also configured to periodically use one of the following as the voltage difference between the first node and the second node: The voltage of the first node minus the voltage of the second node; and The voltage of the second node minus the voltage of the first node.

6. The bandgap reference circuit according to claim 1, wherein, The startup circuit includes: a third transistor, a fourth transistor, a fifth transistor, and a fourth resistor. The control electrode and the second electrode of the third transistor are coupled to the first electrode of the fourth transistor, and the first electrode of the third transistor is coupled to the second voltage terminal. The control electrode and the second electrode of the fourth transistor are coupled to the first bias current terminal. The control electrode of the fifth transistor is coupled to the control electrode of the fourth transistor, the first electrode of the fifth transistor is coupled to the reference voltage output terminal, and the second electrode of the fifth transistor is coupled to the first terminal of the fourth resistor; The second end of the fourth resistor is coupled to the power supply voltage terminal.

7. The bandgap reference circuit according to claim 1, further comprising: Low temperature compensation circuit The low-temperature compensation circuit is configured to raise the reference voltage when the temperature of the bandgap reference circuit is lower than the first threshold temperature.

8. The bandgap reference circuit according to claim 1, further comprising: High temperature compensation circuit The high-temperature compensation circuit is configured to increase the reference voltage when the temperature of the bandgap reference circuit is higher than the second threshold temperature.

9. The bandgap reference circuit according to claim 1, further comprising: Bias current generation circuit The bias current generating circuit is configured to generate the first bias current based on the second bias current, and output the first bias current from the first bias current terminal.

10. A bandgap reference circuit, comprising: The first to forty-sixth transistors, the first to thirteenth resistors, the first capacitor, and the adjustment resistor. Wherein, the collector of the first transistor and the collector of the second transistor are coupled to the power supply voltage terminal, and the base of the first transistor and the base of the second transistor are coupled to the reference voltage output terminal. The first end of the first resistor is coupled to the emitter of the first transistor, and the second end of the first resistor is coupled to the first end of the second resistor. The second end of the second resistor is coupled to the first end of the adjustment resistor; The second end of the adjustment resistor is coupled to the second voltage terminal; The first end of the third resistor is coupled to the emitter of the second transistor, and the second end of the third resistor is coupled to the second voltage terminal; The control electrode and the second electrode of the third transistor are coupled to the first electrode of the fourth transistor, and the first electrode of the third transistor is coupled to the second voltage terminal. The control electrode and the second electrode of the fourth transistor are coupled to the second electrode of the thirteenth transistor; The control electrode of the fifth transistor is coupled to the control electrode of the fourth transistor, the first electrode of the fifth transistor is coupled to the reference voltage output terminal, and the second electrode of the fifth transistor is coupled to the first terminal of the fourth resistor; The second end of the fourth resistor is coupled to the power supply voltage terminal; The first end of the fifth resistor is coupled to the second bias current terminal, the control terminal of the sixth transistor, and the control terminal of the ninth transistor; the second end of the fifth resistor is coupled to the second terminal of the sixth transistor, the control terminal of the seventh transistor, and the control terminal of the eighth transistor. The first terminal of the sixth transistor is coupled to the second terminal of the seventh transistor; The first terminal of the seventh transistor is coupled to the second voltage terminal and the first terminal of the eighth transistor; The second terminal of the eighth transistor is coupled to the first terminal of the ninth transistor; The second terminal of the ninth transistor is coupled to the first terminal of the sixth resistor, the control terminal of the tenth transistor, and the control terminal of the thirteenth transistor; The second terminal of the sixth resistor is coupled to the second terminal of the tenth transistor, the control terminal of the eleventh transistor, and the control terminal of the twelfth transistor; The first terminal of the tenth transistor is coupled to the second terminal of the eleventh transistor; The first terminal of the eleventh transistor is coupled to the power supply voltage terminal and the first terminal of the twelfth transistor; The second terminal of the twelfth transistor is coupled to the first terminal of the thirteenth transistor; The control electrode of the fourteenth transistor is coupled to the control electrode of the third transistor, the first electrode of the fourteenth transistor is coupled to the first terminal of the seventh resistor, and the second electrode of the fourteenth transistor is coupled to the second electrode of the thirty-third transistor, the control electrode of the thirty-ninth transistor, and the control electrode of the fortieth transistor. The second terminal of the seventh resistor is coupled to the second voltage terminal; The control terminal of the fifteenth transistor is coupled to the first terminal of the seventeenth transistor. The first terminal of the fifteenth transistor is coupled to the first terminal of the sixteenth transistor and the second terminal of the nineteenth transistor. The second terminal of the fifteenth transistor is coupled to the second terminal of the seventeenth transistor, the first terminal of the eighth resistor, and the control terminal of the twenty-fourth transistor. The control electrode of the sixteenth transistor is coupled to the first electrode of the eighteenth transistor, and the second electrode of the sixteenth transistor is coupled to the second electrode of the eighteenth transistor, the first terminal of the ninth resistor, and the control electrode of the twenty-third transistor. The control electrode of the seventeenth transistor is coupled to the second electrode of the forty-fourth transistor and the second electrode of the forty-fifth transistor; The control electrode of the eighteenth transistor is coupled to the second electrode of the forty-second transistor and the second electrode of the forty-third transistor; The second terminal of the eighth resistor is coupled to the second voltage terminal and the second terminal of the ninth resistor; The control electrode of the nineteenth transistor is coupled to the control electrode of the tenth transistor, and the first electrode of the nineteenth transistor is coupled to the second electrode of the twentieth transistor; The control electrode of the twentieth transistor is coupled to the control electrode of the eleventh transistor, and the first electrode of the twentieth transistor is coupled to the power supply voltage terminal and the first electrode of the twentieth transistor. The control electrode of the 21st transistor is coupled to the control electrode of the 11th transistor, and the second electrode of the 21st transistor is coupled to the first electrode of the 22nd transistor; The control electrode of the 22nd transistor is coupled to the control electrode of the 10th transistor, and the second electrode of the 22nd transistor is coupled to the first electrode of the 23rd transistor and the first electrode of the 24th transistor; The second terminal of the 23rd transistor is coupled to the second terminal of the 25th transistor, the first terminal of the 27th transistor, and the first terminal of the 28th transistor; The second terminal of the 24th transistor is coupled to the second terminal of the 26th transistor, the first terminal of the 29th transistor, and the first terminal of the 30th transistor; The control electrode of the 25th transistor is coupled to the control electrode of the 26th transistor and the control electrode of the 7th transistor; The control electrode of the 27th transistor is coupled to the control electrode of the 30th transistor and the first clock signal terminal, and the second electrode of the 27th transistor is coupled to the second electrode of the 29th transistor and the first electrode of the 31st transistor; The control electrode of the 28th transistor is coupled to the control electrode of the 29th transistor and the second clock signal terminal, and the second electrode of the 28th transistor is coupled to the second electrode of the 30th transistor and the first electrode of the 32nd transistor. The control electrode of the thirty-first transistor is coupled to the control electrode of the thirty-second transistor and the second bias current terminal; The second terminal of the thirty-first transistor is coupled to the second terminal of the thirty-third transistor; The second terminal of the thirty-second transistor is coupled to the second terminal of the thirty-fourth transistor, the control terminal of the forty-first transistor, and the first terminal of the first capacitor; The control electrode of the thirty-third transistor is coupled to the control electrode of the thirty-fourth transistor, and the first electrode of the thirty-third transistor is coupled to the second electrode of the thirty-fifth transistor and the second electrode of the thirty-seventh transistor; The first terminal of the thirty-fourth transistor is coupled to the second terminal of the thirty-sixth transistor and the second terminal of the thirty-eighth transistor; The control electrode of the thirty-fifth transistor is coupled to the control electrode of the thirty-eighth transistor and the second clock signal terminal, and the first electrode of the thirty-fifth transistor is coupled to the first electrode of the thirty-sixth transistor and the second electrode of the thirty-ninth transistor; The control electrode of the thirty-sixth transistor is coupled to the control electrode of the thirty-seventh transistor and the first clock signal terminal; The first terminal of the thirty-seventh transistor is coupled to the first terminal of the thirty-eighth transistor and the second terminal of the fortieth transistor; The first terminal of the thirty-ninth transistor is coupled to the first terminal of the fortieth transistor and the power supply voltage terminal; The first terminal of the forty-first transistor is coupled to the reference voltage output terminal, and the second terminal of the forty-first transistor is coupled to the first terminal of the tenth resistor. The second terminal of the first capacitor is coupled to the second voltage terminal; The second end of the tenth resistor is coupled to the power supply voltage terminal; The control electrode of the forty-second transistor is coupled to the control electrode of the forty-fifth transistor and the first clock signal terminal, and the first electrode of the forty-second transistor is coupled to the emitter of the second transistor and the first electrode of the forty-fourth transistor; The control electrode of the forty-third transistor is coupled to the control electrode of the forty-fourth transistor and the second clock signal terminal, and the first electrode of the forty-third transistor is coupled to the second terminal of the first resistor and the first electrode of the forty-fifth transistor; The control terminal of the forty-sixth transistor is coupled to the first terminal of the eleventh resistor and the first terminal of the twelfth resistor; the first terminal of the forty-sixth transistor is coupled to the first terminal of the thirteenth resistor; and the second terminal of the forty-sixth transistor is coupled to the second terminal of the thirty-third transistor. The second terminal of the eleventh resistor is coupled to the reference voltage output terminal; The second terminal of the twelfth resistor is coupled to the second voltage terminal and the second terminal of the thirteenth resistor.

Images