Low dropout without off chip capacitor LDO circuit

Abstract

The application relates to a low-dropout (LDO) circuit without external capacitor, which comprises a band-gap reference circuit, an error amplifier (EA), a buffer stage composed of a PMOS tube M1 and a PMOS tube M2, a power output stage composed of a power PMOS tube M0, a feedback resistor R1, a feedback resistor R2 and a compensation device, a substrate modulation amplifier and a protection circuit. The low-dropout (LDO) circuit without external capacitor provided by the application, on the basis of the prior art, on one hand, adopts a power adjustment tube substrate modulation technology to reduce the opening voltage of the power adjustment tube, thereby achieving the target of reducing the LDO voltage difference; on the other hand, adopts multiple protection circuits to increase the reliability of the LDO circuit.

Description

Technical Field

[0001] This invention relates to a low-dropout linear regulator circuit for use in power electronic systems, belonging to the field of integrated circuit technology. Background Technology

[0002] Consumer electronics have become an indispensable part of people's daily lives, with portable electronic devices playing a vital role. For any electronic device, a power source is essential to provide sufficient power for operation. This power source can be mains electricity from a power plant or energy stored in a battery. However, both mains and battery power supplies suffer from voltage instability and high noise. Therefore, to provide a reliable power supply for modern electronic devices, a power management chip is needed between the power source and the electronic device. This chip is responsible for the conversion, distribution, detection, voltage regulation, and noise reduction of electrical energy. The power management chip is indispensable to electronic systems, and its performance directly impacts the overall performance of the device.

[0003] Power supply chips are mainly divided into linear regulators and switching power converters. Most electronic products cannot be directly powered by AC power and require AC-DC conversion. However, current AC-DC converters often struggle to provide stable outputs, necessitating a voltage converter. Common voltage converters include low-dropout linear regulators (LDOs) and inductor-based DC-DC converters. Compared to DC-DC converters, LDOs offer advantages such as simpler structure, lower power consumption, lower high-frequency noise, and smaller size for easier integration. The power requirements of various electronic products differ. For example, mobile phones and communication systems require low noise and low ripple characteristics, and due to system integration needs, they also require small board space and simple peripheral circuitry. In these cases, low-dropout linear regulators are the most suitable choice. To meet these requirements, chips typically possess the following technical characteristics: a precise voltage reference, low quiescent current, low-dropout regulator transistors, high-performance, low-noise operational amplifiers, and stable and fast loop response.

[0004] like Figure 1 As shown, a basic LDO has three pins: input voltage Vin (VDD), output voltage V, and so on. OUT The LDO's submodules mainly include a reference circuit, an error amplifier (EA), a power transistor (pass element), and a feedback network. The reference circuit provides a reference voltage V for the error amplifier and other auxiliary circuits. REF and reference current I REFThe reference circuit comprises two modules: a current reference circuit and a voltage reference circuit. The current reference circuit generates a reference current unaffected by the supply voltage. The voltage reference circuit obtains a temperature-independent reference voltage by weighted summing the emitter-base voltage of a PNP transistor with a negative temperature coefficient and a thermal voltage with a positive temperature coefficient. An error amplifier amplifies the difference between the bandgap reference voltage and the LDO feedback voltage, inputting it to the gate of the power transistor to control the output voltage. The accuracy, transient response, and load current of the LDO's output voltage are directly affected by the error amplifier. When the load changes, the power transistor stabilizes the output voltage by altering its on-resistance. The feedback loop compensation circuit, including a resistor string and a compensation network, provides output voltage control and feedback network stability.

[0005] exist Figure 1 In traditional LDO chips, an external load capacitor is required at the output to suppress overcharge voltage and stabilize the internal loop. For applications requiring low noise, low ripple, and no electromagnetic interference, this external capacitor necessitates dedicated pins on the chip for connection to external capacitors. This not only wastes chip space (primarily for protection circuitry) but also increases board area and overhead. Furthermore, parasitic inductance and antenna effects on the chip-package interconnects can degrade output voltage quality. To address these issues, LDO chips without external load capacitors have become a popular design approach.

[0006] An LDO has a minimum input voltage requirement for normal operation. Only when the input voltage exceeds this minimum value can the regulating transistor operate in the saturation region, enabling the circuit to automatically regulate the output voltage. The voltage difference represents the difference between the output voltage and the minimum input voltage when the output reaches a stable state. During normal operation, the input voltage cannot be lower than the sum of the voltage difference and the output voltage. When the LDO operates in the regulation region, the circuit can stabilize the output voltage at the set value, preventing it from changing with the input voltage. When the input voltage falls below the critical value, the LDO enters the linear region; further decreases in input voltage will lead to a decrease in output voltage, weakening the feedback loop's regulatory capability. As the input voltage decreases further, the LDO enters the cutoff region, at which point the circuit ceases to function. Therefore, LDO circuit design must minimize the voltage difference to achieve the widest possible input voltage range. Summary of the Invention

[0007] Based on existing technology, this invention provides an LDO circuit with ultra-low dropout voltage characteristics and no external capacitor.

[0008] The overall structure of the low dropout capacitor-free LDO circuit provided by the present invention includes: a bandgap reference circuit, an error amplifier, a buffer stage composed of PMOS transistors M1 and M2, a power output stage composed of power PMOS transistor M0, feedback resistor R1, feedback resistor R2 and compensation device, as well as a substrate modulation amplifier and a protection circuit.

[0009] The bandgap reference circuit generates a reference voltage V. REF Bias voltage V B and reference voltage V B1 Reference voltage V REF Connect the negative terminal of the error amplifier and the protection circuit respectively, and connect the positive terminal of the error amplifier to the feedback voltage V. FB The error amplifier is based on the reference voltage V. REF and feedback voltage V FB Output error amplification signal V EA It is connected to the input terminal of the buffer stage, i.e., the gate of PMOS transistor M2. The source of PMOS transistor M2 is connected to the drain of PMOS transistor M1, and serves as the output terminal of the buffer stage, outputting V. G It is connected to the input terminal of the power output stage, that is, the gate of the power PMOS transistor M0, and the gate of the PMOS transistor M1 is connected to the bias voltage V. B The power output stage internally includes: the source of power PMOS transistor M0 and the source of PMOS transistor M1 are connected to the power supply voltage VDD; the drain of power PMOS transistor M0 is connected to the upper end of feedback resistor R1 and serves as the output port of the LDO circuit, outputting Vout, and is also connected to a compensation device that serves as a frequency stabilizer; the lower end of feedback resistor R1 is connected to the upper end of feedback resistor R2 and serves as the feedback voltage V. FB The generation node, the lower end of feedback resistor R2, and the drain of PMOS transistor M2 are connected to ground at voltage VSS; the power output stage is based on V G The output voltage Vout and feedback voltage V of the LDO circuit are generated by the state of the power supply voltage VDD. FB The substrate modulation amplifier is a differential amplifier circuit with differential input and single-ended output. One differential input terminal of the substrate modulation amplifier is connected to a reference voltage V. REF The other differential input is connected to the feedback voltage V. FB The output of the substrate modulation amplifier is connected to the substrate of the power PMOS transistor M0; the protection circuit is used to monitor the chip's operating temperature, voltage, current status, and reference voltage V. REF By comparison, the chip status output signal is obtained.

[0010] Specifically, the bandgap reference circuit includes: a bias startup circuit, PMOS transistors Mr1 and Mr2, resistors Rr1, Rr2, Rr3, Rr4, and Rr5, diodes D1 and D2, operational amplifier A1, and a bias voltage output circuit. The PMOS transistors Mr1 and Mr2, resistors Rr1, Rr2, and Rr3, diodes D1 and D2, and operational amplifier A1 constitute a bandgap voltage generation core circuit. The input bias voltage of the bandgap voltage generation core circuit is the gate voltage Vbr1 of PMOS transistor Mr1 and the gate voltage Vbr2 of PMOS transistor Mr2. The gates of PMOS transistors Mr1 and Mr2 are respectively connected to... The bias startup circuit has two bias voltage output terminals. The source of PMOS transistor Mr1 is connected to the power supply VDD, and the drain of PMOS transistor Mr1 is connected to the source of PMOS transistor Mr2. The drain of PMOS transistor Mr2 is connected to the upper ends of resistors Rr1 and Rr2, outputting a bandgap voltage. The lower end of resistor Rr1 is connected to the positive terminal of operational amplifier A1 and the anode of diode D1. The lower end of resistor Rr2 is connected to the negative terminal of operational amplifier A1 and then connected to the anode of diode D2 through resistor Rr3. The cathodes of diodes D1 and D2 are both grounded. The output terminal of operational amplifier A1 is connected to the gate of PMOS transistor Mr1. ​​The bandgap voltage output from the source of PMOS transistor Mr2 is connected to the upper end of resistor Rr5, and the lower end of resistor Rr5 is grounded through resistor Rr4, outputting a reference voltage V. B1 The two bias voltage output terminals of the bias startup circuit are also connected to the input terminals of the bias voltage output circuit; the output bandgap voltage of the bandgap voltage generation core circuit is the reference voltage. V REF The reference voltage V is generated by voltage division through resistors Rr4 and Rr5. B1 The bias startup circuit has a power-on startup function. During power-on, it first provides an initial input bias voltage Vbr1 and Vbr2, which control the gates of PMOS transistors Mr1 and Mr2, respectively. After power-on, the bias voltage output circuit generates a bias voltage Vb1 based on the bias voltages Vb1 and Vb2. B .

[0011] Specifically, the bias startup circuit includes: PMOS transistors M51, M55, M56, M58, M510, M515, NMOS transistors M52, M53, M54, M57, M59, M511, M512, M513, and M514; the gate of PMOS transistor M51 is connected to the drain of PMOS transistor M51, the drain of NMOS transistor M52, the drain of NMOS transistor M53, and NMOS transistor M514. The gates of transistors M54 and M55 are connected to those of transistors M54, M55, M56, M57, M58, and M59, forming a three-stage cascaded inverter chain. The drain of PMOS transistor M55 is connected to the drain of NMOS transistor M54, the gate of PMOS transistor M56, and the gate of NMOS transistor M57. The drain of PMOS transistor M56 is connected to the drain of NMOS transistor M57, the gate of PMOS transistor M58, and the gate of NMOS transistor M59. The drain of PMOS transistor M58 is connected to the drain of NMOS transistor M59, thus functioning as an inverter. The output of the inverter chain is connected to the gates of NMOS transistors M52, M53, M511, M512, M513, and M514. The input of the inverter chain is the gate of PMOS transistor M51. The drain of NMOS transistor M511 is connected to the drain and gate of PMOS transistors M510 and serves as the output of the bias voltage Vbr1. The source of NMOS transistor M511 is connected to the drain of NMOS transistor M512. The drain of NMOS transistor M514 is connected to the drain of PMOS transistor M515. The gate of PMOS transistor M515 is connected to the output terminal of bias voltage Vbr2, and the source of NMOS transistor M514 is connected to the drain of NMOS transistor M513. The sources of PMOS transistors M51, M55, M56, M58, M510, and M515 are all connected to the power supply voltage VDD. The sources of NMOS transistors M52, M53, M54, M57, M59, M512, and M513 are all connected to the ground voltage VSS.

[0012] Specifically, the protection circuit includes: an over-temperature protection circuit, an under-voltage protection circuit, an over-current protection circuit, and an error handling logic circuit; the temperature protection signal output by the over-temperature protection circuit, the under-voltage protection signal output by the under-voltage protection circuit, and the over-current protection signal output by the over-current protection circuit are simultaneously connected to the input terminal of the error handling logic circuit, and the chip status output signal is obtained after logic processing; when any one or more of the temperature protection signal, under-voltage protection signal, and over-current protection signal are abnormal, the chip status output signal will output an error status signal, otherwise it will output a normal status signal.

[0013] The advantages of this invention are: the low dropout voltage LDO circuit without external capacitor provided by this invention, based on the prior art, firstly adopts power regulator substrate modulation technology to reduce the turn-on voltage of the power regulator, thereby achieving the goal of reducing the LDO dropout voltage; in addition, it adopts a variety of protection circuits to increase the reliability of the LDO circuit. Attached Figure Description

[0014] Figure 1 This is a block diagram of a typical LDO circuit system.

[0015] Figure 2 This is a block diagram of the low dropout capacitor-free LDO circuit system of the present invention.

[0016] Figure 3 This is an embodiment of the error amplifier circuit of the present invention.

[0017] Figure 4 This is an embodiment of the bandgap reference circuit of the present invention.

[0018] Figure 5 for Figure 4 Schematic diagram of the mid-biased startup circuit.

[0019] Figure 6 This is a structural block diagram of an embodiment of the protection circuit of the present invention.

[0020] Figure 7 for Figure 6 Block diagram of an embodiment of the over-temperature protection circuit.

[0021] Figure 8 for Figure 6 Block diagram of an embodiment of the undervoltage protection circuit.

[0022] Figure 9 for Figure 6 Block diagram of an embodiment of an overcurrent protection circuit. Detailed Implementation

[0023] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0024] like Figure 2As shown, the low dropout capacitor-free LDO circuit of the present invention includes: a bandgap reference circuit 1, an error amplifier 2, a buffer stage composed of PMOS transistors M1 and M2, a power output stage composed of a power PMOS transistor M0, feedback resistors R1 and R2, and a compensation device 4, and a substrate modulation amplifier composed of NMOS transistors M3, M4, M5, M6, and M7.

[0025] The bandgap reference circuit 1 generates a reference voltage V. REF Bias voltage V B and reference voltage V B1 Error amplifier 2 is based on the reference voltage V. REF and feedback voltage V FB This generates an error amplification signal V. EA And connect it to the input of the buffer stage. The output of the buffer stage is V. G It is connected to the input terminal of the power output stage, that is, the gate of the power PMOS transistor M0; the power output stage is based on V G The state of the power supply voltage VDD generates the overall LDO circuit's output voltage Vout and feedback voltage V. FB One differential input of the substrate modulation amplifier is connected to the reference voltage V. REF The other differential input is connected to the feedback voltage V. FB The output of the substrate modulation amplifier is connected to the substrate of the power PMOS transistor M0. The protection circuit 3 is used to detect the chip status and the reference voltage V. REF By comparison, the chip status output signal Error is obtained.

[0026] The internal connections of the power output stage are as follows: the sources of power PMOS transistors M0 and M1 are connected to the power supply voltage VDD; the drain of power PMOS transistor M0 is connected to the upper end of feedback resistor R1 and serves as the output port Vout of the LDO, and is also connected to the frequency compensation device 4; the lower end of feedback resistor R1 is connected to the upper end of feedback resistor R2 and serves as the feedback voltage V. FB The generation node; the lower end of the feedback resistor R2 is connected to the ground voltage VSS.

[0027] The substrate modulation amplifier is a typical 5-transistor single-stage differential amplifier circuit. The same function can also be achieved by using a two-stage amplifier with higher gain. The buffer stage is a source follower circuit with PMOS input, which provides a certain driving capability and signal isolation.

[0028] Figure 2 In the circuit shown, the resistor string formed by feedback resistors R1 and R2 detects the LDO output voltage and feeds it back to the input of error amplifier 2, which is compared with the input reference voltage V.REF Error comparison is performed, and the gate voltage of the regulating transistor M0 is locked after passing through a buffer stage to form a stable output voltage of the LDO. V out Unlike conventional LDO circuits, the substrate of the regulating transistor M0 in the power output stage of this invention is modulated by an operational amplifier. By adjusting the substrate voltage of the power PMOS transistor M0, the turn-on voltage Vth of M0 is adjusted, thereby reducing the minimum voltage drop between VDD and Vout and achieving ultra-low dropout performance. For example, the turn-on voltage Vth of a 5V PMOS device is typically around 0.7V, and the resulting LDO dropout is usually 1V. However, by modulating the substrate voltage of M0 to 3V using substrate modulation technology, the substrate and source voltages of M0 become negative, and the Vth voltage will be reduced to around 0.4V, thus achieving an LDO dropout that can typically be reduced to 0.7V.

[0029] Figure 3 This is an embodiment of the error amplifier 2 of the present invention. PMOS transistors M41, M42, M43, NMOS transistors M46, M47, M44, M45, M48, M49, M410, and M411 constitute a folded cascode operational amplifier to maximize gain. PMOS transistors M412 and M413 constitute a wide-swing output stage circuit. The positive and negative input terminals of error amplifier 2 are respectively connected to the reference voltage V. REF and feedback voltage V FB Connected.

[0030] Figure 4 This is an embodiment of the bandgap reference circuit 1 of the present invention. The bandgap reference circuit 1 includes: a bias startup circuit 401, PMOS transistors Mr1 and Mr2, resistors Rr1, Rr2, Rr3, Rr4, and Rr5, diodes D1 and D2, operational amplifier A1, and a bias voltage output circuit 402. Specifically, PMOS transistors Mr1 and Mr2, resistors Rr1, Rr2, and Rr3, diodes D1 and D2, and operational amplifier A1 constitute a bandgap voltage generation core circuit. The input bias voltage of the bandgap voltage generation core circuit is the gate voltage Vbr1 of PMOS transistor Mr1 and the gate voltage Vbr2 of PMOS transistor Mr2. The output bandgap voltage of the bandgap voltage generation core circuit is... V REF bandgap voltage V REF That is, the reference voltage V REF The reference voltage V is generated by voltage division through resistors Rr4 and Rr5. B1The bias startup circuit 401 has a power-on startup function. During power-on, it first provides an initial input bias voltage Vbr1 and Vbr2, which control the gates of PMOS transistors Mr1 and Mr2 respectively, thereby starting the bandgap voltage generation core circuit. After power-on, the operational amplifier A1 inside the bandgap voltage generation core circuit will control the Vbr1 voltage. At this time, the bias voltages Vbr1 and Vbr2 will remain unchanged and are temperature-insensitive reference voltages. The bias voltage output circuit 402 generates the bias voltage V based on the bias voltages Vbr1 and Vbr2. B .

[0031] Figure 5 This is a schematic diagram of the bias startup circuit 401 of the present invention. The bias startup circuit 401 includes: PMOS transistors M51, M55, M56, M58, M510, M515, NMOS transistors M52, M53, M54, M57, M59, M511, M512, M513, and M514.

[0032] The gate and drain of PMOS transistor M51 are connected, and then connected to the drain of NMOS transistor M52, the drain of NMOS transistor M53, the gate of NMOS transistor M54, and the gate of PMOS transistor M55. PMOS transistors M55, M56, M58, M54, M57, and M59 form a three-stage cascaded inverter chain. The input end of the inverter chain is point A, which is the connection point between the gate and drain of PMOS transistor M51, and the output end of the inverter chain is the connection point between the drain of PMOS transistor M58 and the drain of NMOS transistor M59. The output of the inverter chain is also connected to the gates of NMOS transistors M52, M53, M511, M512, M513, and M514; the drain of NMOS transistor M511 is connected to the gate and drain of PMOS transistor M510, and serves as the output of bias voltage Vbr1; the source of NMOS transistor M511 is connected to the drain of NMOS transistor M512; the drain of NMOS transistor M514 is connected to the gate and drain of PMOS transistor M515, and serves as the output of bias voltage Vbr2; the source of NMOS transistor M514 is connected to the drain of NMOS transistor M513.

[0033] The sources of PMOS transistors M51, M55, M56, M58, M510, and M515 are all connected to the power supply voltage VDD; the sources of NMOS transistors M52, M53, M54, M57, M59, M511, M512, M513, and M514 are all connected to the ground voltage VSS.

[0034] like Figure 6 As shown, the protection circuit 3 of the present invention includes: an over-temperature protection circuit 61, an under-voltage protection circuit 62, an over-current protection circuit 63, and an error handling logic circuit 64. The temperature protection signal OTLock output by the over-temperature protection circuit 61, the under-voltage protection signal UVLock output by the under-voltage protection circuit 62, and the over-current protection signal OCLock output by the over-current protection circuit 63 are simultaneously connected to the input terminal of the error handling logic circuit 64, and the chip status output signal Error is obtained after logic processing. When any one or more of the temperature protection signal OTLock, the under-voltage protection signal UVLock, and the over-current protection signal OCLock are abnormal, the chip status output signal Error will output an error status signal; otherwise, Error will output a normal status signal.

[0035] Figure 7 This is a block diagram of an embodiment of the over-temperature protection circuit 61 of the present invention, consisting of a comparator CMP1, a shaping circuit, an inverter INV81, and a PNP transistor Q. THE Resistance R THE1 Resistance R THE2 MOSFET M THE Bias current I bias1 and I bias2 The circuit consists of components such as transistor Q1 and PNP transistor Q2. This over-temperature protection circuit 61 utilizes the negative temperature characteristic of the emitter-base voltage of a PNP transistor to sense temperature. THE The emitter is connected to the positive input of comparator CMP1, and resistor R... THE1 and R THE2 Forming a series connection, R THE1 The low potential terminal of the MOSFET M THE The source terminal of the transistor is connected to the high-potential terminal, which is connected to the inverting input terminal of comparator CMP1. The output terminal of comparator CMP1 is connected to the MOSFET M. THE The gate of the comparator is set to output an over-temperature protection signal. When the internal temperature of the chip is within the normal range, the voltage Vin+ at the positive input terminal of the comparator CMP1 is set to be greater than the voltage Vin- at the negative input terminal, and the output voltage V of the comparator CMP1 is set to be V.THE is at a high level, and the MOS transistor M THE is turned on. At this time, Vin- = I bias2 ·R THE2 . When the chip temperature rises to T > TH, due to the negative temperature characteristic of the emitter-base voltage of the PNP bipolar transistor, the positive input voltage of the comparator CMP1 decreases, Vin+ < Vin-, the output voltage of the comparator CMP1 flips to a low level "0", the output voltage of the inverter INV81 is at a high level "1", and the OTLock signal is "1". The chip returns to the normal working state. At this time, the MOS transistor M THE is turned on again, and Vin- = I bias2 ·R THE2 .

[0036] When the internal temperature of the chip is too high, it will cause irreversible damage to the chip. Therefore, over-temperature protection of the chip is required. The over-temperature protection circuit 61 sets a temperature sensor device in the circuit. When the temperature T exceeds the threshold temperature TH, it generates a signal and turns off the chip. When the temperature T drops below the threshold temperature TL, it generates a signal and turns on the chip. For safety considerations, TL needs to be lower than TH. Therefore, the over-temperature protection circuit 61 has hysteresis, that is, the threshold temperature TH for turning off the circuit by the over-temperature protection circuit 61 is greater than the threshold temperature TL for restarting the circuit. When TH > TL, the circuit can achieve the hysteresis function required for over-temperature protection.

[0037] Figure 8 is a structural block diagram of an embodiment of the under-voltage protection circuit 62 of the present invention. Its structure includes: a voltage detection circuit 81, a comparator circuit 82, and a shaping circuit 83. The voltage detection circuit 81 outputs a power supply voltage detection output signal Vin-uv; the comparator circuit 82 compares the reference voltage signal V REF with the power supply voltage detection output signal Vin-uv to obtain a comparison output signal Vo-uv; the shaping circuit 83 processes the comparison output signal Vo-uv to obtain an under-voltage protection signal UVLocks. UVLocks is a digital logic signal. UVLocks will be connected to the input end of the voltage detection circuit 81 to control the magnitude of the power supply voltage detection output signal Vin-uv. UVLocks also serves as a control input signal and is output to the error handling logic circuit 64 at the same time.

[0038] When the power supply voltage of the chip is normal, the under-voltage protection signal UVLocks is at a low level. The low level of UVLocks will control the voltage detection circuit 81 to generate a relatively high power supply voltage detection output signal Vin-uv; under normal circumstances, the comparator circuit 82 is based on the reference voltage V REFThe output signal Vo-uv obtained from the power supply voltage detection output signal Vin-uv should be a high-level signal; the shaping circuit 83 processes Vo-uv to obtain the undervoltage protection signal UVLock as a low-level logic signal. When the chip power supply voltage is abnormal, the power supply voltage detection output signal Vin-uv detected by the voltage detection circuit 81 will change, generating a lower power supply voltage detection output signal Vin-uv; the comparator circuit 82 determines the lower power supply voltage detection output signal based on the reference voltage V. REF The output signal Vo-uv, obtained from the power supply voltage detection output signal Vin-uv, becomes a low-level signal. The undervoltage protection signal UVLock obtained by the shaping circuit 83 changes to a high-level logic signal. The high level of UVLock will control the voltage detection circuit 81 to generate a lower power supply voltage detection output signal Vin-uv. The voltage Vin will further lock the comparison output signal Vo-uv of the comparator circuit 82 to a high-level signal. The specific implementation of the voltage detection circuit 81, comparator circuit 82, and shaping circuit 83 can use existing technology and will not be described here.

[0039] Figure 9 This is a block diagram of an embodiment of the overcurrent protection circuit 63 of the present invention. The circuit structure is similar to... Figure 8 The undervoltage protection circuit structure of the present invention is similar, including a current detection circuit, a comparator circuit, and a shaping circuit connected in sequence. The overcurrent protection circuit 63 has a similar structure. Figure 8 Compared to the given undervoltage protection circuit 62, the difference is that a current sampling circuit is used to detect the magnitude of the current of the output power device. The obtained sampling current is usually converted into a voltage Vinc through a resistor. This voltage is output to the comparator circuit and compared with the reference voltage signal V. REF The comparison signal Voc is then input to the shaping circuit for processing, and finally outputs the overcurrent protection signal OClock. OClock is connected to the input of the current detection circuit to provide feedback control to Vinc, and also serves as a control input signal output to the error handling logic circuit 64. Its working principle is similar to that of the undervoltage protection circuit 62, and will not be described further here.

[0040] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. Low dropout LDO circuit without external capacitors, including: The bandgap reference circuit (1), the error amplifier (2), the buffer stage composed of PMOS transistors M1 and M2, the power output stage composed of power PMOS transistor M0 and feedback resistors R1, R2 and compensation device (4), and the substrate modulation amplifier and protection circuit (3). The bandgap reference circuit (1) generates a reference voltage V. REF Bias voltage V B and reference voltage V B1 Reference voltage V REF The negative terminal of the error amplifier (2) and the protection circuit (3) are connected respectively, and the positive terminal of the error amplifier (2) is connected to the feedback voltage V. FB The error amplifier (2) is based on the reference voltage V REF and feedback voltage V FB Output error amplification signal V EA It is connected to the input terminal of the buffer stage, i.e., the gate of PMOS transistor M2. The source of PMOS transistor M2 is connected to the drain of PMOS transistor M1, and serves as the output terminal of the buffer stage, outputting V. G It is connected to the input terminal of the power output stage, that is, the gate of the power PMOS transistor M0, and the gate of the PMOS transistor M1 is connected to the bias voltage V. B The power output stage includes: the source of power PMOS transistor M0 and the source of PMOS transistor M1 connected to the power supply voltage VDD; the drain of power PMOS transistor M0 connected to the upper end of feedback resistor R1 and serving as the output port of LDO circuit, outputting Vout; and also connected to compensation device (4) which plays a role in frequency stabilization; the lower end of feedback resistor R1 connected to the upper end of feedback resistor R2 and serving as the feedback voltage VDD. FB The generation node, the lower end of feedback resistor R2, and the drain of PMOS transistor M2 are connected to ground at voltage VSS; the power output stage is based on V G The output voltage Vout and feedback voltage V of the LDO circuit are generated by the state of the power supply voltage VDD. FB The substrate modulation amplifier is a differential amplifier circuit with differential input and single-ended output. One differential input terminal of the substrate modulation amplifier is connected to a reference voltage V. REF The other differential input is connected to the feedback voltage V. FB The output of the substrate modulation amplifier is connected to the substrate of the power PMOS transistor M0; the protection circuit (3) is used to monitor the chip's operating temperature, voltage, current status and reference voltage V. REF By comparison, the chip status output signal is obtained.

2. The low-dropout LDO circuit without external capacitors according to claim 1, characterized in that, The bandgap reference circuit (1) includes: a bias start-up circuit (401), PMOS transistors Mr1 and Mr2, resistors Rr1, Rr2, Rr3, Rr4, and Rr5, diodes D1 and D2, operational amplifier A1, and a bias voltage output circuit (402); wherein, PMOS transistors Mr1 and Mr2, resistors Rr1, Rr2, and Rr3, diodes D1 and D2, and operational amplifier A1 constitute a bandgap voltage generation core circuit, and the input bias voltage of the bandgap voltage generation core circuit is the gate voltage Vbr1 of PMOS transistor Mr1 and the gate voltage Vbr2 of PMOS transistor Mr2, and the gates of PMOS transistors Mr1 and Mr2 are respectively... Connect the two bias voltage output terminals of the bias start-up circuit (401). The source of PMOS transistor Mr1 is connected to the power supply VDD, and the drain of PMOS transistor Mr1 is connected to the source of PMOS transistor Mr2. The drain of PMOS transistor Mr2 is connected to the upper ends of resistors Rr1 and Rr2, and outputs a bandgap voltage. The lower end of resistor Rr1 is connected to the positive terminal of operational amplifier A1 and the anode of diode D1. The lower end of resistor Rr2 is connected to the negative terminal of operational amplifier A1 and then connected to the anode of diode D2 through resistor Rr3. The cathodes of diodes D1 and D2 are both grounded. The output terminal of operational amplifier A1 is connected to the gate of PMOS transistor Mr1. ​​The bandgap voltage output from the source of PMOS transistor Mr2 is connected to the upper end of resistor Rr5. The lower end of resistor Rr5 is grounded through resistor Rr4 and outputs a reference voltage V. B1 The two bias voltage output terminals of the bias startup circuit (401) are also connected to the input terminals of the bias voltage output circuit (402); the output bandgap voltage of the bandgap voltage generating core circuit is the reference voltage. V REF The reference voltage V is generated by voltage division through resistors Rr4 and Rr5. B1 The bias startup circuit (401) has a power-on startup function. During the power-on process, it first provides an initial input bias voltage Vbr1 and Vbr2 to control the gates of PMOS transistors Mr1 and Mr2, respectively. After power-on, the bias voltage output circuit (402) generates a bias voltage Vb1 based on the bias voltages Vb1 and Vb2. B .

3. The low-dropout LDO circuit without external capacitors according to claim 2, characterized in that, The bias start-up circuit (401) includes: PMOS transistors M51, M55, M56, M58, M510, M515, NMOS transistors M52, M53, M54, M57, M59, M511, M512, M513, and M514; the gate of PMOS transistor M51 is connected to the drain of PMOS transistor M51, the drain of NMOS transistor M52, the drain of NMOS transistor M53, and NMOS transistor M54. The gates of MOSFET M54 and PMOS transistor M55 are connected. NMOS transistors M54, M55, M56, M57, M58, and M59 form a three-stage cascaded inverter chain. The drain of PMOS transistor M55 is connected to the drain of NMOS transistor M54, the gate of PMOS transistor M56, and the gate of NMOS transistor M57. The drain of PMOS transistor M56 is connected to the drain of NMOS transistor M57, the gate of PMOS transistor M58, and the gate of NMOS transistor M59. The drain of PMOS transistor M58 is connected to the drain of NMOS transistor M59, thus functioning as an inverter. The output of the inverter chain is connected to the gates of NMOS transistors M52, M53, M511, M512, M513, and M514. The input of the inverter chain is the gate of PMOS transistor M51. The drain of NMOS transistor M511 is connected to the drain and gate of PMOS transistors M510 and serves as the output of the bias voltage Vbr1. The source of NMOS transistor M511 is connected to the drain of NMOS transistor M512. The drain of NMOS transistor M514 is connected to the drain of PMOS transistor M515. The gate of PMOS transistor M515 is connected to the output terminal of bias voltage Vbr2, and the source of NMOS transistor M514 is connected to the drain of NMOS transistor M513. The sources of PMOS transistors M51, M55, M56, M58, M510, and M515 are all connected to the power supply voltage VDD. The sources of NMOS transistors M52, M53, M54, M57, M59, M512, and M513 are all connected to the ground voltage VSS.

4. The low-dropout LDO circuit without external capacitors according to claim 1, characterized in that, The protection circuit (3) includes: an over-temperature protection circuit (61), an under-voltage protection circuit (62), an over-current protection circuit (63), and an error handling logic circuit (64). The temperature protection signal output by the over-temperature protection circuit (61), the under-voltage protection signal output by the under-voltage protection circuit (62), and the over-current protection signal output by the over-current protection circuit (63) are simultaneously connected to the input terminal of the error handling logic circuit (64) and processed by logic to obtain the chip status output signal. When any one or more of the temperature protection signal, under-voltage protection signal, and over-current protection signal are abnormal, the chip status output signal will output an error status signal; otherwise, it will output a normal status signal.

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