An FPGA design method based on partition debugging kernel voltage

Abstract

The application discloses a FPGA design method based on partition debugging kernel voltage, and relates to the technical field of FPGA.The method downloads the code stream corresponding to the chip hardware design including the internal circuit of the chip and a plurality of power supply regions to the FPGA chip, each power supply region is used for providing the acquired kernel voltage to the corresponding local power consumption region, when the chip cannot normally work in the state that the kernel voltage of the basic voltage value is acquired in all power supply regions, the kernel voltage acquired by at least one power supply region is adjusted through the power supply pin of the chip until the chip normally works, or until the local power consumption region with the fault is determined.The method can make the chip work normally or can be positioned to the fault region by adjusting the kernel voltage of the plurality of power supply regions, and the partition debugging method has high flexibility, is easier to debug, makes the chip work normally, or can be more accurately positioned to the fault region.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of FPGA, and in particular to an FPGA design method based on partition debugging kernel voltage. BACKGROUND

[0002] In the design process of FPGA (Field Programmable Gate Array, field programmable gate array), when the user design is completed by using a software tool, and the user netlist is subjected to design processes such as synthesis, mapping, layout, routing and timing analysis, it is determined that the function and timing can meet the requirements, the code stream corresponding to the obtained chip hardware design needs to be generated and downloaded to the FPGA board for actual measurement.

[0003] Although repeated checking and verification are performed by using various software tools in the design stage, the FPGA may still not work normally in the actual measurement stage. In some cases, the code stream can be modified by modifying the user netlist or modifying the layout and routing to increase the timing margin so that the FPGA works normally. However, in some cases, the FPGA still cannot work normally after increasing the timing margin, and at this time, the FPGA needs to be debugged.

[0004] The debugging of the FPGA generally first checks whether the external connection structure is correct, including checking whether each pin of the FPGA is connected correctly, whether each input signal including the power supply voltage is correct, whether the reset and power-on sequence is correct, whether the clock signal is correct, and the like. After it is determined that the external connection structure of the FPGA is correct, it is determined that the chip internal circuit causes the FPGA to not work normally. However, the chip internal structure is not as intuitive and easy to troubleshoot as the external connection structure, the control ability and observation ability of the chip internal circuit are limited, and the available debugging means are limited, which often causes debugging difficulties. SUMMARY

[0005] The present application relates to the field of FPGA, and in particular to an FPGA design method based on partition debugging kernel voltage.

[0006] An FPGA design method based on partition debugging kernel voltage, the design method comprising:

[0007] Obtaining a chip hardware design, the chip hardware design comprising a chip internal circuit and a plurality of power supply regions, each power supply region corresponding to a local power consumption region of the chip internal circuit, and each power supply region being configured to provide a kernel voltage obtained by a power supply input end to a corresponding local power consumption region;

[0008] Generating a code stream corresponding to the chip hardware design and downloading the code stream to an FPGA chip, and the power supply input end of each power supply region being connected to a power supply pin of the FPGA chip.

[0009] When the FPGA chip cannot work normally in the state that the core voltage of the FPGA chip obtains the basic voltage value in all power supply regions, the core voltage obtained by at least one power supply region is adjusted through the power supply pin of the FPGA chip until the FPGA chip works normally or until it is determined that there is a faulty local power consumption region in the FPGA chip.

[0010] A further technical solution is that the method for adjusting the core voltage obtained by at least one power supply region comprises:

[0011] controlling the core voltage of all power supply regions to be boosted or reduced according to a predetermined voltage variation mode until the FPGA chip works normally or until the core voltage reaches a threshold voltage corresponding to the predetermined voltage variation mode while the FPGA chip still cannot work normally, thereby determining that there is a fault in the internal circuit of the FPGA chip corresponding to the predetermined voltage variation mode;

[0012] controlling the core voltage of part of the power supply regions to remain at the basic voltage value and the core voltage of the remaining part of the power supply regions to vary according to a predetermined voltage variation mode until the FPGA chip works normally or until it is determined that there is a local power consumption region with a fault corresponding to the predetermined voltage variation mode.

[0013] A further technical solution is that the method for controlling the core voltage of the power supply region to be boosted or reduced according to a predetermined voltage variation mode comprises:

[0014] controlling the core voltage of the power supply region to be gradually boosted from the basic voltage value until the FPGA chip works normally or until the core voltage reaches an upper threshold voltage while the FPGA chip still cannot work normally, thereby determining that there is a fault in the internal circuit of the FPGA chip that does not meet the setup time constraint;

[0015] and controlling the core voltage of the power supply region to be gradually reduced from the basic voltage value until the FPGA chip works normally or until the core voltage reaches a lower threshold voltage while the FPGA chip still cannot work normally, thereby determining that there is a fault in the internal circuit of the FPGA chip that does not meet the hold time constraint.

[0016] A further technical solution is that when the core voltage of each power supply region is adjusted until the FPGA chip works normally, the core voltages determined by at least two power supply regions are not equal.

[0017] A further technical solution is that the method for controlling the core voltage of each power supply region according to a predetermined strategy comprises:

[0018] The kernel voltages of the rest of the power supply regions are kept as the basic voltage value, the kernel voltage of the power supply region being traversed is controlled to change according to the predetermined voltage change mode, until the FPGA chip works normally; or until the kernel voltage of the power supply region being traversed reaches the threshold voltage corresponding to the predetermined voltage change mode and the FPGA chip still cannot work normally, it is determined that the local power consumption region corresponding to the power supply region being traversed has the fault corresponding to the predetermined voltage change mode.

[0019] The further technical solution is that the method for controlling the kernel voltages of the power supply regions according to the predetermined strategy comprises:

[0020] The kernel voltages of the rest of the power supply regions are kept as the basic voltage value, the kernel voltage of the power supply region being traversed is controlled to change according to the predetermined voltage change mode, until the FPGA chip works normally; or until the kernel voltage of the power supply region being traversed reaches the threshold voltage corresponding to the predetermined voltage change mode and the FPGA chip still cannot work normally, it is determined that the local power consumption region corresponding to the power supply region being traversed has the fault corresponding to the predetermined voltage change mode.

[0021] The further technical solution is that the method for controlling the kernel voltages of the power supply regions according to the predetermined strategy comprises:

[0022] All the power supply regions are taken as initial fault candidate regions;

[0023] The fault candidate regions are divided into two sub candidate regions, and each sub candidate region contains a plurality of power supply regions;

[0024] The kernel voltages of all the power supply regions in one of the sub candidate regions are kept as the basic voltage value, and the kernel voltages of all the power supply regions in the other sub candidate region are controlled to change according to the predetermined voltage change mode, until the FPGA chip works normally;

[0025] When the kernel voltages of all the power supply regions in the sub candidate region reach the threshold voltage corresponding to the predetermined voltage change mode and the FPGA chip still cannot work normally, the sub candidate region is taken as an updated fault candidate region, and the step of dividing the fault candidate region into two sub candidate regions is re-executed, until an iteration condition is reached, it is determined that the local power consumption region corresponding to the power supply region in the fault candidate region has the fault corresponding to the predetermined voltage change mode.

[0026] The further technical solution is that the power supply input ends of two adjacent power supply regions are connected through a separation switch tube, and the method further comprises:

[0027] After the core voltage of each power supply area is adjusted to make the FPGA chip work normally, the isolation switch between the power supply input terminals of the multiple power supply areas with equal core voltage is turned on, and the isolation switch between the power supply input terminals of the multiple power supply areas with unequal core voltage is turned off.

[0028] A further technical solution is that the power supply input terminals of all the power supply areas are connected to the power supply pins of the FPGA chip through voltage adjustment circuits respectively, and the method for providing the core voltage to each power supply area comprises the following steps:

[0029] The power supply pins of the FPGA chip are provided with a basic voltage value, and the voltage adjustment circuit connected to the power supply input terminal of each power supply area is used to adjust the basic voltage value to a corresponding size of the core voltage input to the corresponding power supply area.

[0030] A further technical solution is that the voltage adjustment circuit comprises a voltage boosting unit, a voltage reducing unit and a direct connection unit, and the method further comprises the following steps:

[0031] The voltage adjustment circuit connected to the power supply input terminal of each power supply area is configured through a configuration bit or through a metal option of a re-distribution layer during packaging, the voltage boosting unit in the voltage adjustment circuit is enabled to boost the input basic voltage value and provide it to the corresponding power supply area, or the voltage reducing unit in the voltage adjustment circuit is enabled to reduce the input basic voltage value and provide it to the corresponding power supply area, or the direct connection unit in the voltage adjustment circuit is enabled to directly provide the input basic voltage value to the corresponding power supply area.

[0032] A further technical solution is that the method further comprises the following steps:

[0033] The voltage boosting unit or the voltage reducing unit is configured through a metal option of a re-distribution layer or a configuration pin to adjust the voltage value provided by the voltage boosting unit or the voltage reducing unit to the corresponding power supply area.

[0034] A further technical solution is that the FPGA chip is a multi-die structure, the FPGA chip comprises a silicon connection layer and a plurality of dies stacked on the silicon connection layer; each power supply area corresponds to a local power consumption area of the internal circuit of the chip located in one die; and the voltage adjustment circuit is arranged in the silicon connection layer.

[0035] The beneficial technical effects of the present application are as follows:

[0036] The application discloses an FPGA design method based on partition debugging of core voltage, which can solve the internal structure problem of a chip represented as not meeting a setup time constraint or not meeting a hold time constraint by adjusting the core voltage of a plurality of power supply areas in the FPGA chip for supplying power to internal circuits of the chip, so that the FPGA chip can be debugged to work normally or a fault area can be located. Moreover, the application implements partition power supply for the internal circuits of the FPGA chip, so that the internal circuits can be debugged in partitions, and the flexibility of debugging is high, and the FPGA chip can be more easily debugged to work normally or a fault area can be more accurately located. The method provides an efficient and feasible method for debugging of the FPGA chip in a real measurement stage.

[0037] The method can realize more fine partition debugging by dividing more partitions in the FPGA chip, can improve the success rate of debugging, and is more beneficial to finding a fault part of the internal circuits of the chip. In view of the problem of a current path being cut off due to more partitions, the method can use a separation switch tube before different power supply areas to form a current path with a wider coverage and being connected as much as possible under the condition of meeting the demand of the core voltage of different local power consumption areas, so as to reduce the hidden danger caused by current concentration.

[0038] The plurality of power supply areas can each occupy a power supply pin to realize adjustment of the core voltage of the external control, or can share a power supply pin to realize adjustment of the core voltage in combination with an internal voltage adjustment circuit, so that the chip internal structure problem of the FPGA chip can be corrected and solved in the chip, and the FPGA chip does not need to be reflowed.

[0039] The method can be applied not only to a single-die structure but also to a multi-die structure, has strong applicability, and can use a silicon connection layer to arrange the voltage adjustment circuit connected by each power supply area, has a simple implementation manner, and does not need to occupy too many internal resources of the die. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1 FIG. 1 is a method flowchart of an FPGA design method in an embodiment of the application.

[0041] Figure 2 FIG. 2 is a structural schematic diagram of a plurality of power supply areas in an FPGA chip in an embodiment.

[0042] Figure 3 FIG. 3 is a method flowchart of adjusting the core voltage obtained by at least one power supply area in an embodiment of the application.

[0043] Figure 4 FIG. 4 is a structural schematic diagram of a plurality of power supply areas in an FPGA chip in another embodiment.

[0044] Figure 5 is a structural diagram of a plurality of power supply regions inside an FPGA chip in another embodiment. DETAILED DESCRIPTION

[0045] The specific embodiments of the application will be further described below with reference to the accompanying drawings.

[0046] The application discloses an FPGA design method based on partition debugging kernel voltage, please refer to the flow chart shown in the figure, the method comprises the following steps: Figure 1

[0047] Step 120, obtaining a chip hardware design, the chip hardware design comprising a chip internal circuit and a plurality of power supply regions.

[0048] Each power supply region corresponds to a local power consumption region of the chip internal circuit, and each power supply region is configured to provide the kernel voltage Vcore obtained by the power supply input end to the corresponding local power consumption region. The chip hardware design in the application can be considered as a result of modifying the power supply network after the conventional pre-tapeout chip hardware design. The conventional pre-tapeout chip hardware design comprises a chip internal circuit and a global power supply network, and the global power supply network is configured to provide the obtained kernel voltage Vcore to the entire chip internal circuit. In the application, the global power supply network is divided into a plurality of power supply regions, and the chip internal circuit is divided into a plurality of local power consumption regions. The kernel voltage Vcore obtained by the plurality of power supply regions is provided to the plurality of local power consumption regions, thereby achieving the isolation and partition of internal power supply.

[0049] Step 140, generating a code stream corresponding to the chip hardware design and downloading the code stream to the FPGA chip, and the power supply input end of each power supply region is connected to the power supply pin of the FPGA chip. Please refer to Figure 2 For example, M power supply regions are divided inside the FPGA chip, and the power supply input ends of the M power supply regions are respectively connected to a power supply pin to obtain kernel voltages Vcore1-VcoreM from outside the chip.

[0050] Step 160, providing the kernel voltage Vcore of the basic voltage value Vcc to all power supply regions in the FPGA chip. If the FPGA chip can work normally in this state, no debugging is required, and the actual measurement of the FPGA chip can be completed. The application mainly aims at the case that the FPGA chip cannot work normally when the FPGA chip obtains the kernel voltage Vcore of the basic voltage value Vcc in all power supply regions. At this time, as described in the background art, the external connection structure of the FPGA chip is generally first checked. When it is determined that the external connection structure of the FPGA chip is correct, the following step 180 is executed for debugging.

[0051] ​Step 180, adjust the core voltage Vcore obtained by at least one power supply area through the power supply pin of the FPGA chip until the FPGA chip works normally, or until it is determined that there is a faulty local power consumption area in the FPGA chip.

[0052] In the case where it is determined that the external connection structure of the FPGA chip is correct, it can be determined that the internal circuit of the chip causes the FPGA chip to fail to work normally. Since the hardware design of the chip has been repeatedly checked and verified by various tools, the possibility of functional error is generally very low, and the more likely cause is the physical internal structure problem of the FPGA chip, mainly in the following directions: (1) manufacturing process is unstable, some defective chips are out of the working range, and such chips are used during debugging. (2) The physical design of the chip has defects, resulting in insufficient power supply in the local area of the chip, and the voltage is too low to exceed the normal working range. (3) The timing parameters used by the software tool are not accurate enough, resulting in that some critical paths are reported to be satisfied, but in the chip real object, they are still not satisfied. (4) The timing margin is too low, and due to process variation, some chips can work and some chips cannot work, and the currently used chip cannot work. These internal structure problems of the chip often appear in the form of setup time or hold time, so debugging based on the debugging method of the timing path with setup time or hold time problem can determine that there is the above-mentioned internal structure problem of the chip, although it cannot be determined which of the above-mentioned internal structure of the chip causes the above-mentioned internal structure of the chip, but through debugging, the timing path with setup time or hold time problem can be solved. If most of the FPGA chips can work normally after such debugging, it can be considered that the tape-out is successful, and mass production can be entered. If most of the FPGA chips still cannot work normally after such debugging, the chip hardware design needs to be modified and re-taped to solve the problem.

[0053] Therefore, based on the above idea, the method for adjusting the core voltage Vcore obtained by at least one power supply area includes the following processes, please refer to the flow chart shown in Figure 3

[0054] Firstly, control the core voltage Vcore of all power supply areas to be boosted or reduced according to the predetermined voltage variation mode until the FPGA chip works normally. Or when the core voltage Vcore reaches the threshold voltage corresponding to the predetermined voltage variation mode and the FPGA chip still cannot work normally, it is determined that there is a fault in the internal circuit of the FPGA chip corresponding to the predetermined voltage variation mode.

[0055] ​Then, the core voltage Vcore of part of the power supply regions is kept as the base voltage value Vcc according to a predetermined strategy, and the core voltage Vcore of the rest of the power supply regions is changed according to a predetermined voltage change mode until the FPGA chip works normally, or until a local power consumption region with a fault corresponding to the predetermined voltage change mode is determined, thereby accurately locating the local power consumption region with the fault.

[0056] Based on the debugging method for the timing path with problems in the setup time or the hold time, the above debugging method includes the following two parts, and the execution sequence of the two parts of debugging can be configured by the user:

[0057] (1) Debugging for the timing path with problems in the setup time, the predetermined voltage change mode is gradually increasing from the base voltage value Vcc, and the fault corresponding to the predetermined voltage change mode is the fault of not meeting the setup time constraint. Therefore, the above debugging process is as follows:

[0058] The core voltage Vcore of all power supply regions is gradually increased from the base voltage value Vcc until the FPGA chip works normally. Or when the core voltage Vcore reaches the upper threshold voltage Vmax and the FPGA chip still cannot work normally, it is determined that there is a fault in the chip internal circuit of the FPGA chip that does not meet the setup time constraint.

[0059] Then, the core voltage Vcore of part of the power supply regions is kept as the base voltage value Vcc according to a predetermined strategy, and the core voltage Vcore of the rest of the power supply regions is changed according to a predetermined voltage change mode until the FPGA chip works normally, or until a local power consumption region with a fault corresponding to the predetermined voltage change mode is determined, thereby accurately locating the local power consumption region with the fault.

[0060] When the voltage of the core voltage Vcore obtained by the internal circuit of the chip is increased, the delay of the internal circuit of the chip is reduced and the speed is increased. For example, in actual application, when the core voltage Vcore of some FPGA chip is increased by 5%, the delay can be reduced by about 6%. Thus, by increasing the core voltage Vcore obtained by the internal circuit of the chip, the timing path with a problem of setup time can be solved. However, the core voltage Vcore of each power supply region also has a normal voltage range. The voltage range of the core voltage Vcore is generally defined as Vmin~Vmax, Vmin=Vcc-V1, and Vmax=Vcc+V2, wherein V1 and V2 are determined by the process, and the purpose is to not damage the internal circuit of the chip. For example, when Vcc=1.0V, V1=0.2V, and V2=0.3V, the voltage range of the core voltage Vcore is 0.8V~1.3V. The debugging process of the present application also needs to be performed within the voltage range of the core voltage Vcore. Thus, when the core voltage Vcore is increased from Vcc to Vmax and the FPGA chip still cannot work normally, it can be determined that the FPGA chip has a problem. In an embodiment, when the core voltage Vcore of any one power supply region is gradually increased from the basic voltage value Vcc, the voltage is increased according to a predetermined step, for example, the voltage is increased according to a predetermined step of 0.05V.

[0061] (2) Debugging of the timing path with a problem of hold time, the predetermined voltage change mode is gradually decreasing from the basic voltage value Vcc, and the fault corresponding to the predetermined voltage change mode is a fault of not meeting the hold time constraint. Thus, the above debugging process is as follows:

[0062] The core voltage Vcore of all power supply regions is gradually decreased from the basic voltage value Vcc until the FPGA chip works normally. Or until the core voltage Vcore reaches the lower threshold voltage Vmin and the FPGA chip still cannot work normally, it is determined that the internal circuit of the FPGA chip has a fault of not meeting the hold time constraint.

[0063] Then, according to a predetermined strategy, the core voltage Vcore of part of the power supply regions is kept as the basic voltage value Vcc, and the core voltage Vcore of the remaining power supply regions is gradually decreased from the basic voltage value Vcc until the FPGA chip works normally, or until the local power supply region with a fault of not meeting the hold time constraint is determined, so as to accurately locate the local power supply region with the fault.

[0064] In the above two debugging processes, if the FPGA chip can work normally by boosting or reducing the core voltage Vcore of the local power supply area, the problem of the FPGA chip can be solved by changing the core voltage Vcore of the corresponding power supply area to the corresponding voltage value. Since the present application does not supply power to the entire internal circuit of the chip through the global power supply network, the local power supply area can be debugged by partitioning the local power supply area. The required core voltage Vcore determined by the debugging of each local power supply area corresponding to the power supply area is not completely equal, and there can be at least two core voltages Vcore determined by the debugging of the power supply area, including the following differences: the core voltage Vcore of some power supply areas can be greater than the basic voltage value Vcc, the core voltage Vcore of some power supply areas can be less than the basic voltage value Vcc, and the core voltage Vcore of some power supply areas can be equal to the basic voltage value Vcc, that is, one or more of the above three cases can exist. Even if the required core voltage Vcore of the power supply area is greater than the basic voltage value Vcc, the voltage values of the required core voltage Vcore determined by the debugging of any two power supply areas are equal or unequal, such as the voltage value of the required core voltage Vcore determined by the debugging of one power supply area is Vcc+0.15V, and the voltage value of the required core voltage Vcore determined by the debugging of another power supply area is Vcc+0.05V. Similarly, even if the required core voltage Vcore of the power supply area is less than the basic voltage value Vcc, the voltage values of the required core voltage Vcore determined by the debugging of any two power supply areas are equal or unequal, such as the voltage value of the required core voltage Vcore determined by the debugging of one power supply area is Vcc-0.05V, and the voltage value of the required core voltage Vcore determined by the debugging of another power supply area is Vcc-0.10V.

[0065] The partition debugging method of the application can accurately debug the problematic local power consumption area. If the entire chip internal circuit is powered by the global power supply network, the core voltage Vcore of the entire chip internal circuit needs to be adjusted during adjustment. The overall voltage boost or voltage drop of the core voltage Vcore of the entire chip internal circuit can solve the existing problems of not meeting the setup time constraint or not meeting the hold time constraint, but it is also easy to cause new problems in other areas that do not originally exist, resulting in the FPGA chip being unable to debug to normal work. The partition debugging method of the application can respectively boost or drop or keep the core voltage of each local power consumption area, or even boost the core voltage of part of the local power consumption area, drop the core voltage of part of the local power consumption area, and keep the Vcc of part of the local power consumption area unchanged. The debugging method is flexible, which is more conducive to debugging so that the FPGA chip can work normally. Moreover, the method of the application can locate the local power consumption area with faults, and the area range of the problem is smaller, which is more conducive to finding the fault area.

[0066] Whether it is to control the core voltage Vcore to gradually boost to solve the setup time constraint fault, or to control the core voltage Vcore to gradually drop to solve the hold time constraint fault, in the above two debugging processes, the method of controlling the core voltage Vcore of each power supply area according to the predetermined strategy includes the following:

[0067] Method one, sequentially traversing each power supply area, keeping the core voltage Vcore of the remaining power supply area as the basic voltage value Vcc, controlling the core voltage Vcore of the traversed power supply area to change according to the predetermined voltage change mode, until the FPGA chip works normally. Or until the core voltage Vcore of the traversed power supply area reaches the threshold voltage corresponding to the predetermined voltage change mode and the FPGA chip still cannot work normally, it is determined that the local power consumption area corresponding to the traversed power supply area has the fault corresponding to the predetermined voltage change mode, thereby accurately locating the local power consumption area with faults.

[0068] Method two, sequentially traversing each power supply area, keeping the core voltage Vcore of the traversed power supply area as the basic voltage value, controlling the core voltage Vcore of the remaining power supply area to change according to the predetermined voltage change mode, until the FPGA chip works normally. Or until the core voltage of the remaining power supply area reaches the threshold voltage corresponding to the predetermined voltage change mode and the FPGA chip still cannot work normally, it is determined that the local power consumption area corresponding to the remaining power supply area has the fault corresponding to the predetermined voltage change mode. This method is similar to the above method one, except that the adjustment logic is reversed. Method one changes the core voltage Vcore of the traversed power supply area, while method two changes the core voltage Vcore of the non-traversed power supply area.

[0069] Method three, in the form of dichotomy, first all power supply regions are taken as initial fault candidate regions, then the fault candidate regions are divided into two sub candidate regions, each of which contains several power supply regions. The core voltage Vcore of all power supply regions in one of the sub candidate regions is kept as the basic voltage value Vcc, and the core voltage Vcore of all power supply regions in the other sub candidate region is controlled to change synchronously according to the predetermined voltage change mode until the FPGA chip works normally. When the core voltage Vcore of all power supply regions in one sub candidate region reaches the threshold voltage corresponding to the predetermined voltage change mode and the FPGA chip still cannot work normally, the sub candidate region is taken as the updated fault candidate region, that is, it can be determined that there is a faulty power supply region in the sub candidate region. Then the above step of dividing the fault candidate region into two sub candidate regions is executed cyclically until the iteration condition is reached, and it is determined that the local power consumption region corresponding to the power supply region in the final fault candidate region has the fault corresponding to the predetermined voltage change mode. The iteration condition can be the total number of iterations or the fault candidate region reaching the preset region size.

[0070] Based on the method provided in the present application, the more the number of power supply regions and local power consumption regions, that is, the more the internal partitions of the chip, the more flexible the partition debugging, the more conducive to debugging to the FPGA chip to work normally, and the smaller the range of the problem area defined, the more conducive to finding the chip problem origin. However, the more partitions, the more scattered the current path of the global power supply network inside the FPGA chip will be, which is prone to current concentration problems, so in order to avoid the performance degradation caused thereby, in another embodiment, the power supply input terminals of two adjacent power supply regions are connected through a partitioning switch tube P1, and the partitioning switch tube P1 can be realized by using a PMOS tube. When adjusting and determining the core voltage Vcore of each power supply region, all partitioning switch tubes P1 are disconnected, so that the core voltage Vcore of each power supply region can be adjusted independently without affecting each other. After adjusting and determining the core voltage Vcore of each power supply region to make the FPGA chip work normally, the partitioning switch tubes P1 between the power supply input terminals of multiple power supply regions with equal core voltage Vcore are turned on, and the partitioning switch tubes P1 between the power supply input terminals of multiple power supply regions with unequal core voltage Vcore are turned off, so that multiple power supply regions can be connected to provide more current paths on the basis of meeting the required core voltage Vcore of each power supply region.

[0071] For example, in Figure 4In the experiment, assuming that after debugging, Vcore1 = 1.05V, Vcore2 = 1.05V, and Vcore3 = 0.90V are determined, then after debugging, the separator switch P1 between the two power supply areas corresponding to Vcore1 and Vcore2 is turned on to connect and form a larger power supply area, providing more current paths. Meanwhile, the separator switch P1 between the two power supply areas corresponding to Vcore2 and Vcore3 is turned off to maintain the independence of the power supply from the two power supply areas to the corresponding local power consumption areas.

[0072] As described above, the power input terminal of each power supply region is connected to the power supply pin of the FPGA chip. In one embodiment, each power supply region occupies at least one independent power supply pin. When a power supply region occupies multiple power supply pins, the voltages of the multiple power supply pins it occupies need to be the same. This allows direct control of the core voltage Vcore obtained from each power supply region from outside the FPGA chip. However, to achieve more flexible partitioned debugging, the more partitions the FPGA chip has, the more power supply regions it has, and the more power supply pins it requires. Therefore, in another embodiment, such as... Figure 5 As shown, the power input terminals of all power supply areas are connected to the same power supply pin of the FPGA chip via voltage regulation circuits. The FPGA chip obtains a reference voltage value Vcc from the outside through this power supply pin. The method for providing the core voltage to each power supply area includes providing a base voltage value Vcc to the power supply pin of the FPGA chip, and the voltage regulation circuit connected to the power input terminal of each power supply area adjusting the base voltage value Vcc to a corresponding core voltage input to the corresponding power supply area. In this embodiment, when implementing more partitions, the occupation of the FPGA chip's power supply pins can be reduced. The externally input voltage value to the power supply pin is still Vcc, but the voltage value provided to each power supply area is adjusted by the voltage regulation circuits inside the FPGA chip.

[0073] like Figure 5As shown, the voltage regulation circuit includes a boost unit, a buck unit and a direct connection unit, wherein the boost unit can be implemented by a DC / DC unit, the buck unit can be implemented by an LDO unit, and the direct connection unit can be implemented by a PMOS tube. The method further includes: configuring the voltage regulation circuit connected to the power supply input end of each power supply region by configuring bits or by metal options of the redistribution layer during packaging, and selecting the boost unit in the voltage regulation circuit to boost the input basic voltage value Vcc and provide it to the corresponding power supply region, or selecting the buck unit in the voltage regulation circuit to step down the input basic voltage value Vcc and provide it to the corresponding power supply region, or selecting the direct connection unit in the voltage regulation circuit to directly provide the input basic voltage value to the corresponding power supply region. Further, the boost unit or the buck unit is configured by the metal options of the redistribution layer or the configuration pins to adjust the voltage value provided by the boost unit or the buck unit to the corresponding power supply region, that is, when the boost unit in the voltage regulation circuit boosts the input basic voltage value Vcc, it can be configured to what voltage value it needs to be boosted. Similarly, when the buck unit in the voltage regulation circuit steps down the input basic voltage value Vcc, it can be configured to what voltage value it needs to be stepped down.

[0074] The embodiment not only reduces the occupation of the power supply pins of the FPGA chip, but also has the beneficial effect of realizing on-chip correction. By configuring the voltage regulation circuit, the internal structure problem of the chip can be corrected and solved in the FPGA chip, without the need for reflow.

[0075] The FPGA design method provided in the application can be used to design a single-die FPGA and can also be used to design a multi-die FPGA. The single-die structure FPGA chip includes one die, and the multi-die structure FPGA chip includes a silicon connection layer and a plurality of dies stacked on the silicon connection layer. Whether it is a single-die structure or a multi-die structure, the internal circuit of the chip can be divided into a plurality of local power consumption regions, and the global power supply network can be divided into a plurality of power supply regions accordingly. In an embodiment, for a multi-die structure FPGA chip, the division can be performed as follows: division is performed in units of dies, and each power supply region corresponds to a local power consumption region in which the internal circuit of the chip is located in a die. In the scenario of a multi-die structure FPGA chip, if the power supply input ends of all power supply regions are respectively connected to the power supply pins of the FPGA chip through voltage regulation circuits, the voltage regulation circuits can be arranged in the silicon connection layer.

Claims

1. An FPGA design method for debugging core voltage based on partitioning, characterized in that, The design method comprises: obtaining a chip hardware design, the chip hardware design comprising a chip internal circuit and a plurality of power supply regions, each power supply region corresponding to a local power consumption region of the chip internal circuit, and each power supply region being configured to provide a core voltage obtained by a power supply input end to a corresponding local power consumption region; generating a code stream corresponding to the chip hardware design and downloading the code stream to an FPGA chip, a power supply input end of each power supply region being connected to a power supply pin of the FPGA chip; when the FPGA chip cannot work normally in a state where the FPGA chip obtains the core voltage of the basic voltage value in all power supply regions, adjusting the core voltage obtained by at least one power supply region through the power supply pin of the FPGA chip until the FPGA chip works normally, or until it is determined that there is a faulty local power consumption region in the FPGA chip; wherein the method of adjusting the core voltage obtained by at least one power supply region comprises: controlling the core voltage of all power supply regions to be boosted or reduced according to a predetermined voltage variation mode until the FPGA chip works normally, or until the core voltage reaches a threshold voltage corresponding to the predetermined voltage variation mode and the FPGA chip still cannot work normally, determining that there is a fault in the chip internal circuit of the FPGA chip corresponding to the predetermined voltage variation mode; and controlling the core voltage of part of the power supply regions to remain at the basic voltage value and the core voltage of the remaining power supply regions to vary according to the predetermined voltage variation mode according to a predetermined strategy until the FPGA chip works normally, or until it is determined that there is a local power consumption region corresponding to the fault of the predetermined voltage variation mode; wherein the method of controlling the core voltage of the power supply region to be boosted or reduced according to the predetermined voltage variation mode comprises: controlling the core voltage of the power supply region to be gradually boosted from the basic voltage value until the FPGA chip works normally, or until the core voltage reaches an upper threshold voltage and the FPGA chip still cannot work normally, determining that there is a fault in the chip internal circuit of the FPGA chip that does not meet the setup time constraint; and controlling the core voltage of the power supply region to be gradually reduced from the basic voltage value until the FPGA chip works normally, or until the core voltage reaches a lower threshold voltage and the FPGA chip still cannot work normally, determining that there is a fault in the chip internal circuit of the FPGA chip that does not meet the hold time constraint.

2. The method of claim 1, wherein, When the core voltage of each power supply region is adjusted until the FPGA chip works normally, the core voltages determined by at least two power supply regions are not equal.

3. The method of claim 1, wherein, The method of controlling the core voltage of each power supply region according to the predetermined strategy comprises: The method comprises the following steps:

4. The method of claim 1, wherein, The method for controlling the core voltage of each power supply region according to a predetermined strategy comprises: The method comprises the following steps:

5. The method of claim 1, wherein, The method for controlling the core voltage of each power supply region according to a predetermined strategy comprises: The method comprises the following steps: All power supply regions are taken as initial fault candidate regions; The fault candidate regions are divided into two sub candidate regions, and each sub candidate region contains a plurality of power supply regions; The core voltages of all power supply regions in one of the sub candidate regions are kept as the basic voltage value, and the core voltages of all power supply regions in the other sub candidate region are controlled to change according to the predetermined voltage change mode until the FPGA chip works normally.

6. The method of claim 1, wherein, When the core voltages of all power supply regions in the sub candidate region reach the threshold voltage corresponding to the predetermined voltage change mode and the FPGA chip still cannot work normally, the sub candidate region is taken as an updated fault candidate region, and the step of dividing the fault candidate region into two sub candidate regions is re-executed until an iteration condition is reached, and it is determined that the local power consumption region corresponding to the power supply region in the fault candidate region has the fault corresponding to the predetermined voltage change mode. The power supply input terminals of two adjacent power supply regions are connected through a separation switch tube, and the method further comprises the following steps:

7. The method of claim 1, wherein, After the core voltages of each power supply region are adjusted to make the FPGA chip work normally, the separation switch tubes between the power supply input terminals of a plurality of power supply regions with equal core voltages are turned on, and the separation switch tubes between the power supply input terminals of a plurality of power supply regions with unequal core voltages are turned off. The power supply input terminals of all power supply regions are respectively connected to the power supply pins of the FPGA chip through voltage adjustment circuits, and the method for providing the core voltages of each power supply region comprises the following steps:

8. The method of claim 7, wherein, The basic voltage value is provided to the power supply pins of the FPGA chip, and the voltage adjustment circuit connected to the power supply input terminal of each power supply region is used to adjust the basic voltage value to a corresponding size of core voltage and input the core voltage into the corresponding power supply region. The voltage adjustment circuit comprises a boost unit, a buck unit and a direct connection unit, and the method further comprises the following steps: The voltage regulating circuit connected to the power supply input of each power supply area is configured by a configuration bit or by a metal option of a re-wiring layer at the time of packaging, a boost unit in the voltage regulating circuit boosts an input basic voltage value and provides the corresponding power supply area, or a buck unit in the voltage regulating circuit buck the input basic voltage value and provides the corresponding power supply area, or a direct connection unit in the voltage regulating circuit directly provides the input basic voltage value to the corresponding power supply area.

9. The method of claim 8, wherein, The method further comprises: The boost unit or the buck unit is configured by a metal option of a re-wiring layer or a configuration pin to adjust the voltage value provided by the boost unit or the buck unit to the corresponding power supply area.

10. The method of claim 7, wherein, The FPGA chip is a multi-die structure, and the FPGA chip comprises a silicon connection layer and a plurality of dies stacked on the silicon connection layer; each power supply area corresponds to a local power consumption area of the internal circuit of the chip located in one die; and the voltage regulating circuit is arranged in the silicon connection layer.

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