A slave device using dual serial peripheral interfaces to implement synchronous serial interfaces

Abstract

The present invention relates to a slave device that implements a synchronous serial interface using a dual serial peripheral interface. The slave device includes an MCU and an external interface provided on the MCU. The external interface includes two serial peripheral interfaces SPI, namely a first serial peripheral interface SPI1 and a second serial peripheral interface SPI2. The first serial peripheral interface SPI1 includes a first data output interface SPI1MISO, a first data input interface SPI1MOSI, and a first clock input interface SPI1Clock. The second serial peripheral interface SPI2 includes a frame synchronization signal input interface SPI2CS and a second clock input interface SPI2Clock. The first clock input interface SPI1Clock and the second clock input interface SPI2Clock are connected. Compared with the prior art, the present invention has the advantages of greatly reducing development costs and transplantation costs.

Description

Technical Field

[0001] The present invention relates to a slave device, in particular to a slave device which adopts a dual serial peripheral interface to realize a synchronous serial interface. Background Art

[0002] SSI (Synchronous Serial Interface) is a full-duplex serial interface characterized by a fast communication rate, usually up to 2Mbps and above. The schematic diagram of the slave device using SSI is as follows: Figure 1 As shown, the SSI protocol timing diagram is as follows Figure 2 shown.

[0003] SPI (Serial Peripheral Interface) is also a full-duplex synchronous communication bus interface. The schematic diagram of the slave device using SPI is as follows: Figure 3 As shown, the SPI protocol timing diagram is as follows Figure 4 shown.

[0004] Current mainstream chips, such as the 51 series, STM32 series, and their domestic counterparts, do not support the SSI protocol. Due to their high communication speeds, IO port simulation is often not feasible. SSI-capable chips, such as Atmel's SAM4S series, are relatively rare and expensive. This limited chip selection limits availability and makes porting and switching platforms difficult.

[0005] Therefore, how to realize a slave device that replaces the SSI protocol at a lower cost becomes a technical problem that needs to be solved. Summary of the Invention

[0006] The purpose of the present invention is to overcome the defects of the above-mentioned prior art and provide a slave device that adopts a dual serial peripheral interface to realize a synchronous serial interface.

[0007] The purpose of the present invention can be achieved by the following technical solutions:

[0008] According to one aspect of the present invention, a slave device that implements a synchronous serial interface using a dual serial peripheral interface is provided. The slave device includes an MCU and an external interface provided on the MCU. The external interface includes two serial peripheral interfaces SPI, namely a first serial peripheral interface SPI1 and a second serial peripheral interface SPI2. The first serial peripheral interface SPI1 includes a first data output interface SPI1 MISO, a first data input interface SPI1 MOSI and a first clock input interface SPI1 Clock. The second serial peripheral interface SPI2 includes a frame synchronization signal input interface SPI2 CS and a second clock input interface SPI2 Clock. The first clock input interface SPI1 Clock and the second clock input interface SPI2 Clock are connected.

[0009] As a preferred technical solution, the first clock input interface SPI1 Clock and the second clock input interface SPI2 Clock are respectively connected to the external SSI protocol clock signal output end, and are used to receive the SSI protocol clock signal sent externally.

[0010] As a preferred technical solution, the first data output interface SPI1 MISO is connected to an external SSI protocol data output terminal for receiving SSI protocol data sent externally.

[0011] As a preferred technical solution, the first data input interface SPI1 MOSI is connected to an external SSI protocol data input terminal and is used to send SSI protocol data to the outside.

[0012] As a preferred technical solution, the frame synchronization signal input interface SPI2 CS is connected to the external SSI protocol frame synchronization signal output, and is used to receive the SSI protocol frame synchronization signal sent externally.

[0013] As a preferred technical solution, the frame synchronization signal input interface SPI2 CS is an interface that can capture the pulse signal in the frame synchronization signal;

[0014] The frame synchronization signal input interface SPI2 CS captures the pulse signal in the frame synchronization signal so that the second serial peripheral interface SPI2 can track the frame synchronization signal, and then controls the transmission and stop of the first serial peripheral interface SPI1 through the second serial peripheral interface SPI2.

[0015] As a preferred technical solution, the first serial peripheral interface SPI1 is a serial peripheral interface using a DMA transfer mode.

[0016] As a preferred technical solution, the first serial peripheral interface SPI1 is a serial peripheral interface that adopts an interrupt or blocking transmission mode.

[0017] As a preferred technical solution, the two serial peripheral interfaces SPI are a SPI supporting TI mode and a general SPI.

[0018] As a preferred technical solution, the second serial peripheral interface SPI2 is an SPI that supports TI mode, and the first serial peripheral interface SPI1 is a general SPI that can customize the data receiving length.

[0019] Compared with the prior art, the present invention has the following advantages:

[0020] 1) Compared with using a dedicated SSI chip, the present invention can achieve the same effect as SSI communication through two SPI interfaces. For most chips, adding an interface is much more convenient than replacing the chip;

[0021] 2) The SPI supporting TI mode usually transmits data with a length not exceeding 32 bits BITS and cannot support SSI protocol data with a longer data length. The present invention combines an SPI supporting TI mode with a general SPI to customize the data reception length and is compatible with various situations in the SSI protocol.

[0022] 3) The SPI protocol is similar to the SSI protocol in part, but cannot directly replace it. However, after the improvement of the present invention, communication can be carried out by replacing the SSI protocol with the SPI. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 This is a schematic diagram of an existing SSI slave;

[0024] Figure 2 This is the SSI protocol signal timing diagram;

[0025] Figure 3 This is a schematic diagram of an existing SPI slave;

[0026] Figure 4 This is the SPI protocol signal timing diagram;

[0027] Figure 5 is a schematic diagram of a slave device of the present invention;

[0028] Figure 6 This is a specific circuit diagram of the slave device of the present invention. DETAILED DESCRIPTION

[0029] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0030] like Figure 5 and Figure 6 As shown, a slave device that uses a dual serial peripheral interface to implement a synchronous serial interface, the slave device includes an MCU and an external interface provided on the MCU, the external interface including two serial peripheral interfaces SPI, namely a first serial peripheral interface SPI1 and a second serial peripheral interface SPI2, the first serial peripheral interface SPI1 including a first data output interface SPI1 MISO, a first data input interface SPI1MOSI and a first clock input interface SPI1 Clock, the second serial peripheral interface SPI2 including a frame synchronization signal input interface SPI2 CS and a second clock input interface SPI2Clock, the first clock input interface SPI1Clock and the second clock input interface SPI2Clock are connected. The present invention combines two SPIs, provides a frame synchronization function through one SPI supporting TI (Texas Instruments) mode, and transmits data through the other SPI, thereby realizing the communication mode of replacing the SSI slave with the SPI.

[0031] The first clock input interface SPI1 Clock and the second clock input interface SPI2 Clock are respectively connected to the external SSI protocol clock signal output end, and are used to receive the SSI protocol clock signal sent from the outside.

[0032] The first data output interface SPI1 MISO is connected to an external SSI protocol data output terminal for receiving SSI protocol data transmitted externally. The first data input interface SPI1 MOSI is connected to an external SSI protocol data input terminal for transmitting SSI protocol data externally. Specifically, the SSI protocol data input and output signals are connected to SPI1 MOSI and SPI1 MISO. Data communication is performed via SPI1.

[0033] The frame synchronization signal input interface SPI2CS is connected to the external SSI protocol frame synchronization signal output and is used to receive the externally transmitted SSI protocol frame synchronization signal. The frame synchronization signal input interface SPI2CS is an interface that can capture the pulse signal in the frame synchronization signal. By capturing the pulse signal in the frame synchronization signal, the frame synchronization signal input interface SPI2CS enables the second serial peripheral interface SPI2 to track the frame synchronization signal. The second serial peripheral interface SPI2 then controls the transmission and stopping of the first serial peripheral interface SPI1, ensuring the synchronization of the slave device.

[0034] The first serial peripheral interface SPI1 is a serial peripheral interface that uses DMA transfer mode, which not only reduces chip CPU resource overhead but also enables continuous clock output. DMA can also use single (Normal) or circular (Circular) modes. In single mode, it is re-enabled after each interrupt, while in circular mode, it does not need to be re-enabled. The SPI in the present invention is not limited to DMA transfer mode and can also use interrupt or blocking transfer modes.

[0035] The two serial peripheral interfaces (SPIs) are one supporting TI mode and one universal SPI. The second serial peripheral interface (SPI2) is a SPI supporting TI mode, while the first serial peripheral interface (SPI1) is a universal SPI, allowing for customizable data reception lengths. SPIs supporting TI mode typically transmit data lengths no longer than 32 bits and cannot support SSI protocol data with longer data lengths. By combining a SPI supporting TI mode and a universal SPI, the present invention allows for customizable data reception lengths, compatibility with various SSI protocol scenarios.

[0036] Explanation of special terms

[0037] SSI (Synchronous Serial Interface);

[0038] SPI (Serial Peripheral Interface);

[0039] DMA (Direct Memory Access);

[0040] CS (Chip Select from device);

[0041] MISO (slave device data output);

[0042] MOSI (slave data input);

[0043] NSS (Negative Slave Select);

[0044] Frame Sync (frame synchronization signal);

[0045] TI (Texas Instruments).

[0046] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and such modifications or substitutions are intended to be within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of protection of the claims.

Claims

1. A slave device that implements a synchronous serial interface using a dual serial peripheral interface, characterized in that: The slave device includes an MCU and an external interface provided on the MCU, the external interface including two serial peripheral interfaces SPI, namely a first serial peripheral interface SPI1 and a second serial peripheral interface SPI2, the first serial peripheral interface SPI1 includes a first data output interface SPI1 MISO, a first data input interface SPI1MOSI and a first clock input interface SPI1 Clock, the second serial peripheral interface SPI2 includes a frame synchronization signal input interface SPI2 CS and a second clock input interface SPI2 Clock, the first clock input interface SPI1 Clock and the second clock input interface SPI2 Clock are connected.

2. A slave device that uses a dual serial peripheral interface to implement a synchronous serial interface according to claim 1, characterized in that: The first clock input interface SPI1 Clock and the second clock input interface SPI2Clock are respectively connected to the external SSI protocol clock signal output end, and are used to receive the SSI protocol clock signal sent from the outside.

3. The slave device for implementing a synchronous serial interface using a dual serial peripheral interface according to claim 1, wherein: The first data output interface SPI1 MISO is connected to an external SSI protocol data output terminal and is used to send SSI protocol data to the outside.

4. The slave device for implementing a synchronous serial interface using a dual serial peripheral interface according to claim 1, wherein: The first data input interface SPI1 MOSI is connected to an external SSI protocol data input terminal and is used to receive SSI protocol data sent externally.

5. The slave device for implementing a synchronous serial interface using a dual serial peripheral interface according to claim 1, wherein: The frame synchronization signal input interface SPI2 CS is connected to the external SSI protocol frame synchronization signal output and is used to receive the SSI protocol frame synchronization signal sent externally.

6. The slave device for implementing a synchronous serial interface using a dual serial peripheral interface according to claim 1, wherein: The frame synchronization signal input interface SPI2 CS is an interface that can capture the pulse signal in the frame synchronization signal; The frame synchronization signal input interface SPI2 CS captures the pulse signal in the frame synchronization signal so that the second serial peripheral interface SPI2 can track the frame synchronization signal, and then controls the transmission and stop of the first serial peripheral interface SPI1 through the second serial peripheral interface SPI2.

7. The slave device for implementing a synchronous serial interface using a dual serial peripheral interface according to claim 1, wherein: The first serial peripheral interface SPI1 is a serial peripheral interface that adopts a DMA transmission mode.

8. The slave device for implementing a synchronous serial interface using a dual serial peripheral interface according to claim 1, wherein: The first serial peripheral interface SPI1 is a serial peripheral interface that adopts an interrupt or blocking transmission mode.

9. The slave device for implementing a synchronous serial interface using a dual serial peripheral interface according to claim 1, wherein: The two serial peripheral interfaces SPI are a SPI supporting TI mode and a general SPI.

10. The slave device for implementing a synchronous serial interface using a dual serial peripheral interface according to claim 9, characterized in that: The second serial peripheral interface SPI2 is an SPI supporting TI mode, and the first serial peripheral interface SPI1 is a general SPI, which can customize the data receiving length.

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