A method and system for receiving SSI protocol data based on SPI

Abstract

This invention provides a method and system for receiving SSI protocol data based on SPI, belonging to the field of data transmission. The method includes: configuring a microcontroller to enable its serial peripheral interface to perform data transmission using direct memory access; determining the target number of bytes based on the data acknowledgment response time length of the synchronous serial interface, the total number of effective bytes, and the baud rate of the serial peripheral interface, and determining a synchronization clock signal and data to be transmitted based on the target number of bytes; sending the synchronization clock signal and data to be transmitted to the synchronous serial interface through the serial peripheral interface, while simultaneously receiving data to be decoded sent by the synchronous serial interface, and storing the data to be decoded in a receive buffer; decoding the data to be decoded in the receive buffer when the number of bytes of data to be decoded in the receive buffer equals the target number of bytes. This invention allows the microcontroller to directly receive SSI protocol data, reducing hardware complexity and cost.

Description

Technical Field

[0001] This invention relates to the field of data transmission, and in particular to a data receiving method and system based on the SPI SSI protocol. Background Technology

[0002] SSI (Synchronous Serial Interface) is a synchronous serial interface for point-to-point communication between a master and slave device. The signal connection between the master and slave device only includes two signals: a synchronous clock signal and a data signal. In the field of motor control, high-precision absolute encoders use differential signals for digital serial data transmission. The motor controller receives the protocol data and decodes it to obtain the digital value transmitted by the encoder. Motor controllers typically use commercially available microcontroller chips: DSP (Digital Signal Processing) chips, ARM (Advanced RISC Machine) core-based microcontroller chips (such as Samsung, Freescale, NXP, MICROCHIP, etc.), and FPGA (Field Programmable Gate Array) chips. However, none of these chip designs integrate a directly usable SSI protocol data interface.

[0003] In the field of motor control, the existing solutions for SSI protocol data interface decoding, along with their advantages and disadvantages, are as follows:

[0004] (1) Implementing SSI protocol data decoding and other control functions with a single FPGA chip. FPGA has extremely high design flexibility and can receive and decode protocol data according to the timing of the SSI protocol data interface. However, in the field of motor control, FPGA is programmed using hardware description languages ​​(VHDL or Verilog HDL), making it difficult to implement complex control algorithms and hindering rapid design and debugging. This solution can also use mid-to-high-end FPGA chips with integrated ARM or DSP cores to run complex control algorithms in the ARM or DSP core, solving the problem of the difficulty in implementing complex control algorithms. However, using mid-to-high-end FPGA chips results in higher hardware circuit costs.

[0005] (2) FPGA chip assists microcontroller chip in SSI protocol data decoding. The hardware circuit adopts a design of microcontroller chip plus FPGA chip, in which the microcontroller chip executes motor control algorithm, and the FPGA chip acts as an auxiliary controller to realize SSI protocol data interface decoding. The data is transmitted to the microcontroller chip through a parallel data bus. The advantage is that the decoding logic design is simple and can realize efficient data reading and parsing. However, adding FPGA chip makes the hardware circuit design complex and the cost higher.

[0006] (3) Use a dedicated SSI protocol data interface parsing chip to transmit data to the microcontroller chip via a parallel data bus. The advantage is that the data inside the decoding chip can be read directly through the parallel interface. However, using a dedicated SSI protocol data interface chip increases the complexity and cost of hardware circuit design.

[0007] (4) The microcontroller chip is designed to send, receive and decode programs, control the level state of IO (Input Output) ports, and realize the sending, receiving and decoding of SSI protocol data interface signals. The advantage is that no auxiliary devices or dedicated chips are required and the hardware circuit design is simple. However, the synchronous clock sending and data receiving programs of SSI protocol data frequently operate the IO port state, occupy a lot of microcontroller chip computing resources, cannot achieve efficient data decoding, and reduce the performance of other control programs running on the microcontroller chip.

[0008] Based on the above problems, there is an urgent need for a method that has a simple hardware design, low cost, and enables microcontroller chips to efficiently execute complex control algorithms while efficiently decoding SSI protocol data. Summary of the Invention

[0009] The purpose of this invention is to provide an SPI-based SSI protocol data receiving method and system, which can directly receive SSI protocol data through a microcontroller and efficiently decode the SSI protocol data, while reducing hardware complexity and cost.

[0010] To achieve the above objectives, the present invention provides the following solution:

[0011] A method for receiving SSI protocol data based on SPI, wherein SPI is an interface on a microcontroller, and the method includes:

[0012] Configure the microcontroller's serial peripheral interface and direct memory access peripherals so that the microcontroller's serial peripheral interface uses direct memory access for data reception and transmission.

[0013] The target number of bytes is determined based on the data response time length of the synchronous serial interface, the total number of valid bytes in the response data frame, and the baud rate of the serial peripheral interface. A synchronization clock signal and the data to be transmitted are then determined based on the target number of bytes. The target number of bytes is the number of bytes in one frame of data transmitted by the serial peripheral interface. The number of bytes in the data to be transmitted is the target number of bytes, and the number of synchronization clock signals is the target number of bytes * 8.

[0014] The serial peripheral interface sends the synchronization clock signal and the data to be sent to the synchronous serial interface, and simultaneously receives the data to be decoded sent by the synchronous serial interface through the serial peripheral interface, and stores the data to be decoded in the receive buffer; the receive buffer is a continuous storage address in the memory of the microcontroller.

[0015] When the number of bytes of data to be decoded in the receiving buffer is equal to the target number of bytes, the data to be decoded in the receiving buffer is decoded to obtain synchronous serial interface protocol data.

[0016] Optionally, determining the target number of bytes based on the data acknowledgment response time length of the synchronous serial interface, the total number of valid bytes in the acknowledgment data frame, and the baud rate of the serial peripheral interface specifically includes:

[0017] Based on the data response time length of the synchronous serial interface, the total number of effective bytes of the synchronous serial interface, and the baud rate of the serial peripheral interface, the formula T = t1 + N1 * f is used. z Calculate the duration from the start bit to the stop bit of the acknowledgment data frame; where T is the duration from the start bit to the stop bit of the acknowledgment data frame, t1 is the data acknowledgment response time length of the synchronous serial interface, N1 is the total number of valid bytes in the acknowledgment data frame, and f z The baud rate for the serial peripheral interface;

[0018] Based on the duration and the baud rate of the serial peripheral interface, the formula T / f is used. z ≤send_byte_num*8 determines the target number of bytes; where send_byte_num is the target number of bytes.

[0019] Optionally, sending the synchronization clock signal and the data to be sent to the synchronization serial interface through the serial peripheral interface specifically includes:

[0020] The data to be sent is written into the sending buffer; the sending buffer is a contiguous storage address in the memory of the microcontroller.

[0021] The data to be transmitted in the transmit buffer is output to the shift register of the serial peripheral interface device in sequence through direct storage access peripheral;

[0022] When the shift register is not empty, a synchronization clock signal is sent to the synchronous serial interface through the serial peripheral interface. At the same time, the shift register sends the bytes in the shift register bit by bit to the synchronous serial interface in the order of high bit first and low bit last, on the rising edge of each synchronization clock signal.

[0023] Optionally, receiving the data to be decoded transmitted by the synchronous serial interface through the serial peripheral interface and storing the data to be decoded in the receive buffer specifically includes:

[0024] The serial peripheral interface receives the data to be decoded sent by the synchronous serial interface on the falling edge of each synchronous clock signal;

[0025] The data to be decoded is input bit by bit into the shift register of the serial peripheral interface device through the serial peripheral interface in the order of high bit first and low bit last.

[0026] When the data in the shift register is one byte, the data in the shift register is output to the receive buffer.

[0027] Optionally, the data to be decoded in the receive buffer is decoded to obtain synchronous serial interface protocol data, specifically including:

[0028] The data to be decoded in the receive buffer is stored in a temporary array, and the number of bytes in the receive buffer is cleared to zero;

[0029] The bits of the data to be decoded in the temporary array are concatenated together sequentially to obtain long byte data;

[0030] The long byte data is searched bit by bit from the most significant bit to the least significant bit to determine the starting bit in the long byte data; the starting bit is the position of the bit that is "0" when two adjacent bits of data are "01" for the first time in the long byte data;

[0031] Based on the start bit, the valid data in the long byte data is determined; the valid data is synchronous serial interface protocol data.

[0032] Optionally, the highest bit of the long byte data is the highest bit of the first byte in the temporary array, and the lowest bit of the long byte data is the lowest bit of the last byte in the temporary array.

[0033] Optionally, determining the valid data in the long byte data based on the start bit specifically includes:

[0034] Starting from the start bit, N+2 bits are truncated from the low bits of the long byte data; where the lower N bits of the N+2 bits are valid data, and N is the number of valid data bits of the encoder.

[0035] Optionally, the SPI-based SSI protocol data receiving method further includes:

[0036] Starting from the error flag start bit of the long byte data, two bits are truncated from the least significant bit of the long byte data to obtain the encoder error flag data; the error flag start bit is the bit after the least significant bit of the valid data in the long byte data;

[0037] Starting from the check start bit of the long byte data, 6 bits are truncated from the least significant bit of the long byte data to obtain cyclic redundancy check data; the check start bit is the bit after the least significant bit of the encoder error flag data in the long byte data;

[0038] The valid data is verified based on the encoder error flag data and the cyclic redundancy check data.

[0039] To achieve the above objectives, the present invention also provides the following solution:

[0040] An SPI-based SSI protocol data receiving system is used to receive SSI protocol data via a microcontroller. The SPI-based SSI protocol data receiving system includes:

[0041] The configuration unit is used to configure the serial peripheral interface and direct memory access peripherals of the microcontroller so that the serial peripheral interface of the microcontroller can use direct memory access to receive and send data.

[0042] A clock determination unit, connected to the configuration unit, is used to determine the target number of bytes based on the data response time length of the synchronous serial interface, the total number of valid bytes in the response data frame, and the baud rate of the serial peripheral interface, and to determine the synchronous clock signal and the data to be transmitted based on the target number of bytes; the target number of bytes is the number of bytes sent by the serial peripheral interface in one frame; the number of bytes of the data to be transmitted is the target number of bytes, and the number of synchronous clock signals is the target number of bytes * 8;

[0043] The data transmission unit, connected to the clock determination unit, is used to send the synchronous clock signal and the data to be transmitted to the synchronous serial interface, and simultaneously receive the data to be decoded sent by the synchronous serial interface, and store the data to be decoded in the receive buffer; the receive buffer is a continuous storage address in the memory of the microcontroller;

[0044] The decoding unit, connected to the data transmission unit, is used to decode the data to be decoded in the receiving buffer when the number of bytes of data to be decoded in the receiving buffer is equal to the target number of bytes, so as to obtain synchronous serial interface protocol data.

[0045] Optionally, the data transmission unit is a serial peripheral interface of a microcontroller.

[0046] According to specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0047] This invention takes into account the similarity between the timing of the serial peripheral interface and the synchronous serial interface. It uses the serial peripheral interface of the microcontroller instead of the synchronous serial interface, outputting a synchronous clock signal and receiving protocol data from the synchronous serial interface. The microcontroller can directly receive SSI protocol data, and through direct storage access, the underlying hardware of the microcontroller automatically implements the transmission of the synchronous clock signal and the reception of the serial response data of the synchronous serial interface. The received data is stored in the receive buffer. The transmission and reception process does not require software intervention, reducing the consumption of computing resources. This allows the microcontroller chip to efficiently execute complex control algorithms while efficiently decoding synchronous serial interface data. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 This is a flowchart of the SSI protocol data receiving method based on SPI according to the present invention;

[0050] Figure 2 This is a timing diagram for the SSI protocol data interface;

[0051] Figure 3 This is the SPI timing diagram;

[0052] Figure 4 This is a schematic diagram of the SSI protocol data flow.

[0053] Figure 5 This is a schematic diagram of the module of the SPI-based SSI protocol data receiving system of the present invention.

[0054] Symbol explanation:

[0055] Configuration unit-1, clock determination unit-2, data transmission unit-3, decoding unit-4. Detailed Implementation

[0056] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0057] The purpose of this invention is to provide a method and system for receiving SSI protocol data based on SPI (Serial Peripheral Interface). It uses only a microcontroller chip and controls the SPI to output a synchronous clock signal, receive SSI protocol data and decode it through DMA (Direct Memory Access). No additional auxiliary controller chip or dedicated decoding chip is required. It only uses a single conventional low-end microcontroller chip, which reduces the complexity and cost of hardware design. It enables the microcontroller chip to efficiently execute complex control algorithms while realizing efficient SSI protocol data interface decoding function.

[0058] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0059] Example 1

[0060] like Figure 1 As shown, this embodiment provides a method for receiving SSI protocol data based on SPI. The execution subject of this method is a microcontroller chip, and the SPI-based SSI protocol data reception includes:

[0061] S1: Configure the microcontroller's serial peripheral interface and direct memory access peripherals so that the microcontroller's serial peripheral interface uses direct memory access for data reception and transmission.

[0062] Specifically, configure the microcontroller's DMA peripherals, SPI peripherals (including the SPI baud rate) and I / O ports, and configure the size and address of the DMA send buffer and the size and address of the receive buffer.

[0063] The DMA transmit buffer is a contiguous block of memory in the microcontroller chip, used to temporarily store software-generated data awaiting transmission from the peripheral interface. Similarly, the DMA receive buffer is also a contiguous block of memory in the microcontroller chip, used to temporarily store external serial data received by the SPI peripheral, awaiting further processing by the software.

[0064] Step S1 sets the microcontroller's SPI data receiving and sending mode to DMA mode. This mode enables the microcontroller hardware to automatically exchange data between the chip's peripheral interface and the chip's memory. The data exchange process does not require software operation and does not occupy computing resources.

[0065] S2: Determine the target number of bytes based on the data response time length of the synchronous serial interface, the total number of valid bytes in the response data frame, and the baud rate of the serial peripheral interface. Then, determine the synchronization clock signal and the data to be transmitted based on the target number of bytes. The data response time length of the SSI protocol data interface timing can be found in the device manual.

[0066] Specifically, the formula T = t1 + N1 * f is first used. z Calculate the duration from the start bit to the stop bit of the acknowledgment data frame. Where T is the duration from the start bit to the stop bit of the acknowledgment data frame, t1 is the data acknowledgment response time length of the synchronous serial interface, N1 is the total number of valid bytes in the acknowledgment data frame, and f... z This is the baud rate of the serial peripheral interface. Then, based on the baud rate of the serial peripheral interface, calculate the number of bytes (target bytes) to be sent in one frame (send_byte_num). The target bytes (send_byte_num) are the smallest integers that satisfy the following relationship: T / f z ≤send_byte_num*8. The number of bytes of data to be sent is the target number of bytes, and the number of synchronization clock signals is the target number of bytes * 8.

[0067] The number of SPI synchronization clocks corresponding to the `send_byte_num` bytes must be `send_byte_num * 8` to ensure that the SPI can output enough synchronization clocks to receive a complete frame of SSI protocol data. In the following steps, `send_byte_num` bytes are stored in the DMA transmit buffer.

[0068] like Figure 2 and Figure 3 As shown, the timing of the SSI protocol data interface is similar to that of the SPI. Figure 3 In the SPI interface, MISO is the SPI data input signal, and MOSI is the SPI data output signal. Figure 3 As can be seen from the interface timing, when the SPI completes the data transmission on the rising edge of the synchronous clock corresponding to the last data bit, it will also complete the reception of the last data bit on the falling edge of the synchronous clock. At this time, the number of received data bytes is send_byte_num.

[0069] S3: The synchronous clock signal and the data to be transmitted are sent to the synchronous serial interface through the serial peripheral interface. Simultaneously, the data to be decoded sent by the synchronous serial interface is received through the serial peripheral interface, and the data to be decoded is stored in the receive buffer. The receive buffer is a contiguous memory address in the microcontroller's memory.

[0070] Further, step S3, which involves sending the synchronization clock signal and the data to be sent to the synchronization serial interface via the serial peripheral interface, specifically includes:

[0071] S311: Write the data to be sent into the transmit buffer. The transmit buffer is a contiguous block of memory in the microcontroller's memory. Specifically, write `send_byte_num` bytes of data to be sent into the DMA peripheral transmit buffer. Set the number of bytes in the transmit buffer to `send_byte_num`.

[0072] S312: The data to be transmitted in the transmit buffer is sequentially output to the shift register of the serial peripheral interface device via the direct memory access peripheral. Specifically, the transmit flag of the DMA peripheral transmit enable register is set to 1 to start transmission.

[0073] S313: When the shift register is not empty, a synchronization clock signal is sent to the synchronous serial interface through the serial peripheral interface. At the same time, the shift register sends the bytes in the shift register bit by bit to the synchronous serial interface in the order of high bit first and low bit last, on the rising edge of each synchronization clock signal.

[0074] like Figure 4 The SSI protocol data transmission process shown here, after the transmission flag is set to 1, does not require software control and does not consume computing resources.

[0075] Specifically, the DMA peripheral outputs the first byte of data to be sent from the transmit buffer to the shift register of the SPI peripheral, decrements the number of bytes in the transmit buffer by 1, and the shift register is now non-empty. While the shift register is non-empty, the SPI peripheral outputs a synchronization clock signal. The shift register outputs the data bits sequentially on each rising edge of the synchronization clock signal, from most significant bit to least significant bit. After the data in the SPI peripheral's shift register has been sent, the DMA peripheral outputs the next byte of data from the transmit buffer to the SPI peripheral's shift register, repeating this process until the number of bytes in the transmit buffer is 0. When the SPI peripheral's shift register has sent the last byte of data from the transmit buffer, the synchronization clock signal and data signal stop outputting. During the transmission of one frame of SSI protocol data, the number of synchronization clock signals is 8 * send_byte_num.

[0076] The microcontroller's SPI peripheral, while sending a synchronization clock signal, also receives SSI protocol data interface input data on each falling edge of the synchronization clock signal. Step S3, receiving the data to be decoded sent by the synchronous serial interface through the serial peripheral interface and storing the data to be decoded in the receive buffer, specifically includes:

[0077] S321: Receive the data to be decoded sent by the synchronous serial interface through the serial peripheral interface on the falling edge of each synchronous clock signal.

[0078] S322: The data to be decoded is input bit by bit into the shift register of the serial peripheral interface device through the serial peripheral interface in the order of high bit first and low bit last.

[0079] S323: When the data in the shift register is one byte, output the data in the shift register to the receive buffer.

[0080] refer to Figure 4 During the SSI protocol data interface reception process, after each byte of data is received, the shift register outputs this byte of data to the DMA peripheral receive buffer, and the number of bytes in the receive buffer is incremented by 1. When the number of bytes in the DMA peripheral receive buffer reaches the target number of bytes (send_byte_num), the SSI protocol data interface input data reception is complete, triggering an interrupt, and waiting for software to process the data in the DMA peripheral receive buffer.

[0081] Before step S4, the microcontroller's DMA peripheral interrupt trigger condition is first configured so that the number of data bytes in the receive buffer equals the target number of bytes (send_byte_num). The SPI module receives serial data input signals while simultaneously sending a synchronization clock signal. The shift register inside the SPI module moves the received serial data bits bit by bit from high to low. Every 8 serial data bits received, an 8-bit data byte is output to the DMA receive buffer, and the number of valid data bytes in the receive buffer is incremented by 1. When the number of bytes reaches the configured trigger condition (target number of bytes), an interrupt is triggered, the interrupt service function is entered, and the data in the DMA peripheral receive buffer is retrieved.

[0082] S4: When the number of bytes of data to be decoded in the receiving buffer is equal to the target number of bytes, the data to be decoded in the receiving buffer is decoded to obtain synchronous serial interface protocol data.

[0083] After an interrupt is triggered, the interrupt service routine is executed. The software will process the data in the microcontroller's DMA peripheral receive buffer, according to... Figure 2 The SSI protocol data interface timing begins parsing the received data. After parsing is complete, the number of valid bytes in the receive buffer is cleared to zero, and the interrupt service routine is exited.

[0084] Step S4, which involves decoding the data to be decoded in the receive buffer, specifically includes:

[0085] S41: Store the data to be decoded in the receive buffer into a temporary array, and clear the number of bytes in the receive buffer to zero. Specifically, copy the data in the DMA peripheral receive buffer into a temporary array, and clear the number of bytes in the DMA peripheral receive buffer to zero.

[0086] S42: Concatenate the bits of the data to be decoded in the temporary array together to obtain long byte data.

[0087] In this embodiment, the most significant bit of the long byte data is the most significant bit of the first byte in the temporary array, and the least significant bit of the long byte data is the least significant bit of the last byte in the temporary array. The bitstream of the long byte data from most significant bit to least significant bit can represent the waveform of a frame of SSI protocol data in the time domain. Each bit represents the high or low level of the received signal at each falling edge of the synchronization clock for the SSI protocol data interface. The most significant and second most significant bits of the long byte data are 1.

[0088] S43: Perform a bit-by-bit search on the long byte data from the most significant bit to the least significant bit to determine the start bit in the long byte data. The start bit is the position of the bit that is "0" when two adjacent bits in the long byte data first appear to be "01".

[0089] S44: Based on the start bit, determine the valid data in the long byte data. The valid data is synchronous serial interface protocol data.

[0090] Specifically, starting from the start bit, N+2 bits are truncated from the lower bits of the long byte data. The lower N bits of these N+2 bits are valid data, where N is the number of valid data bits in the encoder, obtained from the encoder product manual.

[0091] Based on step S4, the SPI-based SSI protocol data reception method further includes:

[0092] Starting from the error flag start bit of the long byte data, 2 bits are truncated from the least significant bit of the long byte data to obtain the encoder error flag data. Figure 2 Error flags F1 and F0 in the data. The starting bit of the error flag is the bit after the least significant bit of the valid data in the long byte data.

[0093] Starting from the check start bit of the long byte data, 6 bits are truncated from the least significant bit of the long byte data to obtain CRC (Cyclic Redundancy Check) data. The check start bit is the bit after the least significant bit of the encoder error flag data in the long byte data.

[0094] The valid data is verified based on the encoder error flag data and the cyclic redundancy check data, thus completing the SSI protocol data decoding.

[0095] Compared with existing technical solutions, the present invention has the following advantages:

[0096] 1. This invention utilizes the similarity between the timing of the SSI protocol data interface and the SPI timing, and uses the SPI, which is available in all microcontroller chips, to replace the SSI protocol data interface to perform the transmission of synchronous clock signals and the reception of SSI protocol data. No additional dedicated SSI protocol data interface chip or FPGA chip is required. The received SSI protocol data is decoded by software parsing, which does not require additional auxiliary chips. It can be implemented using only low-end microcontroller chips (such as STM32F1 or STM32F4 series), which simplifies the circuit design and reduces hardware circuit costs.

[0097] 2. This invention utilizes a DMA peripheral to perform data exchange between the microcontroller chip's memory and SPI, requiring no software operation during the data exchange process. When initiating the transmission of the synchronization clock signal, the software only needs to set the transmission flag bit in the microcontroller chip's DMA peripheral transmit enable register to start the transmission of the synchronization clock signal and the reception of SSI protocol data. Subsequent synchronization clock signal transmission and data reception are automatically completed by the microcontroller chip hardware, without software intervention. The microcontroller chip's computing resources are only consumed when initiating the transmission of the synchronization clock signal and parsing / decoding the received SSI protocol data; no computing resources are consumed during transmission and reception, thus reducing the impact on the operation of other programs within the microcontroller chip and achieving efficient SSI protocol data interface decoding functionality.

[0098] In summary, any microcontroller chip equipped with DMA peripherals and SPI can receive SSI protocol data using the method of this invention.

[0099] Example 2

[0100] In order to implement the method corresponding to Embodiment 1 above and achieve the corresponding functions and technical effects, an SPI-based SSI protocol data receiving system is provided below.

[0101] like Figure 5 As shown, the SPI-based SSI protocol data receiving system provided in this embodiment includes: a configuration unit 1, a clock determination unit 2, a data transmission unit 3, and a decoding unit 4.

[0102] The configuration unit 1 is used to configure the serial peripheral interface and direct memory access peripheral of the microcontroller so that the serial peripheral interface of the microcontroller can use direct memory access to receive and send data.

[0103] The clock determination unit 2 is connected to the configuration unit 1. The clock determination unit 2 is used to determine the target number of bytes based on the data response time length of the synchronous serial interface, the total number of effective bytes of the synchronous serial interface, and the baud rate of the serial peripheral interface, and to determine the synchronous clock signal and the data to be sent based on the target number of bytes. The target number of bytes is the number of bytes of one frame of data sent by the serial peripheral interface. The number of bytes of the data to be sent is the target number of bytes, and the number of synchronous clock signals is the target number of bytes * 8.

[0104] The data transmission unit 3 is connected to the clock determination unit 2. The data transmission unit 3 is used to send the synchronous clock signal and the data to be transmitted to the synchronous serial interface, and simultaneously receive the data to be decoded sent by the synchronous serial interface, storing the data to be decoded in a receive buffer. The receive buffer is a contiguous memory address in the microcontroller's memory. In this embodiment, the data transmission unit is the microcontroller's serial peripheral interface.

[0105] Decoding unit 4 is connected to data transmission unit 3. Decoding unit 4 is used to decode the data to be decoded in the receiving buffer when the number of bytes of the data to be decoded in the receiving buffer is equal to the number of target bytes, so as to obtain synchronous serial interface protocol data.

[0106] Compared to existing technologies, the SPI-based SSI protocol data receiving system provided in this embodiment has the same beneficial effects as the SPI-based SSI protocol data receiving method provided in Embodiment 1, and will not be repeated here.

[0107] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0108] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A method for receiving SSI protocol data based on SPI, wherein SPI is an interface on a microcontroller, characterized in that, The SPI-based SSI protocol data reception method includes: Configure the microcontroller's serial peripheral interface and direct memory access peripherals so that the microcontroller's serial peripheral interface uses direct memory access for data reception and transmission. The target number of bytes is determined based on the data response time length of the synchronous serial interface, the total number of valid bytes in the response data frame, and the baud rate of the serial peripheral interface. A synchronization clock signal and the data to be transmitted are then determined based on the target number of bytes. The target number of bytes is the number of bytes sent by the serial peripheral interface in one frame. The number of bytes of the data to be transmitted is the target number of bytes, and the number of synchronization clock signals is the target number of bytes * 8. The serial peripheral interface sends the synchronization clock signal and the data to be sent to the synchronous serial interface, and simultaneously receives the data to be decoded sent by the synchronous serial interface through the serial peripheral interface, and stores the data to be decoded in the receive buffer; the receive buffer is a continuous storage address in the memory of the microcontroller. When the number of bytes of data to be decoded in the receiving buffer is equal to the target number of bytes, the data to be decoded in the receiving buffer is decoded to obtain synchronous serial interface protocol data.

2. The SSI protocol data receiving method based on SPI according to claim 1, characterized in that, The step of determining the target number of bytes based on the data response time length of the synchronous serial interface, the total number of valid bytes in the response data frame, and the baud rate of the serial peripheral interface specifically includes: Based on the data response time length of the synchronous serial interface, the total number of effective bytes of the synchronous serial interface, and the baud rate of the serial peripheral interface, the formula T = t1 + N1 * f is used. z Calculate the duration from the start bit to the stop bit of the acknowledgment data frame; where T is the duration from the start bit to the stop bit of the acknowledgment data frame, t1 is the data acknowledgment response time length of the synchronous serial interface, N1 is the total number of valid bytes in the acknowledgment data frame, and f z The baud rate for the serial peripheral interface; Based on the duration and the baud rate of the serial peripheral interface, the formula T / f is used. z ≤send_byte_num*8 determines the target number of bytes; where send_byte_num is the target number of bytes.

3. The SSI protocol data receiving method based on SPI according to claim 1, characterized in that, Sending the synchronization clock signal and the data to be sent to the synchronization serial interface through the serial peripheral interface specifically includes: The data to be sent is written into the sending buffer; the sending buffer is a contiguous storage address in the memory of the microcontroller. The data to be transmitted in the transmit buffer is output to the shift register of the serial peripheral interface device in sequence through direct storage access peripheral; When the shift register is not empty, a synchronization clock signal is sent to the synchronous serial interface through the serial peripheral interface. At the same time, the shift register sends the bytes in the shift register bit by bit to the synchronous serial interface in the order of high bit first and low bit last, on the rising edge of each synchronization clock signal.

4. The SPI-based SSI protocol data receiving method according to claim 1, characterized in that, Receives the data to be decoded sent by the synchronous serial interface through the serial peripheral interface, and stores the data to be decoded in the receive buffer, specifically including: The serial peripheral interface receives the data to be decoded sent by the synchronous serial interface on the falling edge of each synchronous clock signal; The data to be decoded is input bit by bit into the shift register of the serial peripheral interface device through the serial peripheral interface in the order of high bit first and low bit last. When the data in the shift register is one byte, the data in the shift register is output to the receive buffer.

5. The SPI-based SSI protocol data receiving method according to claim 1, characterized in that, Decoding the data to be decoded in the receive buffer to obtain synchronous serial interface protocol data specifically includes: The data to be decoded in the receive buffer is stored in a temporary array, and the number of bytes in the receive buffer is cleared to zero; The bits of the data to be decoded in the temporary array are concatenated together sequentially to obtain long byte data; The long byte data is searched bit by bit from the most significant bit to the least significant bit to determine the start bit in the long byte data; the start bit is the position of the bit that is "0" when two adjacent bits of data are "01" for the first time in the long byte data; Based on the start bit, the valid data in the long byte data is determined; the valid data is synchronous serial interface protocol data.

6. The SPI-based SSI protocol data receiving method according to claim 5, characterized in that, The highest bit of the long byte data is the highest bit of the first byte in the temporary array, and the lowest bit of the long byte data is the lowest bit of the last byte in the temporary array.

7. The SPI-based SSI protocol data receiving method according to claim 5, characterized in that, Based on the start bit, the valid data in the long byte data is determined, specifically including: Starting from the start bit, N+2 bits are truncated from the low bits of the long byte data; where the lower N bits of the N+2 bits are valid data, and N is the number of valid data bits of the encoder.

8. The SPI-based SSI protocol data receiving method according to claim 5, characterized in that, The SPI-based SSI protocol data reception method further includes: Starting from the error flag start bit of the long byte data, two bits are truncated from the least significant bit of the long byte data to obtain the encoder error flag data; the error flag start bit is the bit after the least significant bit of the valid data in the long byte data; Starting from the check start bit of the long byte data, 6 bits are truncated from the least significant bit of the long byte data to obtain cyclic redundancy check data; the check start bit is the bit after the least significant bit of the encoder error flag data in the long byte data; The valid data is verified based on the encoder error flag data and the cyclic redundancy check data.

9. An SPI-based SSI protocol data receiving system for receiving SSI protocol data via a microcontroller, characterized in that, The SPI-based SSI protocol data receiving system includes: The configuration unit is used to configure the serial peripheral interface and direct memory access peripherals of the microcontroller so that the serial peripheral interface of the microcontroller can use direct memory access to receive and send data. A clock determination unit, connected to the configuration unit, is used to determine the target number of bytes based on the data response time length of the synchronous serial interface, the total number of valid bytes in the response data frame, and the baud rate of the serial peripheral interface, and to determine the synchronous clock signal and the data to be transmitted based on the target number of bytes; the target number of bytes is the number of bytes sent by the serial peripheral interface in one frame; the number of bytes of the data to be transmitted is the target number of bytes, and the number of synchronous clock signals is the target number of bytes * 8; The data transmission unit, connected to the clock determination unit, is used to send the synchronous clock signal and the data to be transmitted to the synchronous serial interface, and simultaneously receive the data to be decoded sent by the synchronous serial interface, and store the data to be decoded in the receive buffer; the receive buffer is a continuous storage address in the memory of the microcontroller; The decoding unit, connected to the data transmission unit, is used to decode the data to be decoded in the receiving buffer when the number of bytes of data to be decoded in the receiving buffer is equal to the number of target bytes, so as to obtain synchronous serial interface protocol data.

10. The SPI-based SSI protocol data receiving system according to claim 9, characterized in that, The data transmission unit is a serial peripheral interface of the microcontroller.

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