Bias power supply circuit, device and liquid crystal screen

Abstract

The application discloses a bias power supply circuit, device and liquid crystal screen, and the circuit comprises a direct current boost conversion module, an output module and a voltage feedback module; the direct current boost conversion module is used for processing a power supply voltage into a first PWM signal and a second PWM signal; the output module is used for converting the first PWM signal and the second PWM signal to obtain a first negative voltage signal and a first positive voltage signal; the voltage feedback module is used for collecting the first positive voltage signal and obtaining a voltage feedback signal according to the first positive voltage signal; the direct current boost conversion module is further used for respectively adjusting the duty cycles of the first PWM signal and the second PWM signal according to the voltage feedback signal; and the output module is used for converting the adjusted first PWM signal and the adjusted second PWM signal respectively to obtain a second negative voltage signal and a second positive voltage signal; and the application can output negative voltage and positive voltage for power supply by using simple modules, and the cost is low.

Description

Technical Field

[0001] This invention relates to the field of power supply technology, and in particular to a bias power supply circuit, device, and LCD screen. Background Technology

[0002] With the development of technology, the use of operational amplifier circuits and TFT LCD screens is becoming more and more widespread. Whether now or in the future, the usage of these components in consumer electronics, industrial products, or automotive electronics is on the rise, and most of these products require the use of power amplifier circuits and TFT LCD screens.

[0003] When using power amplifier circuits and TFT LCD screens, both require simultaneous supply of negative and positive voltages. There are two existing power supply methods: one uses two independent power supply systems to provide negative and positive voltages respectively, and the other uses a capacitor pump to generate both positive and negative voltages. However, both of these methods are relatively expensive. Therefore, a low-cost bias power supply circuit is needed.

[0004] The above content is only used to help understand the technical solution of the present invention and does not represent an admission that the above content is prior art. Summary of the Invention

[0005] The main objective of this invention is to provide a bias power supply circuit, device, and liquid crystal display, which aims to solve the technical problem of high cost of power supply systems in the prior art.

[0006] To achieve the above objectives, the present invention provides a bias power supply circuit, which includes: a DC-DC boost converter module, an output module, and a voltage feedback module;

[0007] The DC boost module is connected to both the output module and the voltage feedback module, and the voltage feedback module is also connected to the output module.

[0008] The DC-DC boost converter module is used to process the power supply voltage into a first PWM signal and a second PWM signal;

[0009] The output module is used to convert the first PWM signal to obtain a first negative voltage signal, and to convert the second PWM signal to obtain a first positive voltage signal;

[0010] The voltage feedback module is used to acquire the first positive voltage signal and obtain a voltage feedback signal based on the first positive voltage signal;

[0011] The DC-DC boost converter module is also used to adjust the duty cycle of the first PWM signal and the second PWM signal respectively according to the voltage feedback signal;

[0012] The output module is used to convert the adjusted first PWM signal to obtain a second negative voltage signal, and to convert the adjusted second PWM signal to obtain a second positive voltage signal. The second negative voltage signal and the second positive voltage signal are used to power the LCD screen.

[0013] Optionally, the output module includes: a first output submodule and a second output submodule;

[0014] The first output submodule is used to convert the first PWM signal to obtain a first negative voltage signal;

[0015] The second output submodule is used to convert the second PWM signal to obtain a first positive voltage signal;

[0016] The first output submodule is also used to convert the adjusted first PWM signal to obtain a second negative voltage signal;

[0017] The second output submodule is also used to convert the adjusted second PWM signal to obtain a second positive voltage signal.

[0018] Optionally, the DC-DC boost converter module includes a chip, a first capacitor, a second capacitor, a third capacitor, and an inductor;

[0019] Specifically, the first pin of the chip is connected to one end of the first capacitor, one end of the second capacitor, and one end of the inductor; the other end of the first capacitor is connected to the first output submodule; the other end of the second capacitor is connected to the second output submodule; the other end of the inductor is connected to the third capacitor; the other end of the third capacitor is grounded; the second pin of the chip is grounded; the third pin of the chip is connected to the voltage feedback module; the fourth pin of the chip is connected to the fifth pin of the chip; and the fifth pin of the chip is connected to the end of the inductor closest to the third capacitor.

[0020] Optionally, the first output submodule includes: a first dual diode, a fourth capacitor, and a Zener diode;

[0021] In this configuration, the first pin of the first dual diode is connected to one end of the fourth capacitor, the end of the fourth capacitor near the first pin of the first dual diode is connected to the anode of the Zener diode, the second pin of the first dual diode is connected to the other end of the fourth capacitor, the end of the fourth capacitor near the second pin of the first dual diode is connected to the cathode of the Zener diode, the end of the fourth capacitor near the cathode of the Zener diode is grounded, and the third pin of the first dual diode is connected to the end of the first capacitor furthest from the chip.

[0022] Optionally, the first dual diode is a BAT54S.

[0023] Optionally, the second output submodule includes: a second dual diode and a fifth capacitor;

[0024] In this configuration, the first pin of the second dual diode is connected to one end of the fifth capacitor, the other end of the fifth capacitor is grounded, the first pin of the second dual diode is also connected to the voltage feedback module, the second pin of the second dual diode is grounded, and the third pin of the second dual diode is connected to the end of the second capacitor furthest from the chip.

[0025] Optionally, the second dual diode is a BAT54S.

[0026] Optionally, the voltage feedback module includes: a first resistor and a second resistor;

[0027] Wherein, one end of the first resistor is connected to the first pin of the second dual diode, the other end of the first resistor is connected to one end of the second resistor, the other end of the second resistor is grounded, and the end of the first resistor closest to the second resistor is connected to the third pin of the chip.

[0028] In addition, to achieve the above objectives, the present invention also proposes a bias power supply device, which includes the bias power supply circuit as described above.

[0029] In addition, to achieve the above objectives, the present invention also proposes a liquid crystal display screen, the liquid crystal display screen including the bias power supply device as described above.

[0030] This invention provides a bias power supply circuit, comprising: a DC-DC boost converter module, an output module, and a voltage feedback module; wherein the DC-DC boost converter module is connected to both the output module and the voltage feedback module, and the voltage feedback module is also connected to the output module; the DC-DC boost converter module is used to process the supply voltage into a first PWM signal and a second PWM signal; the output module is used to convert the first PWM signal to obtain a first negative voltage signal and to convert the second PWM signal to obtain a first positive voltage signal; the voltage feedback module is used to acquire the first positive voltage signal and to obtain a voltage feedback signal based on the first positive voltage signal; the DC-DC boost converter module is also used to adjust the duty cycle of the first PWM signal and the second PWM signal respectively based on the voltage feedback signal; the output module is used to convert the adjusted first PWM signal to obtain a second negative voltage signal and to convert the adjusted second PWM signal to obtain a second positive voltage signal, wherein the second negative voltage signal and the second positive voltage signal are used to power an LCD screen. Because this invention uses simple modules to output negative and positive voltages for power supply, its cost is lower compared to existing power supply systems. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the bias power supply circuit provided in an embodiment of the present invention;

[0032] Figure 2 The circuit schematic diagram of the bias power supply circuit provided in the embodiment of the present invention;

[0033] Figure 3 This is a diagram showing the measurement results of the second positive voltage signal in the bias power supply circuit provided in an embodiment of the present invention.

[0034] Figure 4 This is a diagram showing the measurement results of the second negative voltage signal in the bias power supply circuit provided in an embodiment of the present invention.

[0035] Figure 5 This is a graph showing the ripple voltage measurement results of the second positive voltage signal in the bias power supply circuit provided in an embodiment of the present invention.

[0036] Figure 6 The diagram shows the ripple voltage measurement results of the second negative voltage signal in the bias power supply circuit provided in the embodiment of the present invention.

[0037] Explanation of icon numbers:

[0038] label name label name 1 DC-DC boost converter module C1~C5 First capacitor to fifth capacitor 2 Output module D1 First dual diode 3 Voltage feedback module D2 Second dual diode 21 First output submodule ZD Zener diode 22 Second output submodule R1 First resistor U1 chip R2 Second resistor L1 inductance

[0039] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0040] It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the invention.

[0041] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0042] It should be noted that the descriptions involving "first," "second," etc., in the embodiments of the present invention are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, the user should consider that such a combination of technical solutions does not exist and is not within the scope of protection claimed by the present invention.

[0043] Reference Figure 1 , Figure 1 This is a schematic diagram of the bias power supply circuit provided in an embodiment of the present invention;

[0044] like Figure 1 As shown, the bias power supply circuit provided in this embodiment includes: a DC-DC boost converter module 1, an output module 2, and a voltage feedback module 3;

[0045] The DC boost module is connected to the output module 2 and the voltage feedback module 3 respectively, and the voltage feedback module 3 is also connected to the output module 2.

[0046] The DC-DC boost converter module 1 is used to process the power supply voltage into a first PWM signal and a second PWM signal;

[0047] It should be noted that the bias power supply circuit provided in this embodiment can be applied in any scenario where the LCD screen is powered or the power amplifier circuit is powered. The LCD screen or power amplifier circuit can operate stably and reliably under the power supply of the bias power supply circuit provided in this embodiment.

[0048] It is understood that both the first PWM signal and the second PWM signal mentioned above are pulse width modulation signals. In this embodiment, they are digital signals obtained by digitally encoding the power supply voltage.

[0049] The output module 2 is used to convert the first PWM signal to obtain a first negative voltage signal, and to convert the second PWM signal to obtain a first positive voltage signal;

[0050] It should be understood that the aforementioned first negative voltage signal and first positive voltage signal are determined based on the reference zero-point signal (zero level). For example, the most commonly used zero level is ground. In this embodiment, the reference zero-point signal can be set according to the actual situation.

[0051] It should be noted that the output module 2 includes: a first output submodule 21 and a second output submodule 22; the first output submodule 21 is used to convert the first PWM signal to obtain a first negative voltage signal; the second output submodule 22 is used to convert the second PWM signal to obtain a first positive voltage signal.

[0052] In a specific implementation, the DC-DC boost converter 1 converts the power supply voltage into a first PWM signal and a second PWM signal, and transmits the first PWM signal to the first output submodule 21 and the second PWM signal to the second output submodule 22. The first output submodule 21 converts the first PWM signal into a first negative voltage signal, and the second output submodule 22 converts the second PWM signal into a first positive voltage signal.

[0053] The voltage feedback module 3 is used to acquire the first positive voltage signal and obtain a voltage feedback signal based on the first positive voltage signal;

[0054] It should be noted that the voltage feedback module 3 divides the first positive voltage signal it has acquired to obtain the voltage division result, and transmits the voltage division result to the DC boost module in the form of a voltage feedback signal.

[0055] The DC-DC boost converter module 1 is also used to adjust the duty cycle of the first PWM signal and the second PWM signal respectively according to the voltage feedback signal;

[0056] It should be emphasized that the aforementioned DC boost module has an internal feedback reference voltage. The voltage division result is compared with the feedback reference voltage. When the voltage division result is greater than the feedback reference voltage, the duty cycle time is increased to reduce the voltage division result. When the voltage division result is less than the feedback reference voltage, the duty cycle time is decreased to increase the voltage division result.

[0057] In a specific implementation, the voltage feedback module 3 acquires the first positive voltage signal, divides the first positive voltage signal, and transmits the voltage division result to the DC boost module in the form of a voltage feedback signal. The DC boost module compares the voltage division result with the internal feedback reference voltage and adjusts the duty cycle of the first PWM signal and the second PWM signal according to the comparison result.

[0058] The output module 2 is used to convert the adjusted first PWM signal to obtain a second negative voltage signal, and to convert the adjusted second PWM signal to obtain a second positive voltage signal. The second negative voltage signal and the second positive voltage signal are used to power the LCD screen.

[0059] It should be noted that the above-mentioned conversion of the first PWM signal, the second PWM signal, the adjusted first PWM signal, and the adjusted second PWM signal may include rectification, filtering, or other conversions to obtain the first positive voltage signal and the first negative voltage signal. This embodiment does not limit this.

[0060] It is understood that the first output submodule 21 is also used to convert the adjusted first PWM signal to obtain a second negative voltage signal; the second output submodule 22 is also used to convert the adjusted second PWM signal to obtain a second positive voltage signal. At the same time, the second negative voltage signal and the second positive voltage signal can be used to power the LCD screen and other devices. For ease of understanding, this embodiment uses powering the LCD screen as an example.

[0061] In the specific implementation, the first output submodule 21 converts the adjusted first PWM signal to obtain a second negative voltage signal, and the second output submodule 22 converts the adjusted second PWM signal to obtain a second positive voltage signal. The first output submodule 21 and the second output submodule 22 respectively transmit the second negative voltage signal and the first positive voltage signal to the LCD screen to power the LCD screen.

[0062] In this embodiment, the DC-DC boost converter module 1 converts the supply voltage into a first PWM signal and a second PWM signal. The first PWM signal is transmitted to the first output submodule 21, and the second PWM signal is transmitted to the second output submodule 22. The first output submodule 21 converts the first PWM signal into a first negative voltage signal, and the second output submodule 22 converts the second PWM signal into a first positive voltage signal. The voltage feedback module 3 acquires the first positive voltage signal, divides it, and transmits the voltage division result to the DC-DC boost converter module as a voltage feedback signal. The DC-DC boost converter module 1 compares the voltage division result with the internal feedback reference voltage and adjusts the duty cycle of the first and second PWM signals according to the comparison result. The first output submodule 21 converts the adjusted first PWM signal to obtain a second negative voltage signal, and the second output submodule 22 converts the adjusted second PWM signal to obtain a second positive voltage signal. Since this embodiment uses simple modules to output negative and positive voltages for power supply, the cost of this embodiment is lower than that of existing power supply systems. At the same time, the voltage feedback module 3 forms a closed-loop control, improving the stability of the output second negative and second positive voltage signals.

[0063] To further explain the low cost of the modules used in this embodiment, refer to... Figure 2 , Figure 2 The circuit schematic diagram of the bias power supply circuit provided in the embodiment of the present invention;

[0064] like Figure 2 As shown, the DC-DC boost converter module 1 includes a chip U1, a first capacitor C1, a second capacitor C2, a third capacitor C3, and an inductor L1;

[0065] Specifically, the first pin of chip U1 is connected to one end of the first capacitor C1, one end of the second capacitor C2, and one end of the inductor L1. The other end of the first capacitor C1 is connected to the first output submodule 21. The other end of the second capacitor C2 is connected to the second output submodule 22. The other end of the inductor L1 is connected to the third capacitor C3. The other end of the third capacitor C3 is grounded. The second pin of chip U1 is grounded. The third pin of chip U1 is connected to the voltage feedback module 3. The fourth pin of chip U1 is connected to the fifth pin of chip U1. The fifth pin of chip U1 is connected to the end of the inductor L1 closest to the third capacitor C3.

[0066] It should be noted that the above-mentioned power supply voltage is input to the DC-DC boost converter module 1 through the VIN interface. The above-mentioned chip U1 converts the power supply voltage into the first PWM signal and the second PWM signal through the switching action. The third capacitor C3 is used for front-end filtering, which can reduce the voltage ripple generated by the internal switching action of chip U1 and provide a clean power supply voltage for chip U1.

[0067] Understandably, the aforementioned inductor L1 can be used to address electromagnetic radiation problems caused by excessively long parasitic inductance and capacitance resulting from excessively long wires extending outward from the component package. At the same time, the aforementioned inductor L1 can also serve as an energy storage element. When the first pin of chip U1 is turned on, inductor L1 begins to store energy, and when the first pin of chip U1 is turned off, inductor L1 begins to release energy, providing high-voltage power supply for subsequent circuits.

[0068] It should be understood that the first capacitor C1 and the second capacitor C2 mentioned above can be used to address electromagnetic radiation problems caused by excessively long parasitic inductance and capacitance resulting from excessively long wires leading out of the component package. The first capacitor C1 couples the first PWM signal to the first output submodule 21, and the second capacitor C2 couples the second PWM signal to the second output submodule 22.

[0069] Meanwhile, the chip U1 receives the first positive voltage signal collected by the voltage feedback module 3 through the third pin, adjusts the duty cycle according to the voltage feedback signal, outputs the adjusted first PWM signal to the first output submodule 21 through the first capacitor C1, and outputs the adjusted second PWM signal to the second output submodule 22 through the second capacitor C2.

[0070] Furthermore, the calculation of the duty cycle value mentioned above can be referenced by the following formula:

[0071]

[0072] In the formula, D is the duty cycle, and V0 is the output voltage formed by the first positive and negative voltage signals mentioned above, in volts (V). i The input voltage is formed by the above-mentioned supply voltage, and the unit is V. η is the conversion efficiency of chip U1.

[0073] Furthermore, the values ​​of the first capacitor C1 and the second capacitor C2 can be calculated using the following formula:

[0074]

[0075] In the formula, C represents the values ​​of the first capacitor C1 and the second capacitor C2, in F; I0 represents the output current formed by the first positive and negative voltage signals, in A; V0 represents the output voltage formed by the first positive and negative voltage signals, in V; and fsw represents the switching frequency of chip U1, in Hz.

[0076] Furthermore, the value of the third capacitor C3 can be calculated using the following formula:

[0077]

[0078] In the formula, C is the value of the third capacitor C3, in F; I0 is the output current formed by the first positive and negative voltage signals, in A; fsw is the switching frequency of chip U1, in Hz; V i The input voltage is formed by the above power supply voltage, in volts (V). D is the duty cycle, and fsw is the switching frequency of chip U1, in Hz.

[0079] Furthermore, the value of the inductor L1 can be calculated using the following formula:

[0080]

[0081] In the formula, L is the value of inductance L1, in H and V. i The input voltage is formed by the aforementioned power supply voltage, in volts (V). D is the duty cycle. I0 is the output current formed by the aforementioned first positive and negative voltage signals, in amperes (A). fsw is the switching frequency of chip U1, in Hz.

[0082] In the specific implementation, the aforementioned power supply voltage is input to the DC-DC boost converter module 1 from the VIN interface, and simultaneously filtered by the third capacitor C3 to ensure the stability of the power supply voltage. The power supply voltage is input to the fifth and fourth pins of chip U1. When the first pin of chip U1 is turned on, the inductor L1 begins to store energy. When the first pin of chip U1 is turned off, the inductor L1 begins to release energy. The chip U1 converts the power supply voltage into a first PWM signal and a second PWM signal through a switching action. The first capacitor C1 couples the first PWM signal to the first output submodule 21, and the second capacitor C2 couples the second PWM signal to the second output submodule 22. At the same time, the aforementioned chip U1 receives the first positive voltage signal collected by the voltage feedback module 3 through the third pin, and adjusts the duty cycle according to the voltage feedback signal. The adjusted first PWM signal is output to the first output submodule 21 through the first capacitor C1, and the adjusted second PWM signal is output to the second output submodule 22 through the second capacitor C2.

[0083] Furthermore, continue to refer to Figure 2 ,like Figure 2 As shown, the first output submodule 21 includes: a first dual diode D1, a fourth capacitor C4, and a Zener diode ZD;

[0084] In this configuration, the first pin of the first dual diode D1 is connected to one end of the fourth capacitor C4, the end of the fourth capacitor C4 near the first pin of the first dual diode D1 is connected to the anode of the Zener diode ZD, the second pin of the first dual diode D1 is connected to the other end of the fourth capacitor C4, the end of the fourth capacitor C4 near the second pin of the first dual diode D1 is connected to the cathode of the Zener diode ZD, the end of the fourth capacitor C4 near the cathode of the Zener diode ZD is grounded, and the third pin of the first dual diode D1 is connected to the end of the first capacitor C1 furthest from the chip U1.

[0085] It should be noted that the aforementioned first dual diode D1, fourth capacitor C4, and Zener diode ZD form a negative voltage rectification and filtering output structure. The negative voltage portion can be directly extracted, thereby outputting the first negative voltage signal through the VON interface. The first dual diode D1 rectifies the first PWM signal, avoiding electromagnetic radiation problems caused by excessive parasitic inductance and capacitance due to excessively long wires leading out of the component package. The fourth capacitor C4 filters the signal rectified by the first dual diode D1, and also avoids electromagnetic radiation problems caused by excessively long parasitic inductance and capacitance due to excessively long wires leading out of the component package. The Zener diode ZD clamps the waveform after filtering by the fourth capacitor C4, ensuring that the output voltage does not fluctuate due to load changes.

[0086] Furthermore, in order to achieve the above functions, the selection of the first dual diode D1 should meet the following criteria: forward current IF = 2 × I0, reverse withstand voltage C ≥ 1.2 × V0, where I0 is the output current formed by the first positive and negative voltage signals, in A, and V0 is the output voltage formed by the first positive and negative voltage signals, in V.

[0087] Understandably, according to the above criteria, the first dual diode D1 can be a BAT54S or other dual diodes that meet the above criteria. This implementation does not impose any restrictions on this.

[0088] Furthermore, the value of the fourth capacitor C4 can be calculated using the following formula:

[0089]

[0090] In the formula, C is the value of the fourth capacitor C4, in F; I0 is the output current formed by the first positive and negative voltage signals, in A; fsw is the switching frequency of chip U1, in Hz; V0 is the output voltage formed by the first positive and negative voltage signals, in V; D is the duty cycle; and fsw is the switching frequency of chip U1, in Hz.

[0091] Furthermore, to achieve the above functions, the selection of the Zener diode ZD should meet the following criteria: clamping voltage V zt =V0, where V0 is the output voltage formed by the first positive and negative voltage signals mentioned above, and the unit is V.

[0092] In the specific implementation, the first PWM signal is rectified by the first dual diode D1 and then filtered by the fourth capacitor C4. The Zener diode ZD clamps the waveform after filtering by the fourth capacitor C4 to ensure that the output voltage does not fluctuate due to load changes. Finally, the first negative voltage signal is output through the VON interface.

[0093] Furthermore, continue to refer to Figure 2 ,like Figure 2 As shown, the second output submodule 22 includes: a second dual diode D2 and a fifth capacitor C5;

[0094] In this configuration, the first pin of the second dual diode D2 is connected to one end of the fifth capacitor C5, the other end of the fifth capacitor C5 is grounded, the first pin of the second dual diode D2 is also connected to the voltage feedback module 3, the second pin of the second dual diode D2 is grounded, and the third pin of the second dual diode D2 is connected to the end of the second capacitor C2 away from the chip U1.

[0095] It should be understood that the aforementioned second dual diode D2 and fifth capacitor C5 form a negative voltage rectification and filtering output structure, allowing direct extraction of the positive voltage portion. The second dual diode D2 rectifies the second PWM signal, avoiding electromagnetic radiation problems caused by excessively long parasitic inductance L1 and parasitic capacitance due to excessively long wires leading out of the component package. The fifth capacitor C5 filters the signal rectified by the second dual diode D2, and also avoids electromagnetic radiation problems caused by excessively long parasitic inductance L1 and parasitic capacitance due to excessively long wires leading out of the component package.

[0096] Furthermore, in order to achieve the above functions, the selection of the second dual diode D2 should meet the following criteria: forward current IF = 2 × I0, reverse withstand voltage VR ≥ 1.2 × V0, where I0 is the output current formed by the first positive and negative voltage signals, in A, and V0 is the output voltage formed by the first positive and negative voltage signals, in V.

[0097] Understandably, according to the above criteria, the second dual diode D2 can be a BAT54S or other dual diodes that meet the above criteria. This implementation does not impose any restrictions on this.

[0098] Furthermore, the value of the fifth capacitor C5 can be calculated using the following formula:

[0099]

[0100] In the formula, C is the value of the fourth capacitor C4, in F; I0 is the output current formed by the first positive and negative voltage signals, in A; fsw is the switching frequency of chip U1, in Hz; V0 is the output voltage formed by the first positive and negative voltage signals, in V; D is the duty cycle; and fsw is the switching frequency of chip U1, in Hz.

[0101] In the specific implementation, the second PWM signal is rectified by the second dual diode D2 and then filtered by the fifth capacitor C5. At the same time, the rectified first positive voltage signal is input to the voltage feedback module 3.

[0102] Furthermore, the voltage feedback module 3 includes: a first resistor R1 and a second resistor R2;

[0103] Wherein, one end of the first resistor R1 is connected to the first pin of the second dual diode D2, the other end of the first resistor R1 is connected to one end of the second resistor R2, the other end of the second resistor R2 is grounded, and the end of the first resistor R1 closest to the second resistor R2 is connected to the third pin of the chip U1.

[0104] It should be noted that the first resistor R1 and the second resistor R2 form a voltage divider circuit. The end of the first resistor R1 connected to the second bipolar transistor receives the first positive voltage signal and performs voltage division to obtain a voltage feedback signal, which is then output to the third pin of chip U1.

[0105] Understandably, the aforementioned chip U1 has an internal feedback reference voltage. The voltage value of the voltage feedback signal is compared with the reference voltage value. When the voltage value of the voltage feedback signal is greater than the feedback reference voltage value, the duty cycle time is increased, thereby reducing the first positive voltage signal and the first negative voltage signal. The reduced second negative voltage signal is then output from the VON interface, and the reduced second positive voltage signal is output from the VOP interface. When the voltage value of the voltage feedback signal is less than the feedback reference voltage value, the duty cycle time is decreased, thereby increasing the first positive voltage signal and the first negative voltage signal. The increased second negative voltage signal is then output from the VON interface, and the increased second positive voltage signal is output from the VOP interface.

[0106] Furthermore, the values ​​of the first resistor R1 and the second resistor R2 can be determined with reference to the following formula:

[0107]

[0108] In the formula, R1 is the resistance value of the first resistor R1, in Ω; R2 is the resistance value of the second resistor R2, in Ω; V0 is the output voltage composed of the first positive and negative voltage signals, in V; and VBF is the feedback reference voltage of chip U1, in V.

[0109] In a specific implementation, the first resistor R1 acquires the first positive voltage signal, divides the first positive voltage signal to obtain a voltage feedback signal, and transmits the voltage feedback signal to the third pin of the chip U1 to form a closed-loop control.

[0110] Furthermore, to verify the feasibility of the above scheme, verification is conducted according to the above requirements, for example, the input voltage V. i =3.8V, the voltage value of the second positive voltage signal VOP = 7.8V, the voltage value of the second negative voltage signal VON = -7.8V, the output current I0 = 40mA, the output ripple voltage Vrip = 78mV, the chip U1 is SY7208LABC, according to the SY7208LABC datasheet, the switching frequency is 1MHz, the duty cycle D = 0.6 can be calculated using the above formula, the third capacitor C3 = 4.7uF, the inductor L1 = 220uH. The first capacitor C1 = 1uF, the first dual diode D1 and the second dual diode D2 are both BAT54S, the fourth capacitor C4 = 2.2uF, the Zener diode ZD is ZMM55-B8V2_R1_10001, the second capacitor C2 = 1uF, the fifth capacitor C5 = 2.2uF, the second resistor R2 = 10KΩ, according to the SY7208LABC datasheet, the feedback reference voltage VFB = 0.6V, and the first resistor R1 = 120KΩ.

[0111] Furthermore, a 200Ω resistor is used as the output load to simulate an output current I0 = 40mA; refer to Figure 3 , Figure 4 , Figure 5 and Figure 6 , Figure 3 This is a diagram showing the measurement results of the second positive voltage signal in the bias power supply circuit provided in an embodiment of the present invention. Figure 4 This is a diagram showing the measurement results of the second negative voltage signal in the bias power supply circuit provided in an embodiment of the present invention. Figure 5 This is a graph showing the ripple voltage measurement results of the second positive voltage signal in the bias power supply circuit provided in an embodiment of the present invention. Figure 6 This is a graph showing the ripple voltage measurement results of the second negative voltage signal in the bias power supply circuit provided in an embodiment of the present invention. According to... Figure 3 , Figure 4 , Figure 5 and Figure 6 It can be seen that the parameters designed in this scheme and the experimental verification results are consistent with each other by more than 95%, and the overall cost is low.

[0112] In this embodiment, the power supply voltage is input to the DC-DC boost converter module 1 via the VIN interface. It is simultaneously filtered by the third capacitor C3 to ensure voltage stability. The power supply voltage is input to the fifth and fourth pins of chip U1. When the first pin of chip U1 is turned on, inductor L1 begins to store energy; when the first pin of chip U1 is turned off, inductor L1 begins to release energy. Chip U1 converts the power supply voltage into a first PWM signal and a second PWM signal through a switching action. The first capacitor C1 couples the first PWM signal to the first output submodule 21, and the second capacitor C2 couples the second PWM signal to the second output submodule 22. The first PWM signal is rectified by the first dual diode D1 and then filtered by the fourth capacitor C4 to obtain a first negative voltage signal. The second PWM signal is rectified by the second dual diode D2 and then filtered by the fifth capacitor C5 to obtain a first positive voltage signal. The first resistor R1 acquires the first positive voltage signal and divides it to obtain a voltage feedback signal. This voltage feedback signal is then transmitted to the third pin of chip U1. Chip U1 has an internal feedback reference voltage. The voltage value of the feedback signal is compared with the reference voltage value. When the voltage value of the feedback signal is greater than the feedback reference voltage value, the duty cycle time is increased, thereby reducing the first positive and first negative voltage signals. The resulting second negative voltage signal is output from the VON interface, and the resulting second positive voltage signal is output from the VOP interface. Conversely, when the voltage value of the feedback signal is less than the feedback reference voltage value, the duty cycle time is decreased, thereby increasing the first positive and first negative voltage signals. The resulting second negative voltage signal is output from the VON interface, and the resulting second positive voltage signal is output from the VOP interface, thus achieving closed-loop control.

[0113] The above are merely preferred embodiments of the present invention and do not limit the scope of the patent. Any equivalent structural or procedural transformations made based on the description and drawings of the present invention, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of the present invention.

Claims

1. A bias power supply circuit, characterized by comprising: The bias power supply circuit comprises a direct current boost conversion module, an output module and a voltage feedback module; The direct current boost conversion module is connected with the output module and the voltage feedback module respectively, and the voltage feedback module is further connected with the output module; The direct current boost conversion module is configured to process a power supply voltage into a first PWM signal and a second PWM signal; The output module is configured to convert the first PWM signal to obtain a first negative voltage signal, and convert the second PWM signal to obtain a first positive voltage signal; The voltage feedback module is configured to collect the first positive voltage signal and obtain a voltage feedback signal according to the first positive voltage signal; The direct current boost conversion module is further configured to adjust the duty cycle of the first PWM signal and the second PWM signal according to the voltage feedback signal; The output module is configured to convert the adjusted first PWM signal to obtain a second negative voltage signal, and convert the adjusted second PWM signal to obtain a second positive voltage signal, wherein the second negative voltage signal and the second positive voltage signal are used to supply power to a liquid crystal screen; The output module comprises a first output submodule and a second output submodule; The first output submodule is configured to convert the first PWM signal to obtain a first negative voltage signal; The second output submodule is configured to convert the second PWM signal to obtain a first positive voltage signal; The first output submodule is further configured to convert the adjusted first PWM signal to obtain a second negative voltage signal; The second output submodule is further configured to convert the adjusted second PWM signal to obtain a second positive voltage signal.

2. The bias supply circuit of claim 1, wherein, The direct current boost conversion module comprises a chip, a first capacitor, a second capacitor, a third capacitor and an inductor; The first pin of the chip is connected with one end of the first capacitor, one end of the second capacitor and one end of the inductor, the other end of the first capacitor is connected with the first output submodule, the other end of the second capacitor is connected with the second output submodule, the other end of the inductor is connected with the third capacitor, the other end of the third capacitor is grounded, the second pin of the chip is grounded, the third pin of the chip is connected with the voltage feedback module, the fourth pin of the chip is connected with the fifth pin of the chip, and the fifth pin of the chip is connected with one end of the inductor close to the third capacitor.

3. The bias supply circuit of claim 2, wherein, The first output submodule comprises a first double diode, a fourth capacitor and a voltage stabilizing diode; The first pin of the first double diode is connected with one end of the fourth capacitor, one end of the fourth capacitor close to the first pin of the first double diode is connected with the anode of the voltage stabilizing diode, the second pin of the first double diode is connected with the other end of the fourth capacitor, one end of the fourth capacitor close to the second pin of the first double diode is connected with the cathode of the voltage stabilizing diode, one end of the fourth capacitor close to the cathode of the voltage stabilizing diode is grounded, and the third pin of the first double diode is connected with one end of the first capacitor away from the chip.

4. The bias power supply circuit of claim 3, wherein, The model of the first double diode is BAT54S.

5. The bias power supply circuit of any one of claims 2 to 4, wherein, The second output sub-module comprises a second double diode and a fifth capacitor. The first pin of the second double diode is connected with one end of the fifth capacitor, the other end of the fifth capacitor is grounded, the first pin of the second double diode is also connected with the voltage feedback module, the second pin of the second double diode is grounded, and the third pin of the second double diode is connected with one end of the second capacitor away from the chip.

6. The bias supply circuit of claim 5, wherein, The model of the second double diode is BAT54S.

7. The bias supply circuit of claim 6, wherein, The voltage feedback module comprises a first resistor and a second resistor. One end of the first resistor is connected with the first pin of the second double diode, the other end of the first resistor is connected with one end of the second resistor, the other end of the second resistor is grounded, and one end of the first resistor close to the second resistor is connected with the third pin of the chip.

8. A bias power supply apparatus, characterized by comprising: The bias power supply device comprises the bias power supply circuit in any one of claims 1 to 7.

9. A liquid crystal panel, characterized by comprising: The liquid crystal screen comprises the bias power supply device in claim 8.

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