Drive circuit and memory

Abstract

This application relates to a driving circuit and a memory. The driving circuit includes: a main driving module for receiving a first signal and generating a second signal based on the first signal; and an auxiliary driving module whose output terminal is connected to the output terminal of the main driving module, and whose first input terminal is used to receive the first signal. The auxiliary driving module and the main driving module jointly generate the second signal. The second signal has three level values, denoted as a first level value, a second level value, and a third level value. The first signal has two level values, namely the first level value and the second level value, and the third level value is greater than the first level value and less than the second level value. By using the active driving module and the auxiliary driving module to pull down and stabilize the second level value of the first signal to the third level value before generating the second signal, the amplitude of the first signal is weakened, the level transition time is reduced, and the transmitted data signal is stabilized.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a driver circuit and a memory. Background Technology

[0002] For frequently switching high-frequency signals like "1,0,1,0,1,0,...", the attenuation is more severe than for continuous low-frequency signals like "1,1,1,0,0,0,...". Furthermore, the high-frequency "1,0,1,0,1,0,..." generates inter-symbol interference (ISI). DRAM is a high-speed data transfer memory; the increased signal transmission rate leads to greater channel losses and more severe ISI, further affecting the integrity and accuracy of the memory's output data signals. Summary of the Invention

[0003] This application provides a driving circuit and a memory, which can optimize the integrity and accuracy of the memory output signal.

[0004] To achieve the above objectives, in one respect, the present invention provides a driving circuit, comprising:

[0005] The main drive module is used to receive the first signal and generate the second signal based on the first signal;

[0006] An auxiliary drive module has its output terminal connected to the output terminal of the main drive module, and its first input terminal is used to receive the first signal. The auxiliary drive module and the main drive module jointly generate the second signal.

[0007] The second signal has three level values, referred to as the first level value, the second level value, and the third level value, respectively. The first signal has two level values, referred to as the first level value and the second level value, respectively. The third level value is greater than the first level value and less than the second level value.

[0008] In one embodiment, the second input terminal of the auxiliary drive module is used to receive a pulse control signal, and the auxiliary drive module is used to pull down the first signal from the second level value to the third level value when the pulse control signal is received.

[0009] In one embodiment, the first level value is low, and the second and third level values ​​are both high.

[0010] In one embodiment, the main drive module includes:

[0011] The first pull-up transistor has a control terminal for receiving the first signal and a first terminal connected to the power supply voltage.

[0012] A first pull-down transistor, the control terminal of the first pull-down transistor is connected to the control terminal of the first pull-up transistor, the first terminal of the first pull-down transistor is connected to the ground terminal, and the second terminal of the first pull-down transistor is connected to the second terminal of the first pull-up transistor.

[0013] The second pull-up transistor has its control terminal connected to the second terminal of the first pull-up transistor, and its first terminal connected to the power supply voltage.

[0014] The second pull-down transistor has its control terminal connected to the control terminal of the second pull-up transistor. The first terminal of the second pull-down transistor is connected to the ground terminal, and the second terminal of the second pull-down transistor is connected to the second terminal of the second pull-up transistor. It is used to output the second signal.

[0015] The first signal is used to control the turning on and off of the first pull-up transistor, the first pull-down transistor, the second pull-up transistor, and the second pull-down transistor to generate the second signal.

[0016] In one embodiment, the first pull-up transistor and the second pull-up transistor are both P-type transistors, and the first pull-down transistor and the second pull-down transistor are both N-type transistors.

[0017] In one embodiment, the first terminal of the first pull-up transistor is the drain of the first pull-up transistor, and the second terminal of the first pull-up transistor is the source of the first pull-up transistor; the first terminal of the first pull-down transistor is the source of the first pull-down transistor, and the second terminal of the first pull-down transistor is the drain of the first pull-down transistor; the first terminal of the second pull-up transistor is the drain of the second pull-up transistor, and the second terminal of the second pull-up transistor is the source of the second pull-up transistor; the first terminal of the second pull-down transistor is the source of the second pull-down transistor, and the second terminal of the second pull-down transistor is the drain of the second pull-down transistor.

[0018] In one embodiment, the driving circuit further includes:

[0019] The first pulse generation module has a first input terminal for receiving a first even pulse signal, a second input terminal for receiving a first odd pulse signal, a third input terminal for receiving a first data strobe signal, a fourth input terminal for receiving a second data strobe signal, and an output terminal connected to the second input terminal of the auxiliary drive module.

[0020] The first pulse generation module is used to generate the pulse control signal based on the first even pulse signal, the first odd pulse signal, the first data strobe signal, and the second data strobe signal;

[0021] The second data strobe signal is the inverted signal of the first data strobe signal.

[0022] In one embodiment, the first pulse generation module is used to superimpose the received first even pulse signal and the first odd pulse signal to generate a pre-pulse control signal, and generate the pulse control signal after eliminating the continuously generated pulse signals in the pre-pulse control signal according to the received first data gating signal and the second data gating signal.

[0023] In one embodiment, the driving circuit further includes:

[0024] The second pulse generation module has a first input terminal for receiving a second even pulse signal, a second input terminal for receiving a second odd pulse signal, a third input terminal for receiving an even data signal, a fourth input terminal for receiving an odd data signal, a first output terminal connected to the first input terminal of the first pulse generation module, and a second output terminal connected to the second input terminal of the first pulse generation module.

[0025] The second pulse generation module is used to generate the first even pulse signal and the first odd pulse signal respectively based on the received second even pulse signal, second odd pulse signal, even data signal and odd data signal.

[0026] In one embodiment, the second pulse generation module is configured to respond to the second even pulse signal and generate the first even pulse signal when the even data signal is a valid level signal; the second pulse generation module is configured to respond to the second odd pulse signal and generate the first odd pulse signal when the odd data signal is a valid level signal.

[0027] In one embodiment, the effective level signal of the even data signal and the effective level signal of the odd data signal are both high-level signals.

[0028] In one embodiment, the driving circuit further includes:

[0029] A rising edge detection module, wherein the first input terminal of the rising edge detection module is used to receive the first data strobe signal, the second input terminal of the rising edge detection module is used to receive the second data strobe signal, the third input terminal of the rising edge detection module is used to receive the readout strobe signal, the first output terminal of the rising edge detection module is connected to the first input terminal of the second pulse generation module, and the second output terminal of the rising edge detection module is connected to the second input terminal of the second pulse generation module;

[0030] The rising edge detection module is used to generate the second even pulse signal and the second odd pulse signal based on the received first data gating signal, the second data gating signal, and the readout gating signal, respectively.

[0031] In one embodiment, when the readout strobe signal is a valid level signal, the rising edge detection module is used to respond to the rising edge of the first data strobe signal and generate the second even pulse signal; the rising edge detection module is also used to respond to the rising edge of the second data strobe signal after generating the second even pulse signal and generate the second odd pulse signal.

[0032] In one embodiment, the effective level signal of the readout strobe signal is a high level signal.

[0033] The present invention also provides a memory including the driving circuit described above.

[0034] The aforementioned driving circuit and memory include a main driving module for receiving a first signal and generating a second signal based on the first signal; and an auxiliary driving module whose output terminal is connected to the output terminal of the main driving module, and whose first input terminal is used to receive the first signal. The auxiliary driving module and the main driving module jointly generate the second signal. The second signal has three level values, denoted as a first level value, a second level value, and a third level value. The first signal has two level values, namely the first level value and the second level value. The third level value is greater than the first level value and less than the second level value. By using the active driving module and the auxiliary driving module to pull down and stabilize the second level value of the first signal to a third level value before generating the second signal, the amplitude of the first signal is weakened, the level transition time is reduced, the transmitted data signal is stabilized, and the integrity and accuracy of the output signal are improved. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a schematic diagram of the drive circuit in the first embodiment;

[0037] Figure 2 This is a schematic diagram of the first signal and the second signal in one embodiment;

[0038] Figure 3 This is a schematic diagram of the drive circuit in the second embodiment;

[0039] Figure 4 This is a schematic diagram of the drive circuit in the third embodiment;

[0040] Figure 5 This is a schematic diagram of the drive circuit in the fourth embodiment;

[0041] Figure 6 This is a schematic diagram of the drive circuit in the fifth embodiment;

[0042] Figure 7 This is a schematic diagram of the drive circuit in the sixth embodiment;

[0043] Figure 8 for Figure 7 A corresponding embodiment shows the signal timing diagram.

[0044] Explanation of reference numerals in the attached figures:

[0045] 100. Main drive module; 102. First pull-up transistor; 104. First pull-down transistor; 106. Second pull-up transistor; 108. Second pull-down transistor; 200. Auxiliary drive module; 300. First pulse generation module; 400. Second pulse generation module; 500. Rising edge detection module. Detailed Implementation

[0046] To facilitate understanding of the embodiments of this application, a more comprehensive description of the embodiments of this application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the embodiments of this application. However, the embodiments of this application can be implemented in many different forms and are not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the embodiments of this application more thorough and complete.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which embodiments of this application belong. The terminology used herein in the description of embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments of this application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0048] In the description of the embodiments of this application, it should be understood that the terms "upper", "lower", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the method or positional relationship shown in the drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0049] It is understood that the terms "first," "second," etc., used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first input terminal may be referred to as a second input terminal, and similarly, a second input terminal may be referred to as a first input terminal. Both the first input terminal and the second input terminal are input terminals, but they are not the same input terminal.

[0050] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. In the description of this application, "several" means at least one, such as one, two, etc., unless otherwise explicitly specified.

[0051] Figure 1 This is a schematic diagram of the drive circuit in the first embodiment. Figure 2 This is a schematic diagram of the first and second signals in one embodiment. See also... Figure 1 , Figure 2In this embodiment, the driving circuit includes a main driving module 100 and an auxiliary driving module 200. The main driving module 100 receives a first signal Full_Data and generates a second signal Final_Data based on the first signal Full_Data. The second signal Final_Data has three level values, denoted as a first level value Vol, a second level value VDDQ, and a third level value Voh. The first signal Full_Data has two level values, namely the first level value Vol and the second level value VDDQ. The third level value Voh is greater than the first level value Vol and less than the second level value VDDQ. The output terminal of the auxiliary driving module 200 is connected to the output terminal of the active driving module 100. The first input terminal of the auxiliary driving module 200 receives the first signal Full_Data. The auxiliary driving module 200 and the active driving module 100 jointly generate the second signal Final_Data. The main driving module 100 obtains data signals from the logic circuit of the memory, processes the obtained data signals, and transmits the processed signals to the controller through a signal channel, thereby realizing the transmission of data signals. In this embodiment, the first signal Full_Data is the data signal obtained by the main drive module 100 from the logic control circuit, and the second signal Final_Data is the signal sent to the signal channel after processing by the main drive module 100. By processing the first signal Full_Data through the main drive module 100 and the auxiliary drive module 200, the second level value VDDQ in the first signal Full_Data is pulled down and stabilized at a third level value Voh, which is greater than the first level value Vol, to generate the second signal Final_Data. This weakens the level amplitude of the first signal Full_Data, making the data signal transmission more stable and improving the integrity and accuracy of the transmitted data signal.

[0052] For example, the memory can be Dynamic Random Access Memory (DRAM) and Static Random-Access Memory (SRAM). Specifically, it can be DRAM, SRAM, Thyristor RAM (TRAM), Zero Capacitor RAM (Z-RAM), Dual Transistor RAM (TTRAM), MRAM, etc., of low-power DDR4 (LPDDR4) or LPDDR4X memory.

[0053] Specifically, data signal reading and writing are performed in response to clock signals. Therefore, if the data signal to be written has not reached the target level when the rising edge and / or falling edge of the clock signal arrives, it will lead to data read / write errors. For example, if the data to be written at the current clock signal edge is 0, while the data to be written at the previous clock signal edge is 1, then the second signal Final_Data needs to be pulled down from the high level range to the low level range between the two adjacent clock signal edges, for example, from 1.0V to 0.1V, in order to achieve accurate transmission of the second signal Final_Data. If the second signal Final_Data has not reached the low level range when the current clock signal edge arrives, the signal transmitted to the signal channel will be a high level signal, that is, the actual second signal Final_Data has not been accurately transmitted to the signal channel, thus resulting in a transmission error of the second signal Final_Data.

[0054] Figure 3 This is a schematic diagram of the drive circuit in the second embodiment. See also... Figure 3 In this embodiment, the second input terminal of the auxiliary drive module 200 is used to receive the pulse control signal Final_AP. The auxiliary drive module 200, upon receiving the pulse control signal Final_AP, pulls down the first signal Full_Data from the second level value VDDQ to the third level value Voh. Specifically, after receiving a valid pulse control signal Final_AP, the auxiliary drive module 200, together with the main control module 100, pulls down the second level value VDDQ in the first signal Full_Data and stabilizes it at a third level value Voh, which is greater than the first level value Vol. Then, it generates the second signal Final_Data, weakening the amplitude of the first signal Full_Data, making the data signal transmission more stable and improving the integrity and accuracy of the transmitted data signal. It can be understood that the pulse control signal Final_AP can be generated by the drive circuit based on the received signal, or it can be directly received by the drive circuit. The pulse control signal Final_AP is used for real-time de-emphasis of the data signal transmission.

[0055] In one embodiment, the first voltage level Vol is low, and the second voltage level VDDQ and the third voltage level Voh are both high. For example, when the power supply voltage is 1.2V, a voltage level less than or equal to 0.2V can be considered low, and a voltage level greater than or equal to 1.0V can be considered high. In practical applications, the voltage ranges for low and high levels can be set as needed.

[0056] Figure 4 This is a schematic diagram of the drive circuit in the third embodiment. See also... Figure 3In this embodiment, the main drive module 100 includes: a first pull-up transistor 102, a first pull-down transistor 104, a second pull-up transistor 106, and a second pull-down transistor 108. The control terminal of the first pull-up transistor 102 is used to receive the first signal Full_Data, and its first terminal is connected to the power supply voltage VDDQ. The control terminal of the first pull-down transistor 104 is connected to the control terminal of the first pull-up transistor 102, its first terminal is connected to ground, and its second terminal is connected to the second terminal of the first pull-up transistor 102. The control terminal of the second pull-up transistor 106 is connected to the second terminal of the first pull-up transistor 102, and its first terminal is connected to the power supply voltage VDDQ. The control terminal of the second pull-down transistor 108 is connected to the control terminal of the second pull-up transistor 106, its first terminal is connected to ground, and its second terminal is connected to the second terminal of the second pull-up transistor 106, and it is used to output the second signal Final_Data. The first signal Full_Data is used to control the on and off states of the first pull-up transistor 102, the first pull-down transistor 104, the second pull-up transistor 106, and the second pull-down transistor 108 to generate the second signal Final_Data.

[0057] Furthermore, the first pull-up transistor 102 and the second pull-up transistor 106 are both P-type transistors, and the first pull-down transistor 104 and the second pull-down transistor 108 are both N-type transistors.

[0058] Furthermore, the first terminal of the first pull-up transistor 102 is the source of the first pull-up transistor 102, and the second terminal of the first pull-up transistor 102 is the drain of the first pull-up transistor 102; the first terminal of the first pull-down transistor 104 is the source of the first pull-down transistor 104, and the second terminal of the first pull-down transistor 104 is the drain of the first pull-down transistor 104; the first terminal of the second pull-up transistor 106 is the source of the second pull-up transistor 106, and the second terminal of the second pull-up transistor 106 is the drain of the second pull-up transistor 106; the first terminal of the second pull-down transistor 108 is the source of the second pull-down transistor 108, and the second terminal of the second pull-down transistor 108 is the drain of the second pull-down transistor 108.

[0059] Figure 5 This is a schematic diagram of the drive circuit in the fourth embodiment. See also... Figure 5In this embodiment, the pulse control signal Final_AP is generated by the driving circuit based on the received signal. The driving circuit further includes a first pulse generation module 300. The first input terminal of the first pulse generation module 300 is used to receive the first even pulse signal Even_D_AP, the second input terminal is used to receive the first odd pulse signal Odd_D_AP, the third input terminal is used to receive the first data strobe signal DQS, and the fourth input terminal is used to receive the second data strobe signal DQSn. The output terminal of the first pulse generation module 300 is connected to the second input terminal of the auxiliary driving module 200. The first pulse generation module 300 is used to generate a pulse control signal Final_AP based on the first even pulse signal Even_D_AP, the first odd pulse signal Odd_D_AP, the first data strobe signal DQS, and the second data strobe signal DQSn; wherein, the second data strobe signal DQSn is the inverted signal of the first data strobe signal DQS, that is, the superposition of the second data strobe signal DQSn and the first data strobe signal DQS results in a signal with a level of zero.

[0060] Furthermore, the first pulse generation module 300 superimposes the received first even pulse signal Even_D_AP and the first odd pulse signal Odd_D_AP to generate a pre-pulse control signal Pre_F_AP as an intermediate signal. That is, it combines the first even pulse signal Even_D_AP and the first odd pulse signal Odd_D_AP with the real-time data to be transmitted to generate a 0->1 pre-pulse control signal Pre_F_AP. Then, based on the received first data gating signal DQS and second data gating signal DQSn, it eliminates the continuously generated pulse signals in the pre-pulse control signal Pre_F_AP to generate the pulse control signal Final_AP. For example, it combines the pre-pulse control signal Pre_F_AP with the first data gating signal DQS and the second data gating signal DQSn, and uses a counter to eliminate the continuously generated pulses in the pre-pulse control signal Pre_F_AP, thereby generating the pulse control signal Final_AP. It is understood that the first even pulse signal Even_D_AP and / or the first odd pulse signal Odd_D_AP can be generated by the driving circuit based on the received signal, or they can be directly received by the driving circuit.

[0061] Figure 6 The diagram below shows the structure of the driving circuit in the fifth embodiment. In this embodiment, the driving circuit further includes a second pulse generation module 400. The first even pulse signal Even_D_AP and the first odd pulse signal Odd_D_AP are both generated by the second pulse generation module 400 in the driving circuit based on the received signals.

[0062] The first input terminal of the second pulse generation module 400 is used to receive the second even pulse signal Even_AP, the second input terminal is used to receive the second odd pulse signal Odd_AP, the third input terminal is used to receive the even data signal Even_Data, and the fourth input terminal is used to receive the odd data signal Odd_Data. The first output terminal of the second pulse generation module 400 is connected to the first input terminal of the first pulse generation module 300, and the second output terminal of the second pulse generation module 400 is connected to the second input terminal of the first pulse generation module 300. The second pulse generation module 400 is used to generate the first even pulse signal Even_D_AP and the first odd pulse signal Odd_D_AP based on the received second even pulse signal Even_AP, second odd pulse signal Odd_AP, even data signal Even_Data, and odd data signal Odd_Data, respectively. Similarly, it can be understood that the second even pulse signal Even_AP and / or the second odd pulse signal Odd_AP can be generated by the driving circuit based on the received signal, or can be directly received by the driving circuit.

[0063] Furthermore, the second pulse generation module 400 responds to the second even pulse signal Even_AP and generates the first even pulse signal Even_D_AP when the even data signal Even_Data is an active level signal; the second pulse generation module 400 responds to the second odd pulse signal Odd_AP and generates the first odd pulse signal Odd_D_AP when the odd data signal Odd_Data is an active level signal.

[0064] Furthermore, the effective level signals for both the even data signal Even_Data and the odd data signal Odd_Data are high-level signals. In other embodiments, the high-level signal or the low-level signal can be set as the effective level signal for the even data signal Even_Data and / or the odd data signal Odd_Data, depending on actual needs.

[0065] Figure 7 The diagram below shows the structure of the driving circuit in the sixth embodiment. In this embodiment, the driving circuit further includes a rising edge detection module 500. The second even pulse signal Even_AP and the second odd pulse signal Odd_AP are both generated by the rising edge detection module 500 in the driving circuit based on the received signals.

[0066] The first input terminal of the rising edge detection module 500 is used to receive the first data strobe signal DQS, the second input terminal of the rising edge detection module 500 is used to receive the second data strobe signal DQSn, and the third input terminal of the rising edge detection module 500 is used to receive the readout strobe signal RD_PW. The first output terminal of the rising edge detection module 500 is connected to the first input terminal of the second pulse generation module 400, and the second output terminal of the rising edge detection module 500 is connected to the second input terminal of the second pulse generation module 400. The rising edge detection module 500 is used to generate a second even pulse signal Even_AP and a second odd pulse signal Odd_AP according to the received first data strobe signal DQS, second data strobe signal DQSn, and readout strobe signal RD_PW, respectively.

[0067] Furthermore, when the readout strobe signal RD_PW is a valid level signal, the rising edge detection module 500 is used to respond to the rising edge of the first data strobe signal DQS and generate the second even pulse signal Even_AP; the rising edge detection module 500 is also used to respond to the rising edge of the second data strobe signal DQSn after generating the second even pulse signal Even_AP and generate the second odd pulse signal Odd_AP.

[0068] Furthermore, the effective level signal of the strobe signal RD_PW is read as a high-level signal. In other embodiments, the effective level signal of the strobe signal RD_PW is read as a low-level signal.

[0069] Figure 8 for Figure 7 A corresponding signal timing diagram is shown in one embodiment. See also... Figure 7 , Figure 8 The operation of the driving circuit of this application is described exemplarily. The driving circuit can receive existing first data strobe signal DQS, second data strobe signal DQSn, readout strobe signal RD_PW, even data signal Even_Data, odd data signal Odd_Data, and first signal Full_Data, and output second signal Final_Data. The second data strobe signal DQSn is the inverted signal of the first data strobe signal DQS. For example, when the first data strobe signal DQS is high, the second data strobe signal DQSn is low. Each pulse signal is composed of multiple initial pulses.

[0070] In the first step, when the readout strobe signal RD_PW is low, the rising edge detection module 500 responds to the first rising edge 1 of the first data strobe signal DQS, generating a second even pulse signal Even_AP. After generating the second even pulse signal Even_AP (after the first initial pulse of Even_AP), it begins to respond to the rising edge of the second data strobe signal DQSn, generating a second odd pulse signal Odd_AP. It can be understood that the second even pulse signal Even_AP is generated earlier than the second odd pulse signal Odd_AP. In the second step, the second pulse generation module 400 responds to the second even pulse signal Even_AP, generating a first even pulse signal Even_D_AP when the even data signal Even_Data is high. Simultaneously, the second pulse generation module 400 responds to the second odd pulse signal Odd_AP, generating a first odd pulse signal Odd_D_AP when the odd data signal Odd_Data is high. The levels of the even data signal Even_Data and the odd data signal Odd_Data can be any level between high and low. Thirdly, the first pulse generation module 300 first superimposes the received first even pulse signal Even_D_AP and the first odd pulse signal Odd_D_AP to generate a pre-pulse control signal Pre_F_AP as an intermediate signal. Then, based on the received first data gating signal DQS and second data gating signal DQSn, it eliminates the continuously generated pulse signals (initial pulse A and initial pulse B) in the pre-pulse control signal Pre_F_AP to generate the pulse control signal Final_AP. Specifically, the initial pulses A, B, and C in the pre-pulse control signal Pre_F_AP correspond to the continuous data gating signals on the first data gating signal DQS or the second data gating signal DQSn. The initial pulse C generated first in the pre-pulse control signal Pre_F_AP is retained, while the initial pulses A and B are removed to obtain the pulse control signal Final_AP. In the fourth step, the auxiliary drive module 200, together with the main control module 100, pulls the first signal Full_Data down from the second level value VDDQ to the third level value Voh based on the pulse control signal Final_AP, thus obtaining the second signal Final_Data. The time T1 for the second signal Final_Data to reach the second level value VDDQ is greater than or equal to the width T2 of the initial pulse in the pulse control signal Final_AP, and less than the time T3 for the first signal Full_Data to reach the second level value VDDQ. It can be understood that the time for the voltage corresponding to the second signal Final_Data to transition from a low level to the voltage corresponding to the third level value Voh is the same as the time for the voltage corresponding to the second signal Final_Data to transition from a low level to the voltage corresponding to the third level value Voh.The pulse control signal Final_AP generates a real-time de-emphasized data signal for transmission. It keeps the amplitude of the rising and falling edges of the second signal Final_Data unchanged, weakens the amplitude in other places, and reduces the level transition time, thereby ensuring stable transmission and reducing power consumption.

[0071] For example, the effective level duration of the readout strobe signal RD_PW is greater than the duration during which the signals in the first data strobe signal DQS and the second data strobe signal DQSn remain at the same level; the pulse widths of the second even pulse signal Even_AP and the second odd pulse signal Odd_AP are the same and less than the duration during which the signals in the first data strobe signal DQS and the second data strobe signal DQSn remain at the same level; the duration during which the even data signal Even_Data and the odd data signal Odd_Data remain at the same level is greater than the pulse widths of the second even pulse signal Even_AP and the second odd pulse signal Odd_AP; the pulse width of the first even pulse signal Even_D_AP is equal to the pulse width of the second even pulse signal Even_AP; and the pulse width of the first odd pulse signal Odd_D_AP is equal to the pulse width of the second odd pulse signal Odd_AP.

[0072] The present invention also provides a memory including the driving circuit described above.

[0073] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0074] The above-described embodiments are merely illustrative of several implementation methods of the embodiments of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the embodiments of this application, and these all fall within the protection scope of the embodiments of this application. Therefore, the protection scope of the patent for the embodiments of this application should be determined by the appended claims.

Claims

1. A driving circuit, characterized in that, include: The main drive module is used to receive a first signal and generate a second signal based on the first signal; An auxiliary drive module has its output terminal connected to the output terminal of the main drive module, and its first input terminal is used to receive the first signal. The auxiliary drive module and the main drive module jointly generate the second signal. The second signal has three voltage levels, denoted as the first voltage level, the second voltage level, and the third voltage level, while the first signal has two voltage levels, denoted as the first voltage level and the second voltage level, and the third voltage level is greater than the first voltage level and less than the second voltage level. The second input terminal of the auxiliary drive module is used to receive a pulse control signal, and the auxiliary drive module is used to pull down the first signal from the second level value to the third level value when the pulse control signal is received; The driving circuit also includes: The first pulse generation module has a first input terminal for receiving a first even pulse signal, a second input terminal for receiving a first odd pulse signal, a third input terminal for receiving a first data strobe signal, a fourth input terminal for receiving a second data strobe signal, and an output terminal connected to the second input terminal of the auxiliary drive module. The first pulse generation module is used to generate the pulse control signal based on the first even pulse signal, the first odd pulse signal, the first data strobe signal, and the second data strobe signal; The second data strobe signal is the inverted signal of the first data strobe signal.

2. The driving circuit according to claim 1, characterized in that, The first level value is low, and the second and third level values ​​are both high.

3. The driving circuit according to claim 1, characterized in that, The main drive module includes: The first pull-up transistor has a control terminal for receiving the first signal and a first terminal connected to the power supply voltage. A first pull-down transistor, the control terminal of the first pull-down transistor is connected to the control terminal of the first pull-up transistor, the first terminal of the first pull-down transistor is connected to the ground terminal, and the second terminal of the first pull-down transistor is connected to the second terminal of the first pull-up transistor. The second pull-up transistor has its control terminal connected to the second terminal of the first pull-up transistor, and its first terminal connected to the power supply voltage. The second pull-down transistor has its control terminal connected to the control terminal of the second pull-up transistor. The first terminal of the second pull-down transistor is connected to the ground terminal, and the second terminal of the second pull-down transistor is connected to the second terminal of the second pull-up transistor. It is used to output the second signal. The first signal is used to control the turning on and off of the first pull-up transistor, the first pull-down transistor, the second pull-up transistor, and the second pull-down transistor to generate the second signal.

4. The driving circuit according to claim 3, characterized in that, Both the first pull-up transistor and the second pull-up transistor are P-type transistors, and both the first pull-down transistor and the second pull-down transistor are N-type transistors.

5. The driving circuit according to claim 4, characterized in that, The first terminal of the first pull-up transistor is the drain of the first pull-up transistor, and the second terminal of the first pull-up transistor is the source of the first pull-up transistor; the first terminal of the first pull-down transistor is the source of the first pull-down transistor, and the second terminal of the first pull-down transistor is the drain of the first pull-down transistor; the first terminal of the second pull-up transistor is the drain of the second pull-up transistor, and the second terminal of the second pull-up transistor is the source of the second pull-up transistor. The first terminal of the second pull-down transistor is the source of the second pull-down transistor, and the second terminal of the second pull-down transistor is the drain of the second pull-down transistor.

6. The driving circuit according to claim 1, characterized in that, The first pulse generation module is used to superimpose the received first even pulse signal and the first odd pulse signal to generate a pre-pulse control signal, and to generate the pulse control signal after eliminating the continuously generated pulse signals in the pre-pulse control signal according to the received first data gating signal and the second data gating signal.

7. The driving circuit according to claim 1, characterized in that, Also includes: The second pulse generation module has a first input terminal for receiving a second even pulse signal, a second input terminal for receiving a second odd pulse signal, a third input terminal for receiving an even data signal, a fourth input terminal for receiving an odd data signal, a first output terminal connected to the first input terminal of the first pulse generation module, and a second output terminal connected to the second input terminal of the first pulse generation module. The second pulse generation module is used to generate the first even pulse signal and the first odd pulse signal respectively based on the received second even pulse signal, second odd pulse signal, even data signal and odd data signal.

8. The driving circuit according to claim 7, characterized in that, The second pulse generation module is used to respond to the second even pulse signal and generate the first even pulse signal when the even data signal is an effective level signal; the second pulse generation module is used to respond to the second odd pulse signal and generate the first odd pulse signal when the odd data signal is an effective level signal.

9. The driving circuit according to claim 8, characterized in that, The effective level signal of the even data signal and the effective level signal of the odd data signal are both high level signals.

10. The driving circuit according to claim 7, characterized in that, Also includes: A rising edge detection module, wherein the first input terminal of the rising edge detection module is used to receive the first data strobe signal, the second input terminal of the rising edge detection module is used to receive the second data strobe signal, the third input terminal of the rising edge detection module is used to receive the readout strobe signal, the first output terminal of the rising edge detection module is connected to the first input terminal of the second pulse generation module, and the second output terminal of the rising edge detection module is connected to the second input terminal of the second pulse generation module; The rising edge detection module is used to generate the second even pulse signal and the second odd pulse signal based on the received first data gating signal, the second data gating signal, and the readout gating signal, respectively.

11. The driving circuit according to claim 10, characterized in that, When the readout strobe signal is a valid level signal, the rising edge detection module is used to respond to the rising edge of the first data strobe signal and generate the second even pulse signal; the rising edge detection module is also used to respond to the rising edge of the second data strobe signal after generating the second even pulse signal and generate the second odd pulse signal.

12. The driving circuit according to claim 11, characterized in that, The effective level signal of the readout strobe signal is a high level signal.

13. A memory, characterized in that, Includes the driving circuit as described in any one of claims 1-12.

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